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JPS634714B2 - - Google Patents
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JPS634714B2 - - Google Patents

Info

Publication number
JPS634714B2
JPS634714B2 JP55187283A JP18728380A JPS634714B2 JP S634714 B2 JPS634714 B2 JP S634714B2 JP 55187283 A JP55187283 A JP 55187283A JP 18728380 A JP18728380 A JP 18728380A JP S634714 B2 JPS634714 B2 JP S634714B2
Authority
JP
Japan
Prior art keywords
sealing cap
semiconductor chip
package
concave portion
polyimide resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55187283A
Other languages
Japanese (ja)
Other versions
JPS57112055A (en
Inventor
Tetsushi Wakabayashi
Kyoshi Muratake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55187283A priority Critical patent/JPS57112055A/en
Publication of JPS57112055A publication Critical patent/JPS57112055A/en
Publication of JPS634714B2 publication Critical patent/JPS634714B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00Arrangements for thermal protection or thermal control
    • H10W40/20Arrangements for cooling
    • H10W40/22Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 本発明は低熱抵抗性の、集積回路(以下ICと
略称する)用パツケージの新規な構造に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel structure of a package for an integrated circuit (hereinafter abbreviated as IC) with low thermal resistance.

近年のICはますます高密度化されて来る傾向
にあり、これにともなつて、当然発熱量も大とな
つて来ている。このICにおける発熱すなわち温
度上昇は大規模集積回路(LSI)においては一層
顕著であつて、このような温度上昇が伴うと、第
1には該IC中の能動素子の動作点がずれ、第2
には論理演算速度が低下し、したがつて第3には
S/N比が劣化していわゆるノイズ・マージンが
減少する、などの不都合が生じるばかりでなく、
第4にはICの寿命を短くするといつた問題が生
じ、このためICの放熱、換言すれば低温保持と
いつたことをいかにして実現するかが現在重要な
問題となつて来ている。
In recent years, ICs have become more and more densely packed, and along with this, their heat output has naturally increased. This heat generation, or temperature rise, in an IC is even more noticeable in large-scale integrated circuits (LSI), and when such a temperature rise is accompanied, firstly, the operating point of the active elements in the IC shifts, and secondly, the operating point of the active element in the IC shifts.
This not only causes inconveniences such as a decrease in logic operation speed and thirdly a deterioration of the S/N ratio and a reduction in the so-called noise margin.
Fourth, problems arise when the lifespan of an IC is shortened, and for this reason, how to dissipate heat from the IC, or in other words, maintain low temperatures, is currently becoming an important issue.

第1図は従来のICの側断面図であつて、たと
えば論理回路などが組込まれている半導体チツプ
2は、絶縁性のステム部材1に堀り込まれた通常
キヤビテイと称される凹部中央付近に設置され、
その半導体チツプ2上の図示しないボンデイング
パツドは、外部導出端子5との間にたとえば金線
などのボンデイングワイヤ3を用いて、いわゆる
ワイヤボンデイングがなされているだけで、放熱
という問題に関しては従来は未だ不充分であつ
た。ただし第1図中に4として示したものは、上
記ICの上部を覆う封じ用キヤツプである。
FIG. 1 is a side sectional view of a conventional IC, in which a semiconductor chip 2 in which, for example, a logic circuit or the like is incorporated is located near the center of a recess, usually called a cavity, dug into an insulating stem member 1. installed in
The bonding pad (not shown) on the semiconductor chip 2 is connected to the external lead-out terminal 5 using a bonding wire 3 such as a gold wire, so-called wire bonding. It was still insufficient. However, what is shown as 4 in FIG. 1 is a sealing cap that covers the top of the IC.

本発明は、こうした点に鑑みてなされたもので
上記の封じ用キヤツプ4の所定部分を上面から見
て凹状にして、前記半導体チツプ2の上面2aと
熱的に接触せしめ、該封じ用キヤツプ4に一種の
放熱板としての機能をもたせ、これによつて前記
半導体チツプ2の温度上昇を抑制せんとするもの
であり、第2図以下の図面を用いて詳述する。
The present invention has been made in view of these points, and a predetermined portion of the sealing cap 4 is formed into a concave shape when viewed from above, and is brought into thermal contact with the upper surface 2a of the semiconductor chip 2. This is intended to serve as a kind of heat sink, thereby suppressing the temperature rise of the semiconductor chip 2, and will be described in detail with reference to FIG. 2 and subsequent drawings.

第2図は本発明に係るIC用パツケージの側断
面図を示したもので、前記第1図と同等部位には
同一符号を付して示してある。この第2図に示し
たパツケージと第1図に示したパツケージとの間
の相異点は、封じ用キヤツプ4の半導体チツプ直
上部に、該パツケージの上部より見て凹型の部分
8を設け、かつ該凹型部の低面を緩衝性を有し、
かつ熱抵抗の低い絶縁性の物質たとえばポリイミ
ド樹脂の層9を介して前記半導体チツプの上面に
熱的に接触させたところにある。
FIG. 2 shows a side cross-sectional view of an IC package according to the present invention, in which the same parts as in FIG. 1 are given the same reference numerals. The difference between the package shown in FIG. 2 and the package shown in FIG. 1 is that the sealing cap 4 is provided with a concave portion 8 just above the semiconductor chip when viewed from the top of the package. and the lower surface of the concave portion has a cushioning property,
It is in thermal contact with the upper surface of the semiconductor chip via a layer 9 of an insulating material with low thermal resistance, such as polyimide resin.

上述の封じ用キヤツプの凹部底面は該キヤツプ
の弾性でもつて半導体チツプ2の上面に押しつけ
る型で圧着させるのであるが、この場合半導体チ
ツプ2の上部表面は通常PSG(リンケイ酸ガラ
ス)層で厚く保護されているために、上記半導体
チツプ2の上部に構成されている能動ならびに受
動素子すなわちトランジスタ、ダイオード、抵抗
類これらを接続するたとえばアルミニウム(Al)
配線等は、上記の圧着による圧力で損なわれるこ
とはない。
The bottom surface of the concave portion of the sealing cap described above is pressed against the top surface of the semiconductor chip 2 by the elasticity of the cap, but in this case, the top surface of the semiconductor chip 2 is usually protected with a thick layer of PSG (phosphosilicate glass). Because of this, active and passive elements such as transistors, diodes, and resistors configured on the upper part of the semiconductor chip 2 are connected to each other, for example, using aluminum (Al).
Wiring and the like will not be damaged by the pressure caused by the above-mentioned crimping.

しかも上述のPSG保護膜の上部、すなわち半
導体チツプの上面は、前述したごとく、ポリイミ
ド樹脂層9によつてさらに覆われているので、半
導体チツプ2の上部構成物の損傷がないばかりで
なく、周知のポリイミドの耐放射線性から、こう
した構造をとることにより、このICは放射線に
対する抵抗性をも備えるようになる。
Moreover, since the upper part of the above-mentioned PSG protective film, that is, the upper surface of the semiconductor chip, is further covered with the polyimide resin layer 9 as described above, not only the upper components of the semiconductor chip 2 are not damaged, but also the well-known Due to the radiation resistance of polyimide, this structure also makes the IC resistant to radiation.

封じ用キヤツプの凹部底面にはハンダクラツド
をほどこしておき、同時にポリイミド樹脂の上部
表面にはたとえばアルミニウム・銅(Al―Cu)
あるいはチタン・タングステン・ニツケル(Ti
―W―Ni)などの合金を蒸着によつて被着せし
め、上記封じ用キヤツプ4を所定の温度すなわち
ハンダの融点にまで加熱すれば、ポリイミド樹脂
上面の蒸着金属膜と封じ用キヤツプの凹部底面と
はハンダ付けされるので、放熱には一層の効果が
上がる。この場合ポリイミド樹脂は450℃の耐熱
性を有するから、通常の低融点ハンダの融点には
充分耐えうるものであり、ポリイミド樹脂が上記
のハンダ付け工程による熱的損傷を受けることは
ない。
Solder cladding is applied to the bottom of the concave part of the sealing cap, and at the same time, a layer of aluminum/copper (Al-Cu), for example, is applied to the top surface of the polyimide resin.
Or titanium, tungsten, nickel (Ti
-W--Ni) is deposited by vapor deposition and the sealing cap 4 is heated to a predetermined temperature, that is, the melting point of the solder, so that the vapor-deposited metal film on the top surface of the polyimide resin and the bottom surface of the recess of the sealing cap are heated. Since it is soldered, heat dissipation is even more effective. In this case, since the polyimide resin has a heat resistance of 450° C., it can sufficiently withstand the melting point of ordinary low-melting point solder, and the polyimide resin will not be thermally damaged by the above-mentioned soldering process.

また上記ポリイミド樹脂のかわりに普通のパワ
ートランジスタに用いられるいわゆる接合部保護
レジン(Junction Coating Resin:以下JCRと
略称する)を用いてもよく効果は同等に期待でき
る。なお前記封じ用キヤツプ4の材料としては熱
伝導性が高くハンダの乗りが良好な金属板が望ま
しく、その厚さとしてはたとえば0.2〜0.5mm厚の
ものが好ましい。
Furthermore, instead of the above-mentioned polyimide resin, a so-called junction coating resin (hereinafter abbreviated as JCR) used in ordinary power transistors may be used, and the same effect can be expected. The sealing cap 4 is desirably made of a metal plate having high thermal conductivity and good solderability, and preferably has a thickness of, for example, 0.2 to 0.5 mm.

第3図は本発明の一つの変形実施例としてのパ
ツケージの構造を示したもので、封じ用キヤツプ
4の端部に10で示したような折り曲げ段を設け
該端部の第3図中に示したdなる幅を絶縁性のス
テム部材1の上部部材1a,1bの上面の幅に略
等しく設定しておく。そして上部部材1a,1b
の上面をメタライズしておき、ハンダ11によつ
て該メタライズ部と前記封じ用キヤツプ4の端部
底面とをハンダ付けする。
FIG. 3 shows the structure of a package as a modified embodiment of the present invention, in which a folding step as shown in FIG. 3 is provided at the end of the sealing cap 4 as shown in FIG. The width d shown is set to be approximately equal to the width of the upper surface of the upper members 1a and 1b of the insulating stem member 1. And upper members 1a, 1b
The upper surface of the sealing cap 4 is metallized, and the metallized portion and the bottom surface of the end of the sealing cap 4 are soldered with solder 11.

かくすれば上記折り曲げ段10はステム部材1
の左右端に位置する2つの上部部材1a,1bの
間にはまり込む。すなわちこの場合には上記上部
部材1a,1bは封じ用キヤツプ4の位置決め部
材としての役割を演じるから、該封じ用キヤツプ
4の凹部底面4bは正しく半導体チツプ2上に塗
布されたポリイミド樹脂層9の上部に位置するよ
うになり、上記キヤツプ4の凹部側面4aがボン
デイングワイヤ3と接触するような事故を未然に
防止することができる。
In this way, the above-mentioned folding step 10 becomes the stem member 1.
It fits between the two upper members 1a and 1b located at the left and right ends of. That is, in this case, since the upper members 1a and 1b play the role of positioning members for the sealing cap 4, the bottom surface 4b of the concave portion of the sealing cap 4 is correctly aligned with the polyimide resin layer 9 coated on the semiconductor chip 2. This makes it possible to prevent an accident in which the concave side surface 4a of the cap 4 comes into contact with the bonding wire 3.

またさらに上記キヤツプの第3図中において4
Cとして示した凹部空間に新たに別の放熱スタツ
ドを立てた上で、放熱用フインを取り付ければ放
熱効果は一層向上する。
Furthermore, in Figure 3 of the above cap, 4
If another heat dissipation stud is newly erected in the recessed space shown as C and a heat dissipation fin is attached, the heat dissipation effect will be further improved.

以上に述べた本発明に係るIC用パツケージを
用いた実際の実験結果によれば、該ICの熱抵抗
は、上記の放熱フインを立てない状態においてさ
えも、およそ10゜/Wという低い値となることが
判明している。そしてこのような形状のICパツ
ケージは、封止用キヤツプ4のほぼ中央部を単に
凹状にするだけでよく、特に他の製造工程、マウ
ント工程等に大幅な変更を要さないので低価格で
大きな成果が得られるものであるから実用上多大
の効果が期待できる。
According to actual experimental results using the IC package according to the present invention described above, the thermal resistance of the IC is as low as approximately 10°/W even when the heat dissipation fins are not erected. It is clear that this will happen. To create an IC package with this shape, it is sufficient to simply make the almost central part of the sealing cap 4 concave, and it does not require any major changes in other manufacturing processes or mounting processes, so it is inexpensive and large. Since the results can be obtained, great practical effects can be expected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来構造のICパツケージの側断面図、
第2図は本発明に係る第1の実施例としてのIC
パツケージの側断面図、第3図は本発明の第2の
実施例としてのICパツケージの側断面図である。 1:絶縁性のステム部材、1a,1b:上部部
材、2:半導体チツプ、3:ボンデイングワイ
ヤ、4:封じ用キヤツプ、5:外部導出端子、
8:封じ用キヤツプの凹型部分、9:ポリイミド
樹脂、10:封じ用キヤツプの折り曲げ段。
Figure 1 is a side sectional view of an IC package with a conventional structure.
FIG. 2 shows an IC as a first embodiment of the present invention.
FIG. 3 is a side sectional view of an IC package as a second embodiment of the present invention. 1: Insulating stem member, 1a, 1b: Upper member, 2: Semiconductor chip, 3: Bonding wire, 4: Sealing cap, 5: External lead-out terminal,
8: Concave portion of the sealing cap, 9: Polyimide resin, 10: Folding step of the sealing cap.

Claims (1)

【特許請求の範囲】 1 絶縁性ステム部材上に集積回路が形成された
側を上面にして半導体チツプを設置して、該ステ
ム部材の上部を封止用キヤツプで覆つてなる集積
回路用パツケージにおいて、 前記封止用キヤツプを導熱性の材料で構成し、
かつ該封止用キヤツプの半導体チツプ直上部に凹
型の部分を設けて、該凹型部分の底面が、前記半
導体チツプの上面のワイヤが接続された領域以外
の部分と接触する形でステム封止をしてなること
を特徴とする集積回路用パツケージ。
[Claims] 1. An integrated circuit package comprising: 1. A semiconductor chip is placed on an insulating stem member with the side on which the integrated circuit is formed facing upward; and the upper part of the stem member is covered with a sealing cap. , the sealing cap is made of a heat conductive material,
Further, a concave portion is provided in the sealing cap directly above the semiconductor chip, and the stem is sealed in such a manner that the bottom surface of the concave portion is in contact with a portion of the top surface of the semiconductor chip other than the area to which the wire is connected. An integrated circuit package characterized by:
JP55187283A 1980-12-29 1980-12-29 Integrated circuit package Granted JPS57112055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55187283A JPS57112055A (en) 1980-12-29 1980-12-29 Integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55187283A JPS57112055A (en) 1980-12-29 1980-12-29 Integrated circuit package

Publications (2)

Publication Number Publication Date
JPS57112055A JPS57112055A (en) 1982-07-12
JPS634714B2 true JPS634714B2 (en) 1988-01-30

Family

ID=16203279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55187283A Granted JPS57112055A (en) 1980-12-29 1980-12-29 Integrated circuit package

Country Status (1)

Country Link
JP (1) JPS57112055A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62114253A (en) * 1985-11-13 1987-05-26 Nec Corp Heat sink structure for integrated circuit
US4924353A (en) * 1985-12-20 1990-05-08 Hughes Aircraft Company Connector system for coupling to an integrated circuit chip
JP2599233B2 (en) * 1991-11-18 1997-04-09 富士通株式会社 Semiconductor device
JPH08124633A (en) * 1994-10-24 1996-05-17 Nec Corp Connector
US5909056A (en) * 1997-06-03 1999-06-01 Lsi Logic Corporation High performance heat spreader for flip chip packages
JP2004140289A (en) * 2002-10-21 2004-05-13 Funai Electric Co Ltd Heat radiation structure of electronic component and disk drive device comprising it
JP5309732B2 (en) * 2008-07-02 2013-10-09 日本精工株式会社 Electric power steering device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5531494B2 (en) * 1971-09-13 1980-08-19

Also Published As

Publication number Publication date
JPS57112055A (en) 1982-07-12

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