JPS634716B2 - - Google Patents
Info
- Publication number
- JPS634716B2 JPS634716B2 JP56075908A JP7590881A JPS634716B2 JP S634716 B2 JPS634716 B2 JP S634716B2 JP 56075908 A JP56075908 A JP 56075908A JP 7590881 A JP7590881 A JP 7590881A JP S634716 B2 JPS634716 B2 JP S634716B2
- Authority
- JP
- Japan
- Prior art keywords
- pull
- down resistor
- input terminal
- input
- transfer gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体集積回路（以下LSIと略す）に
関し、特にLSI上の入力端子の構成に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit (hereinafter abbreviated as LSI), and particularly to the configuration of input terminals on the LSI.
従来、キーダイオードマトリツクスなどをLSI
の入力端子に入力する場合、外付け部品としてプ
ルダウン抵抗が必要であつた。 Conventionally, key diode matrices, etc. were manufactured using LSI.
When inputting to the input terminal of , a pull-down resistor was required as an external component.
又、プルダウン抵抗付きのLSIも電子式卓上計
算機用のLSIなど用途が限られたものにはある。
しかし、汎用として使用されるマイクロコンピユ
ータでは、何を入力信号として用いるかユーザー
が決定するため、プルダウン抵抗をあらかじめ
LSIに内蔵しておくと、ユーザーにとつて不便な
場合が起こつてくる。 Additionally, LSIs with pull-down resistors are available for limited uses, such as LSIs for electronic desktop calculators.
However, in general-purpose microcomputers, the user decides what to use as an input signal, so pull-down resistors are installed in advance.
If it is built into an LSI, it may be inconvenient for the user.
本発明はこのような事情に鑑みてなされたもの
で、入力端子にプルダウン抵抗を外付する必要が
なく、しかも汎用性のある半導体集積回路を提供
することを目的とする。 The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor integrated circuit that does not require an external pull-down resistor to an input terminal and is versatile.
本発明によれば、入力端子と所定電位間にトラ
ンスフアーゲートを介して挿入されたプルダウン
抵抗及び前記トランスフアーゲートを制御するレ
ジスタを備えてなることを特徴とする半導体集積
回路が得られる。 According to the present invention, there is obtained a semiconductor integrated circuit characterized in that it includes a pull-down resistor inserted between an input terminal and a predetermined potential via a transfer gate, and a register for controlling the transfer gate.
レジスタ出力によつてトランスフアーゲートの
導通／非導通を制御すれば、予め挿入されている
プルダウン抵抗を入力端子に接続するか、非接続
にするか選択できるので極めて便利である。 Controlling the conduction/non-conduction of the transfer gate by the register output is extremely convenient since it is possible to select whether the pull-down resistor inserted in advance is connected to the input terminal or not.
次に実施例に従い、図面を用いて本発明を詳細
に説明する。 Next, the present invention will be described in detail according to examples and with reference to the drawings.
図は本発明の一実施例を示す回路接続図で、半
導体集積回路の入力端子とその周辺部分を示すも
のである。プルダウン抵抗７が入力端子１に接続
か非接続か選択できる様にトランスフアゲートと
して選択トランジスタ８を作つておく。プルダウ
ン抵抗７を入力端子１に接続したい場合、データ
バス４に“１”の信号を乗せ、レジスタの一種で
あるプルダウン接続モードフリツプフロツプ６へ
の入力命令時に“１”となる入力制御線５でプル
ダウン接続モードフリツプフロツプ６に“１”を
書き込めば選択トランジスタ８が導通になり入力
端子１にプルダウン抵抗７が接続され、入力端子
１に中間レベルが入力されても選択トランジスタ
８、プルダウン抵抗７を通して入力端子１は
“０”にレベルが設定され、入力バツフアーイン
バータ２は“０”を読み取り内部バス３へ伝達し
ていく。又プルダウン抵抗７を非接続にしたい場
合は、プルダウン抵抗接続モードフリツプフロツ
プ６に“０”を書き込めばよい。なおこの例では
プルダウン抵抗７のゲートは電源電位９として、
そのトランジスタの導通時の抵抗を抵抗分として
用いている。 The figure is a circuit connection diagram showing an embodiment of the present invention, and shows an input terminal of a semiconductor integrated circuit and its surrounding parts. A selection transistor 8 is prepared as a transfer gate so that it can be selected whether the pull-down resistor 7 is connected or not connected to the input terminal 1. If you want to connect the pull-down resistor 7 to the input terminal 1, put a "1" signal on the data bus 4, and connect the input control line that becomes "1" when an input command is input to the pull-down connection mode flip-flop 6, which is a type of register. 5, pull-down connection mode When "1" is written in the flip-flop 6, the selection transistor 8 becomes conductive, and the pull-down resistor 7 is connected to the input terminal 1. Even if an intermediate level is input to the input terminal 1, the selection transistor 8, The level of the input terminal 1 is set to "0" through the pull-down resistor 7, and the input buffer inverter 2 reads "0" and transmits it to the internal bus 3. If it is desired to disconnect the pull-down resistor 7, it is sufficient to write "0" to the pull-down resistor connection mode flip-flop 6. In this example, the gate of the pull-down resistor 7 is set to the power supply potential 9,
The resistance when the transistor is turned on is used as the resistance component.
上記の様に、ユーザーのプログラムによりプル
ダウン抵抗７が入力端子１に接続か非接続かの選
択が可能となる。 As described above, it is possible to select whether the pull-down resistor 7 is connected or not connected to the input terminal 1 according to the user's program.
本例ではマイクロコンピユータ内部の命令でプ
ルダウン抵抗接続モードフリツプフロツプ６をセ
ツト又はリセツトしたが、たとえばそのための端
子を設けて外部より制御することも可能である。 In this example, the pull-down resistor connection mode flip-flop 6 is set or reset by a command inside the microcomputer, but it is also possible to provide a terminal for this purpose and control it from the outside.
図は本発明の一実施例を示す回路接続図であ
り、１は入力端子、２は入力バツフアーインバー
タ、３は内部バスへ、４はデータバスへ接続され
る。５は入力制御線、６はプルダウン抵抗接続モ
ードフリツプフロツプ、７はプルダウン抵抗を構
成するトランジスタ、８は選択トランジスター、
９は電源電位。
The figure is a circuit connection diagram showing an embodiment of the present invention, in which 1 is an input terminal, 2 is an input buffer inverter, 3 is connected to an internal bus, and 4 is connected to a data bus. 5 is an input control line, 6 is a pull-down resistor connection mode flip-flop, 7 is a transistor forming the pull-down resistor, 8 is a selection transistor,
9 is the power supply potential.
Claims (1)
トを介して挿入されたプルダウン抵抗及び前記ト
ランスフアゲートを制御するレジスタを備えてな
ることを特徴とする半導体集積回路。1. A semiconductor integrated circuit comprising a pull-down resistor inserted between an input terminal and a predetermined potential via a transfer gate, and a register for controlling the transfer gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56075908A JPS57190347A (en) | 1981-05-20 | 1981-05-20 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56075908A JPS57190347A (en) | 1981-05-20 | 1981-05-20 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57190347A JPS57190347A (en) | 1982-11-22 |
| JPS634716B2 true JPS634716B2 (en) | 1988-01-30 |
Family
ID=13589901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56075908A Granted JPS57190347A (en) | 1981-05-20 | 1981-05-20 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57190347A (en) |
-
1981
- 1981-05-20 JP JP56075908A patent/JPS57190347A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57190347A (en) | 1982-11-22 |
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