JPS6347370B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a two-phase pulse 1/2 frequency division system that divides two pulses with a phase difference of 90 degrees to 1/2, for example, for determining the direction of forward rotation and reverse rotation and for counting. Concerning vessels.

Conventionally, as shown in Figure 1, an external command circuit (e.g.
The command pulse from the CPU) 1 is set in the deviation counter of the digital control device 2, and after D/A conversion, the driven object of the numerically controlled machine tool is driven via the servo motor control device 3 and the servo motor 4. ,
For example, the moving direction and moving distance of the table 5 can be detected by feeding back two pulses with a phase difference of 90 degrees output from a pulse generator 6 connected to a servo motor 4 to a deviation counter of the digital controller 2. It is carried out by Incidentally, it may be necessary to feed back the output pulses of the pulse generator 6 to the servo motor control device 3 as well. In this case, if the frequency of the output pulse of the pulse generator 6 is higher than the maximum input frequency of the servo motor control device 3,
Pulse generator 6 in servo motor control device 3
It is not possible to feed back the pulse of As a countermeasure to this problem, it is possible to lower the rotation speed so that the rated frequency, which is the frequency of pulses when the pulse generator 6 is at the rated rotation speed, is below the maximum input frequency of the servo motor control device 3.
When the rotation speed is lowered, the position detection accuracy of the pulse generator 6 is reduced. Furthermore, it is sufficient to install two pulse generators 6, one for the digital control device 2 and one for the servo motor control device 3, but this is disadvantageous in terms of cost. Furthermore, if the rated frequency of the pulse generator 6 is lowered, the accuracy of speed control of the servo motor control device 3 will deteriorate.

The present invention was proposed in view of these problems, and is a two-phase pulse 1/2 method that divides the frequency of two input pulses of a pulse generator with a phase difference of 90° into 1/2 without shifting the phase. The purpose is to provide peripheral equipment.

This type of frequency dividing circuit is disclosed in Japanese Patent Publication No. 52-4710. The frequency dividing circuit disclosed in this Japanese Patent Publication No. 52-4710 divides the frequency into 1/4, 1/8, etc.
In order to divide the frequency into 2, a differentiating circuit, a switching circuit, etc. are required, which makes the circuit complicated. In addition, in this frequency dividing circuit, when one input pulse rises when the rotation direction is switched, the servo motor makes a minute movement (operation/
(stop), unnecessary pulses appear continuously in one of the input pulses. This pulse appears in the 1/4 frequency-divided and 1/8 frequency-divided output pulses, causing a count error in the output pulses, and as this count error is accumulated, the control position gradually shifts.

The two-phase pulse 1/2 frequency divider of the present invention overcomes the drawbacks of the conventional frequency dividing circuit described above, and is capable of dividing the frequency by 1/2, so that unnecessary pulses are added to one of the input pulses during minute movements of the motor. Even if this pulse appears, the influence of this pulse does not appear on the output pulse, and the control position is prevented from shifting due to the output pulse.

The present invention will be described below with reference to drawings of embodiments. FIG. 2 is a block diagram of a two-phase pulse 1/2 frequency divider according to one embodiment of the present invention. T ₁ and T ₂ are each a 90° phase difference output from a pulse generator attached to a rotating body, such as a motor,
Both are input terminals for the first input pulse S ₁ and the second input pulse S ₂ with a duty cycle of 0.5. 1
are differential pulses S ₉ , S ₁₂ corresponding to the rising edge of the second input pulse S ₂ and differential pulses S ₁₀ , corresponding to the falling edge of the second input pulse S 2 .
This is a differential pulse generation circuit that outputs _S11 . 2 is the differential pulse prohibition signal when the prohibition condition is met.
This is a differential pulse inhibition circuit that prohibits generation of differential pulses S ₁₀ and S ₁₂ at S ₇ and S ₈ . Reference numeral 3 denotes a forward/reverse determining circuit which has two determining circuits and outputs respective forward/reverse determining signals S ₃ and S ₄ to the differential pulse inhibition circuit 2 and the forward/reverse switching signal generating circuit 5 . The forward/reverse switching signal generation circuit 5 outputs a forward switching signal S ₅ and a reverse switching signal S ₆ based on the forward/reverse determination signals S ₃ and S ₄ . 4 is the positive side switching signal S ₅
The differential pulses S ₉ and S ₁₀ are output as pulses respectively.
The differential pulses S ₁₁ and S ₁₂ are outputted as S 14 and S ₁₃ , respectively, and the differential pulses S ₁₁ and S ₁₂ are output as S ₁₄ and
This is a differential pulse output switching circuit that outputs as output _S13 . 6 is a first output pulse S ₁₅ whose logic level is inverted every time the differential pulse S 13 is output, and the frequency of the first input pulse S ₁ is divided by 1/2 _, and every time the differential pulse S ₁₄ is output. A second output pulse whose logic level is inverted and which divides the second input pulse S ₂ by 2 and has an in-phase phase difference of 90° with respect to the first output pulse S ₁₅
This is an output pulse generation circuit that generates _S16 respectively. The first output pulse S ₁₅ and the second output pulse S ₁₆ generated by the output pulse generation circuit 6 are output from output terminals T ₃ and T ₄ , respectively, to the digital control device 2 shown in FIG. 1, for example.

FIG. 3 shows a two-phase pulse 1/1 according to an embodiment of the present invention.
FIG. 2 is a circuit diagram corresponding to the block diagram of FIG. 2 of a frequency divider by two; _IN1 is an inverter circuit that inverts the second input pulse _S2 . FF ₁ is the first output pulse
This is a D-flip-flop which takes _S1 as the D input, the second input pulse _S2 as the CP input, and outputs the forward/reverse determination signal _S3 from the Q output. FF ₂ is the first input pulse
S ₁ as D input, second input pulse S ₂ inverted signal ₂
This is a D-flip-flop which outputs the forward/reverse determination signal _S4 from the Q output as the CP input. EOR ₁ is an exclusive OR circuit that takes the exclusive OR of the first input pulse S ₁ and the forward/reverse determination signal S ₃ and outputs the differential pulse inhibition signal S ₇ . EOR ₂ is an exclusive OR circuit that takes the exclusive OR of the first input pulse S ₁ and the forward/reverse determination signal S ₄ and outputs the differential pulse inhibition signal S ₈ . IN ₂ is the forward/reverse judgment signal
This is an inverter circuit that inverts _S3 . _IN3 is an inverter circuit that inverts the forward/reverse determination signal _S4 . AND ₁ is an AND circuit that performs the logical product of the forward/reverse determination signal S ₃ and the inverted signal ₄ of the forward/reverse determination signal S ₄ .
AND ₂ is an AND circuit that performs the logical product of the inverted signal ₃ of the forward/reverse determination signal S ₃ and the forward/reverse determination signal S ₄ . FF ₃ PR (presets) the output signal of the AND circuit AND ₁
Input, output signal of AND circuit AND ₂ as CL (clear) input, positive side switching signal S ₅ , reverse side switching signal
This is a D-flip-flop that outputs _S6 from the Q output and the output, respectively. IN ₄ is the second input pulse
This is an inverter circuit that inverts _S2 . _AND3 is an AND circuit that performs a logical product of the positive side switching signal _S5 and the differential pulse inhibition signal _S8 . AND ₄ is the positive side switching signal
This is an AND circuit that takes the AND of _S5 and the differential pulse inhibition signal _S7 . AND ₅ is an AND circuit that performs the logical product of the reverse side switching signal S ₆ and the differential pulse inhibition signal S ₇ .
AND ₆ is the reverse side switching signal S ₆ and the differential pulse inhibition signal S ₈
This is an AND circuit that performs the logical product of . FF ₄ is a D-flip-flop in which the output signal of the AND circuit AND ₃ is used as the D input, the second input pulse S ₂ is used as the CP input, and the Q output and CL input are _connected . A differential pulse _S9 corresponding to the rising edge of is output. FF ₅ has the output signal of the AND circuit AND ₄ as the D input, the inverted signal ₂ of the second input pulse S ₂ which is the output signal of the inverter circuit IN ₄ as the CP input, and the D- to which the Q output and CL input are connected. The flip-flop outputs a differential pulse _S10 corresponding to the falling edge of the second input pulse _S2 during normal rotation. FF ₆ is the output signal of AND circuit AND ₅ as D input, and inverter circuit.
The inverted signal ₂ of the second input pulse S2, which is the output signal of IN _{4 ,} is used as the CP input, and the Q output and CL input are connected to the D-flip- _flop . A corresponding differential pulse _S11 is output. FF ₇ uses the output signal of the AND circuit AND ₆ as the D input, the second input pulse S ₂ as the CP input, and the Q
A D-flip-flop whose output and CL input are connected outputs a differential pulse _S12 in response to the rising edge of the second input pulse _S2 during reverse rotation. _OR1 takes the logical sum of the output signal _S10 of the D-flip-flop _FF5 and the output signal _S12 of the D-flip-flop _FF7 ,
This is an OR circuit that outputs a differential pulse _S13 . OR ₂
is the output signal _S9 of D-flip-flop _FF4 and D-
This is an OR circuit that takes the AND of the output signal _S11 of the flip-flop _FF6 and outputs a differential pulse _S14 .
FF ₈ uses the output signal S ₁₃ of OR circuit OR ₁ as CP input,
A D-flip-flop has a Q output connected to a D input, and a first output pulse _S15 whose logic level is inverted each time a differential pulse _S13 appears is outputted from the Q output. FF ₉ is the differential pulse of OR circuit OR ₂
A D-flip-flop has _S14 as a CP input and an output connected to a D input, and a second output pulse _S16 whose logic level is inverted every time the differential pulse _S14 appears is outputted from the Q output.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to the timing chart shown in FIG. 4. In FIG. 3, it is assumed that the rotation of the motor whose rotation is detected by the pulse generator is switched from normal rotation to reverse rotation at time _t0 .
The phase of the first input pulse S ₁ is equal to that of the second input pulse
From the phase of S ₂ , it is the forward side that is 90 degrees ahead during forward rotation, and the opposite side that is 90 degrees behind during reverse rotation. Therefore, D
- The forward/reverse determination signal _S3 , which is the output signal of the flip-flop _FF1 , is the first second input pulse _S2 during reversal.
It remains "high" until time _t3 , which is the rising edge of , and then becomes "low". Conversely, the forward/reverse determination signal _S4 , which is the output signal of the D-flip-flop _FF2 , is "low" until time _t1 , which is the falling edge of the second input pulse _S2 , when switching from forward rotation to reverse rotation. After that, it becomes “high”. These forward/reverse determination signals S ₃ and S ₄ are inverted by inverter circuits IN ₃ and IN ₃ , respectively, and then sent to AND circuits AND ₁ and
Since it is input to AND ₂ , the output signal of AND circuit AND ₁ is "high" until time t ₃ and becomes "low" thereafter, and the output signal of AND circuit AND ₂ is "low" until time t ₃ and becomes "high" thereafter. ” becomes. The positive side switching signal S ₅ is the output signal of the D-flip-flop FF ₃ ,
The reverse side switching signal _S6 is an AND circuit _AND1 ,
Same as AND ₂ output signal. On the other hand, the differential pulse inhibition signal _S7 , which is the output signal of the exclusive OR circuit EOR ₁ , is the first input pulse _S1 and the time _t3.
The polarities are different up to, and after time _t3 , the polarities become the same. The differential pulse inhibition signal _S8 , which is the output signal of the exclusive OR circuit _EOR2 , has the same polarity as the first input pulse _S1 until time _t1 , and then the polarity is reversed. The output signal of the AND circuit _AND3 is the differential pulse inhibition signal _S8 , which is the output signal of the exclusive OR circuit _EOR2 , which is set to "low" after time _t1 . D-flipflop FF ₄ is Q
Since the output is connected to the CL input, every time the second input pulse _S2 is input as the CP input, a differential pulse _S9 is output in accordance with the rising edge of the second input pulse S2. Similarly D
- Flip-flop FF ₅ outputs a differential pulse S ₁₀ corresponding to the falling edge of the second input pulse S ₂ during normal rotation;
The flip-flop _FF6 outputs a differential pulse _S11 corresponding to the falling edge of the second input pulse _S2 at the time of reverse rotation, and converts it into a D-
Flip-flop FF ₇ outputs a differential pulse S ₁₂ in response to the rise of the second input pulse S ₂ during reverse rotation. However, the times t ₁ and t ₃ when switching from forward rotation to reverse rotation
Differential pulses (indicated by broken lines) corresponding to the falling and rising edges of the second input pulse _S2 do not appear. Differential pulse S ₁₃ output from OR circuit OR ₁
are the differential pulse _S10 corresponding to the falling edge of the second input pulse _S2 during forward rotation and the second input pulse _S2 during reverse rotation.
It includes a differential pulse _S12 corresponding to the rising edge of . Differential pulse output from OR circuit OR _2
S14 is the differential pulse _S9 corresponding to the rising edge of the second input pulse _S2 during forward rotation and the second input pulse during reverse rotation.
The signal includes a differential pulse _S11 corresponding to the falling edge of _S2 . D-Flip-flop FF ₈ is OR circuit
Every time the differential pulse S ₁₃ from OR ₁ is input to the CP input, a first output pulse S ₁₅ whose output is inverted is output.
The D-flip-flop _FF9 outputs a second output pulse _S16 whose output is inverted every time the differential pulse _S14 is input to the CP input from the OR circuit _OR2 . The first and second output pulses S ₁₅ and S ₁₆ are pulses obtained by dividing the first input pulse S ₁ and the second input pulse S ₁ by 1/2, respectively, and have the same phase difference of 90°.

As described above, there are two detection devices for the first and second input pulses S ₁ and S ₂ and the first and second output pulses S ₁₅ and S ₁₆ of the two-phase pulse 1/2 frequency divider of the present invention. When the logic level of the first pulse of the phase pulse changes, a differential pulse on the positive side or the opposite side is generated depending on the logic level of the second pulse. For example, when the second pulse is at a high level at the rising edge of the first pulse, a positive side pulse is generated. A two-phase pulse detection device that generates an opposite pulse when the second pulse is at a high level at the falling edge of the first pulse is effective. 2 detected by this two-phase pulse detection device
Assuming that the number of input positive side pulses of phase input pulses is N _1F , the number of input reverse side pulses is N _1R , the number of output positive side pulses of two-phase output pulses is N _2F , and the number of output reverse side pulses is N _2R ,
The following relational expression holds true between these pulse numbers N _1F , N _1R , N _2F , and N _2R .

(1) For steady one-way operation on the forward or reverse side N _1F −K=2N _2F , N _1R −K=2N _2R ……… (K=1……N _1F , N _1R is an odd number) When K=0......When N _1F and N _1R are even numbers) (2) In the case of forward/reverse operation from the forward side to the reverse side, N _1F −N _1R 〜〜〜=2( N _2F −N _2R 〜〜 ~) ……… (3) In the case of forward/reverse operation from the reverse side to the positive side N _1R −N _1F 〜〜〜=2( N _2R −N _2F 〜〜〜) ……… In the formula, the minuend (− The underlined number) is the number of pulses before forward/reverse switching, and the subtracted number (underlined . . . ) is the number of pulses after forward/reverse switching.
The relationships between N _1F and N _2F and N _1R and N _2R are the same as in the formula. As a result of the above, even in forward and reverse repetitive operation,
|N _1F −N _1R |=2|N _2F −N _2R | Therefore, accurate position detection is possible.

FIG. 5 is a state transition diagram of the two-phase pulse 1/2 frequency divider of the present invention. The numbers in circles indicate the logic levels of the two-phase input pulses S ₁ and S ₂ from the left. Also, the part surrounded by the broken line shows that even if the logic levels of the two-phase first and second input pulses S ₁ and S ₂ change, the first and second output pulses do not change.
The logic levels of S ₁₅ and S ₁₆ do not change, and the numbers in parentheses to the right indicate the first and second output pulses S ₁₅ ,
S shows ₁₆ logical levels. The solid arrow line is
Clockwise is the first input pulse S ₁ (first output pulse S ₁₅ ) is the second input pulse S ₂ (second input pulse
In the counterclockwise direction, the first input pulse S ₁ (first output pulse S ₁₅ ) is the second input pulse _{S 2} (second output pulse S ₁₆ ) shows the “opposite side” where the phase is delayed.

The two-phase input pulses S ₁ , S ₂ and the two-phase output pulses S ₁₅ , S ₁₆ of the two-phase pulse 1/2 frequency divider of the present invention are detected by a two-phase pulse detection device (for example, when the second pulse is detected at the rising edge of the first pulse). When the first pulse is "1", a positive pulse is generated, and when the second pulse is "1", a reverse pulse is generated and counted. It is described below. However, two-phase input pulse
When S ₁ and S ₂ change from (1, 0) to (1, 1), count the positive pulse by +1 (represented as +1 in Figure 5), and change from (1, 1) to (1, 0). When it changed to
Count the opposite pulse by +1 (denoted as -1 in FIG. 5). Two-phase output pulse (S ₁₅ , S ₁₆ ) is (1, 0)
When it changes from (1, 1), the positive side pulse is +
1 count (represented as (+1) in Figure 5), (1,
When the pulse changes from 1) to (1, 0), the opposite pulse is counted by +1 (denoted as (-1) in FIG. 5).

(1) In the case of steady operation on the positive side In Figure 5, (S ₁ , S ₂ ) = (0, 1), (S ₁₅ , S ₁₆ )
Starting from = (1, 1), (S ₁ , S ₂ ) becomes (0, 0), (1, 0), (1, 1) (0, 1),
It changes sequentially from (0, 0), (1, 0), (1, 1) and returns to (0, 1). During this time, the positive pulse +1
Count twice. Also, (S ₁₅ , S ₁₆ ) is (0,
1), (0, 0), (1, 0) and then returns to (1, 1). During this time, the positive pulse (+1)
Count once.

(2) When switching from the normal side to the reverse side Starting point (S ₁ , S ₂ ) = (0, 1), (S ₁₅ , S ₁₆ ) =
(1, 1) (i) After n laps, (S ₁ , S ₂ ) = (0, 0), (S ₁₅ , S ₁₆
)
= When switching at (0, 1). (S ₁ , S ₂ ) moves n times from (0, 1) to (0, 1) on the positive side,
Enter the route (0, 0), (0, 1). Then, go through (1, 1), (1, 0) and enter the opposite route, (0, 0), (0, 1), (1, 1),
(1, 0). During this time, the positive pulse +1
is counted 2n times (N _1F = 2n) and the opposite pulse -1 is counted 2 times (N _1R = 2). Similarly, (S ₁₅ , S ₁₆ )
is (1, 1) after N rotations from (1, 1), (0,
1), (1, 1), (1, 0). During this time,
The positive pulse (+1) is counted n times (N _2F =n) and the reverse pulse (-1) is counted once (N _2R = 1).

(ii) After n laps, (S ₁ , S ₂ ) = (1, 1), (S ₁₅ , S ₁₆
)
= When switching at (0, 0). (S ₁ , S ₂ ) goes n times from (0, 1) on the positive side, and becomes (0, 0).
(1, 0), (1, 1), where (1,
0) route. and (0, 0),
Pass through (0, 1) and enter the opposite route (1, 1), (1, 0), (0, 0), (0, 1),
(1, 1), (1, 0). During this period, the positive side pulse +1 is applied (2n+1) times (N _1F = 2n+1),
Count the reverse pulse -1 three times (N _1R = 3). Similarly, (S ₁₅ , S ₁₆ ) rotates n times from (1, 1), (1, 1), (0, 1), (0, 0),
(0, 1), (1, 1), (1, 0). During this time, the positive side pulse (+1) is applied n times (N _2F =
N), reverse side pulse (-1) once (N _2R = 1)
Count.

As explained above, the present invention divides the frequency of two pulses with a phase difference of 90° into 1/2 while keeping the same phase. is small, the input pulses of the pulse generator can be fed back without lowering the rotation speed of the servo motor or the like to reduce position detection accuracy or adding a pulse generator. Also, since the present invention divides the input pulse frequency by 1/2, by connecting it in series, it divides the frequency of the input pulse into 1/2, 1/4, 1/8, 1/16, etc.
It becomes possible to divide the frequency of... Furthermore, in the present invention, even if a continuous pulse is output to one input pulse when there is a slight fluctuation in which the rotational direction of the motor is switched,
These pulses have no effect, and position control will not be disturbed. Note that the output pulse obtained by dividing the input pulse by 1/2 becomes symmetrical at a point delayed by half a cycle with respect to the forward/reverse switching point (Fig. 4 A), but since this is fixed, the integration will not occur even if the forward/reverse switching point is repeated. It will not be done.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional servo device, Figure 2 is a block diagram of a conventional servo device.
The figure is a block diagram of a two-phase pulse 1/2 frequency divider according to an embodiment of the present invention, FIG. 3 is a circuit diagram showing an embodiment of a circuit corresponding to the block diagram of FIG. 2, and FIG. FIG. 3 is a timing chart showing the waveforms of each part of the circuit diagram, and FIG. 5 is a state transition diagram of the two-phase pulse 1/2 frequency divider of the present invention. 11: Differential pulse generation circuit, 12: Differential pulse inhibition circuit, 13: Forward/reverse determination circuit, 14: Differential pulse output switching circuit, 15: Forward/reverse switching signal generation circuit,
16: Output pulse generation circuit.

Claims (1)

[Claims] 1. A differential pulse generation circuit that generates a first differential pulse and a second differential pulse at the leading edge and trailing edge of a second input pulse, respectively; and the previous logic of the second input pulse. The logic level of the first input pulse having a phase difference of 90° from the second input pulse when the level changes, and the logic level of the first input pulse immediately before the current logic level change of the second input pulse. a differential pulse prohibition circuit that prohibits output of the first differential pulse or the second differential pulse due to a change in the current logic level of the second input pulse when the logic levels are the same; and the second input pulse. a first determination circuit that maintains the logic level of the first input pulse at the leading edge of the current pulse until the leading edge of the next pulse of the second input pulse; and an inversion of the second input pulse. said first at the leading edge of the current pulse of the signal.
a forward/reverse determination circuit having a second determination circuit that holds the logic level of the input pulse until the leading edge of the next pulse of the inverted signal of the second input pulse; a forward/reverse switching signal generation circuit that generates first and second forward/reverse switching signals with the logic levels of the signals inverted; When, the first differential pulse and the second differential pulse are respectively a second differential pulse output and a first differential pulse output, and the second forward/reverse switching signal is the first differential pulse and the second differential pulse, a differential pulse output switching circuit that switches the first differential pulse and the second differential pulse to the first differential pulse output and the second differential pulse output, respectively, when the polarity is the same as that of the first differential pulse; Each time a pulse is output from the pulse output, the logic level is inverted, and the logic level of the first or second
A first latch circuit outputs a first output pulse obtained by dividing the input pulse by half, and the logic level is inverted every time a pulse is output from the second differential pulse output. An output pulse generator comprising a second latch circuit that outputs a second output pulse that has an in-phase phase difference of 90° with respect to the output pulse and is obtained by dividing the frequency of the first or second input pulse by 1/2. A two-phase pulse 1/2 frequency divider characterized by consisting of a circuit.