JPS6349320B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing junction-destructive PROM (programmable read-only memory).

Normally, information is written to PROM by the user. Therefore, the manufacturer needs to inspect it in an unwritten state. A junction destruction type memory cell is in an electrically open state unless the junction between the emitter and collector of the transistor is destroyed. Therefore, no matter which memory cell is selected, only the same information can be obtained at the output.

As a testing method in this case, conventionally, as shown in FIG. 1, read-only test memory cell groups TSTR ₁ and TSTR ₂ are added to the memory cell section. By sequentially reading out these test memory cell groups, the functionality of each circuit in the readout system is tested. Further, the test as to whether or not data can be normally written to the memory cells is performed by actually writing to the unwritten test memory cell groups TSTW ₁ and TSTW ₂ .

However, the above inspection method still cannot perform a complete inspection. That is, it was insufficient in the following points.

In the above read and write operations, it is unclear whether the write circuit is correctly selecting the bit line. For example, when reading a high level (junction breakdown) in a read test, the same high level will be output even if the other doubly selected cell is in an open state or in a junction breakdown state.

Furthermore, in the write test, double selection cannot be similarly detected because junction breakdown occurs in all test memory cells.

Furthermore, since no actual test is performed on the unwritten memory cells used by the user, it is impossible to detect any disconnection, deterioration of characteristics, etc.

The purpose of this invention is to provide a bond-breaking type with improved reliability.
The objective is to provide a PROM testing method.

According to the basic feature of the present invention, a current value that is less than or equal to the junction breakdown current of a transistor constituting the memory cell is applied to the test memory cell and/or the unwritten memory cell through the write circuit. The quality of the product is determined by reading the output terminal voltage of a current source circuit that supplies a voltage that causes breakdown between the emitters.

Hereinafter, this invention will be explained in detail together with examples.

In this invention, a joint breaking type as shown in FIG.
In the PROM, the read test and write test as described above are performed using the test memory cell group as described above. Then, the following inspection method is added.

In other words, as shown in the circuit diagram of the main part _of the embodiment in _FIG . The current is supplied at a small current value (for example, about 20 mA) under a voltage (for example, 20 volts) V _CC that causes breakdown (primary breakdown) between the collector and emitter. Then, the output terminal voltage of this constant current circuit _I0 , in other words, the voltage value at the output terminal _OUT1 is read by the comparators _C1 and _C2 .
A preset upper limit value V _H and lower limit value V _L are applied to these comparators C ₁ and C _2, respectively, and the judgment output is input to the AND gate circuit G to obtain the pass/fail judgment output GO/NG. It's something you get.
That is, when the voltage value is between the upper limit value _VH and the lower limit value _VL , a determination output GO is obtained indicating that the product is non-defective.

The write circuit WR is tested by selecting the test memory cell group _TSTR1 .

That is, one of the write circuits WR is selected by the diode logic circuit receiving the output signal of the address decoder circuit AD _B , and bit line selection is performed.

For example, for a decoder output signal in which diodes Q ₁₃ to Q ₁₄ are turned off, transistors Q ₁₂ ,
_Q11 turns on and bit line _B1 is selected.

On the other hand, by the word line selection circuit WD that receives the decoder output signal of the address decoder circuit AD _W ,
Test word line W _T is selected.

Now, if bit line B ₁ is selected and a current of approximately 20 mA is applied to unwritten memory cell Q _T1 from constant current circuit I ₀ , the breakdown voltage between the collector and emitter of memory cell Q _T1 and the thyristor configuration A voltage of about 10V is obtained at the output terminal OUT1, which is the sum of the base-to-emitter voltage of the transistor _Q11 , the collector-to-emitter voltage of the transistor _Q12 , and the collector-to _- emitter voltage of the word line selection transistor _QT . Therefore, the upper limit voltage V _H and lower limit voltage V _L , which are the expected values at this time, are set to, for example, about 11V and 9V, respectively.

Now, if there is a disconnection or an abnormality in the above circuit route and the current drive capacity is insufficient, 12~
A high voltage of 20V appears at the output terminal OUT ₁ .
In addition, if there is a leak between other circuits, if the programmed transistor Q _T is also selected by double selection, or if the withstand voltage of the memory cell Q _T1 has deteriorated, a low voltage of 8V or less will be output. terminal
Appears on OUT ₁ .

On the other hand, for example, select the bit line B ₂ and connect it to the written memory cell Q _T2 by about 20 m from the constant current circuit I ₀ .
When a current of A flows, the voltage is the sum of the base-to-emitter voltage and the collector-to-emitter voltage of transistors Q ₂₁ , Q ₂₂ , and Q _T in the same selection circuit as above, and the base-to-emitter voltage of memory cell Q _T2 . Approximately 6V is available at the output terminal OUT ₁ . Therefore,
The upper limit value V _H ′ and lower limit value V _L ′ are the expected values at this time.
For example, they are set to 7V and 5V, respectively.

Now, if there is a disconnection or abnormality in the circuit route above, and the current drive capacity is insufficient, then 7.5
A high voltage of ~20V appears at the output terminal OUT ₁ . Also, if the ground falls in the middle of the circuit route,
A voltage below 5V appears at the output terminal OUT ₁ .

The relationship between the output terminal voltage and the current value from the constant current circuit _I0 for the unwritten memory cell Q _T1 and the written memory cell Q _T2 is shown in FIG. Therefore, the expected values V _H , V _L and
V _H ′ and V _L ′ are set to have a predetermined width, as shown by the dotted line in the figure.

Similar tests are performed on other memory cells Q _T3 -Q _To .

On the other hand, all of the memory cells MC used by the user (selective writing) are unwritten memory cells, so the above expected values V _H , V _L
A similar test is performed by setting the voltage to 11V or 9V, for example.

In this case, it is desirable to carry out the test after completing the test of the write circuit WR. That is, by inspecting the memory cell MC after the write circuit WR has been determined to be a non-defective product, if a defect is found, it can be clearly determined that the memory cell is defective.

In this example, the test is performed by flowing a small current that does not cause junction breakdown into unwritten memory cells, so in addition to the test memory cells, the memory cells used by the user are also tested. Reliable non-destructive inspection can be performed.

Furthermore, since a certain degree of current drive ability can also be determined, for example, the test memory cell groups TSTW ₁ and TSTW ₂ to which writing is actually performed may be omitted.

In the block diagram of FIG. 1, SE is a sense circuit, and _Q1 to _Q4 are output buffer circuits.

The present invention is not limited to the above-mentioned embodiments, and any circuit for determining pass/fail may be used. Further, the determination level can be changed in various ways.

Furthermore, the block configuration and specific circuit of the junction-destructive PROM to be tested can be modified in various ways.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a junction breakdown type PROM, FIG. 2 is a characteristic diagram showing the relationship between test current and judgment voltage for explaining the present invention, and FIG.
The figure is a main circuit diagram showing an embodiment of the present invention.

Claims (1)

[Claims] 1. A plurality of word lines, a plurality of bit lines, an unwritten memory cell having a transistor structure to be used on the user side provided between each word line and the pit line, and a word line. A method for testing a junction-destroying PROM comprising a line selection circuit and a write circuit, the method comprising:
Determining a current source circuit that outputs a current with a value less than the junction breakdown current of a memory cell under a voltage that causes breakdown between the collector and emitter of an unwritten memory cell, and the output level of such a current source circuit. and determining means to select an unwritten memory cell by the write circuit and the word line selection circuit, and to supply the output of the current source circuit to the selected memory cell via the write circuit. , a joint destruction type characterized in that pass/fail is determined based on the output of the above-mentioned determining means at that time.
PROM inspection method. 2. Claim No. 2 characterized in that the junction destruction type PROM includes a test memory cell, and after the above-mentioned test of the test memory cell is completed, the test of the unwritten memory cell is started. A method for inspecting a junction-destructive PROM as described in Section 1.