JPS6349417B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention In an information processing device, for example, when transmitting and receiving data between a host computer and an input/output device, parallel information is transmitted word by word in serial form. It is used to convert it into a form and then send and receive it. On the receiving side, the received serial information is converted into parallel information and processed. The present invention relates to a method for diagnosing a circuit that converts digital information into serial data for transmission and reception.

(b) Background of the Technology As shown in FIG. 1, a host computer 1 is connected to a plurality of input/output devices 3a, 3b, 3c, . . . via a workstation channel 2. As shown in the workstation channel 2 and the input/output device 3a, each is equipped with a driver DV and a receiver RV for transmission, and information transmission from the driver DV to the receiver RV on the other side is via coaxial This is done with cable 4. At this time, parallel data is converted into serial data and transmitted. Therefore, on the receiving side, the received data must be converted into parallel data.

FIG. 2 is a block diagram showing a conventional example of a circuit that converts parallel data into serial data and serial data into parallel data for transmission and reception. The data to be transmitted is sent in parallel from the write data bus 5 in serial/parallel, parallel/
The signal is input to a serial conversion register 6, shifted to a sampling circuit 7, and output. Then, the sampling circuit 7 converts the pulse width and other data according to the transfer method of the serial interface section, and then outputs the data to the serial interface section via the driver DV. Also serial
The serial reception data inputted from the interface section is inputted to the sampling circuit 7 via the receiver RV, and after data conversion, it is serially inputted to the conversion register 6, converted to parallel data, and then sent to the read data bus 8. is output to.

(c) Prior art and its problems When transmitting and receiving data by converting serial/parallel or parallel/serial, it is necessary to diagnose whether each circuit operates correctly when the power is turned on before transmitting or receiving data. is started.

Conventionally, to perform such a diagnosis, diagnostic data A ₁ , A _{2 ,} etc. with various bit patterns were used.
. . . is written in the memory 9, and the respective data A ₁ , A ₂ .
Set in register 6 for parallel/serial conversion. Then, after converting to serial, with the transmitting circuit turned off, the output data is looped back to the conversion register 6 -> sampling circuit 7 -> driver DV -> receiver RV -> sampling circuit 7 -> conversion register 6, and then to the conversion register again. Enter 6. The data thus output serially is converted into parallel data by the conversion register 6 and inputted to the Y register 12 via the read data bus 8. The arithmetic circuit 11 then compares and collates the data with the data previously input from the X register 10 to check whether the bit patterns match. Such a diagnosis is performed for each diagnostic data A ₁ , A _{2 .} . . .

However, in such a system, the conversion register 6
For example, if the data set in the conversion register 6 is one word "10111000P" (P is a check bit), and the shift is not performed due to a malfunction of the conversion register 6, and the data remains in the conversion register 6, , the content of the data will be "10111000P" also when output to the read data bus 8. If all the circuits operate correctly, it goes without saying that the returned data will be converted into parallel data by the conversion register 6 and the content of the data output to the read data bus 8 will be "10111000P". . In the end, the content of the output data when the transmitter/receiver circuit operates correctly is the same as the read content of the data that remains set without being shifted from the conversion register 6, making it impossible to diagnose the conversion register 6 itself. There will be no.

(d) Object of the Invention The object of the present invention is to eliminate such problems in the conventional diagnostic method for transmitting/receiving circuits, and to make it possible to reliably diagnose malfunctions of conversion registers.

(e) Structure of the Invention In order to achieve this object, the present invention converts digital information input in parallel into serial data using registers for serial/parallel and parallel/serial conversion, and transmits and receives the data in serial form. When diagnosing a circuit, set the digital bit length for serial/parallel and parallel/serial conversion to data length + α bits, and connect the parallel input of the serial/parallel and parallel/serial conversion registers to the serial/parallel and parallel/serial conversion registers.
A method is adopted in which the diagnostic data output from the parallel and parallel/serial conversion registers is repeatedly re-inputted by changing the bit position of the serial input.

(f) Embodiments of the Invention Next, examples will be used to explain how the diagnosis method for a transmitting/receiving circuit according to the present invention is actually implemented.
FIG. 3 is a block diagram showing an embodiment of the system of the present invention, and the same parts as those in FIG. 2 are given the same reference numerals. In the case of the present invention as well, diagnostic data A ₁ , A ₂ . The point of comparison with the data entered in is the same. In the present invention, the bit positions of the initially set data and the folded data are different. For this purpose, the bit length of the conversion register 6 is set to the data length of the diagnostic data + α bits, which is longer than the data length of the diagnostic data by α (2 bits in the illustrated example). The data set from the write data bus 5 is performed in a predetermined bit area (in the illustrated example, 9 bits including the parity check bit P) from the beginning. When setting serial data by looping back from receiver RV, do not set data for the first 2 bits, and set data for the remaining 9 bits.
Set to bit area. In other words, the bit position is shifted by 2 bits when parallel input from the write data bus 5 and when folded data is input serially.

In this way, if the first parallel input data is, for example, one word "10111000P", the shift will not be performed due to a malfunction of the conversion register 6, and the data will remain in the conversion register 6. If it reads data bus 8
The content of the data when outputting to is, as mentioned above, the first two bits are not used.
It becomes “111000PXX”. XX is undefined and the previous state remains. Therefore, the arithmetic circuit 11 in FIG.
Then, when comparing the parallel input data "10111000P" and the data "111000PXX" remaining due to the malfunction of conversion register 6, only the difference between the bit length of the conversion register and the data length is α bits (2 bits in the example shown). , there is a mismatch, and the conversion register 6
It can be detected that the system is malfunctioning.

If all the circuits operate correctly, the returned data will also be "10111000P" and will be set in the third and subsequent bit positions. However, since reading is also performed from the 3rd bit onwards, the data content output to the read data bus 8 is also "10111000P", and the data content is output to the write data bus 5 first.
This will match the data entered from.

(g) Effects of the Invention As described above, according to the present invention, the bit length of the register for serial/parallel and parallel/serial conversion is set to the data length of diagnostic data + α bits, and serial/parallel, parallel/serial conversion is performed. The system shifts the bit positions of the parallel input of the serial conversion register and the folded serial input. Therefore, even if the parallel input data remains as it is due to a malfunction of the conversion register itself, when it is read out to the read data bus, it will be read out with a difference of α bit, resulting in a mismatch when the data is compared. Malfunctions of conversion registers can be checked, and all circuits can be reliably diagnosed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data transmission/reception system, FIG. 2 is a block diagram showing a conventional transmission/reception circuit diagnostic system, and FIG. 3 is a block diagram showing an embodiment of a transmission/reception circuit diagnostic system according to the present invention. . In the figure, 5 is a write data bus, 6 is a register for serial/parallel and parallel/serial conversion, 7 is a sampling circuit, DV is a driver, RV is a receiver, 8 is a read data bus, 1
1 indicates an arithmetic circuit for comparison and verification, respectively.

Claims (1)

[Claims] 1. When diagnosing a circuit that converts digital information input in parallel to serial using a register for serial/parallel or parallel/serial conversion and transmits/receives in serial form, The bit length of the register for parallel and parallel/serial conversion is set as data length + α bit, and the parallel input of the serial/parallel and parallel/serial conversion register and the serial/
A diagnostic method for a transmitting/receiving circuit characterized by changing the bit position of a serial input in which diagnostic data output from a parallel and parallel/serial conversion register is looped back and re-inputted.