JPS6349449B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital protection relay, and more particularly to a digital protection relay that reduces the number of circuits to be sampled.

Attempts to apply digital processing devices such as microcomputers to protective relays used in power systems are being studied both domestically and internationally, and the time for practical application is approaching.

As is well known, a protective relay using a digital processing unit, that is, a digital protective relay, converts analog relay input from the power system into digital quantities, and performs a relay judgment by performing digital calculations using these digital quantities. It is something. Here, a conventional circuit configuration diagram of a digital protective relay (for example, a distance relay) that performs relay determination using a plurality of electric quantities will be explained with reference to FIG. In Fig. 1, I ₁ to I _N are the input electrical quantities consisting of the voltage and current of each phase, and are respectively input to the sample and hold circuit 1.
Input from 1 to 1N. The sample and hold circuits 11 to 1N sample each of the relay inputs I ₁ to _IN in response to a sample and hold signal S _S from the control circuit 2, and hold these sampled values. Moreover, this sampling is N
This is performed simultaneously in the sample and hold circuits 11 to 1N. Each of the outputs S ₁ to S _N from the sample and hold circuits 11 to 1N is introduced into a selection circuit 3, and based on the selection signal S _M from the control circuit 2, the inputs S ₁ to _{S N} are selected one by one as outputs S ₁₀ . Output in chronological order. The conversion circuit 4 inputs the conversion signal _SA from the control circuit 2, converts the input _S10 into a digital quantity based on this conversion signal SA, and outputs _S11 . The calculation unit 5 inputs the selection signal S _M and the end signal S ₁₂ output from the conversion circuit 4 at the end of analog/digital conversion in the conversion circuit 4, and outputs the respective outputs S for the relay inputs I ₁ to _{I N.} Load ₁₁ . Then, using this input _S11 and the setting value _S13 from the setting circuit 6, a relay determination for each input is performed by digital arithmetic processing. As a result of digital calculation processing in the calculation unit 5, when it is determined that an accident has occurred, a circuit breaker trip command is output.

Here, the sample-and-hold signal S _S is generally sampled 12 times during one cycle, and the sample-and-hold circuits 11 to 1N are controlled to hold the sampled value during each sampling. . As the calculation unit 5, a microcomputer or the like is used.

In the conventional circuit configuration described above, all inputs of each relay are simultaneously sampled, and therefore, a number of sample and hold circuits equal to the number of electrical quantities input to the relays are required. As a result, a large number of relay elements are housed in a digital protective relay, which not only makes the device larger and more expensive, but also has drawbacks such as reduced reliability due to the increased number of parts used. Ta.

The present invention has been made in order to solve the above-mentioned drawbacks, and provides digital protection that allows the number of sampling circuits to be reduced even if the number of relay inputs increases, and also allows for miniaturization, lower cost, and higher reliability. The purpose is to provide electrical relays.

Examples will be described below with reference to the drawings. Second
FIG. 3 is a time chart explaining the response; FIG. 4 is a circuit diagram of another embodiment of the digital protection relay according to the present invention; FIGS. 5 and 6; FIG. 7 shows still other embodiments.

In FIG. 2, the same symbols as in FIG. 1 are the same components. In the figure, 31 and 32 are the first
There are two selection circuits. 33 is the second
21 is a control circuit, I ₁₁ to I _1M and I ₂₁ to
I _2M are each relay inputs. The first selection circuits 31 and 32 have relay inputs _I11 to _I1M and _I21 , respectively.
~I _2M and the first selection signal S _M1 output from the control circuit 21 are input, and based on the selection signal S _M1 , the relay inputs I ₁₁ ~ I _1M and I ₂₁ ~ _{I 2M} are respectively set one by one. Outputs as outputs S ₃₁ and S ₃₂ in chronological order. The sampling and holding circuits 11 and 12 respectively input the outputs S ₃₁ and S ₃₂ and the sampling and holding signal S _S output from the control circuit 21, and sample S ₃₁ and S ₃₂ based on the sampling and holding signal S _S. and retains the sampled value for a certain period of time. These sampled values are output from the sampling and hold circuits 11 and 12 as outputs S ₂₁ and S ₂₂ , respectively. The second selection circuit 33
S ₂₁ , S ₂₂ and a second selection signal S _M2 are input, and S ₂₁ and _{S 22 are} output one by one as S ₃₀ in time series based on the second selection signal S M2. This S ₃₀ is input to the conversion circuit 4, which converts the output S ₃₀ into a digital amount based on the conversion signal S _A output from the control circuit 21, and outputs an output S ₁₁ which is a digital amount. Then, when the conversion to _S11 is completed, an end signal _S12 is output. The arithmetic unit 5 outputs the output
S ₁₁ , the end signal S ₁₂ , the first selection signal S _M1 , and the second selection signal S _M2 are respectively input, and the relay inputs I ₁₁ to
I _1M and the output S ₁₁ corresponding to the relay inputs I ₂₁ to I _2M are read. The calculation unit 5 performs a relay determination by digital calculation processing based on the setting value _S13 outputted from the setting circuit 6 and the output _S11 , and outputs a circuit breaker trip command when it is determined that an accident has occurred. The response in the circuit configuration shown in FIG. 2 will be explained below with reference to FIG.

In FIG. 3, the first selection signal S _M1 is at time t ₀
The value is "1" at time T ₁ of ~ t ₁ , and during this time, the relay inputs from the first selection circuits 31 and 32, respectively.
Performs control to output I ₁₁ and I ₂₁ . Therefore, between time t ₀ and t ₁ , S ₃₁ becomes I ₁₁ and S ₃₂ becomes I ₂₁ .
After time _t1 , the first selection signal S _M1 sequentially changes to "2", "3", ... "M" at _T1 time intervals, and accordingly, _S31 and _S32 also sequentially change to _I12 , I ₁₃ ...I _1M and I ₂₂ ,
I ₂₃ ...I _2M . Sample and hold signal S _S is the first
The selection signal S _M1 becomes "1" at time t ₀ and is then output at time t ₀₁ , samples I ₁₁ and I ₂₁ in sample and hold circuits 11 and 12, respectively, and holds the sampled values. They are output as S ₂₁ and S ₂₂ , respectively. Therefore
S ₂₁ and S ₂₂ are respectively relay inputs I ₁₁ at time t ₀₁
and the sampling value of I ₂₁ . After time t ₀₁ , the sample and hold signal S _S is output at every time interval T ₁ that is the same as the change in the first selection signal S _M1 , and sampling is performed in the same manner thereafter. The second selection signal S _M2 has a value of "1" at time t ₀₁ , and the second selection circuit 33 performs control to output the output S ₃₀ as S ₂₁ , and at time t after time T ₁ /2. "2" in ₀₂
, and the output S ₃₀ from the second selection circuit 33 is
is output as S ₂₁ , and the time T ₁ /2
At a later time _t02 , the value becomes "2", and control is performed to output the output _S30 from the second selection circuit 33 as _S22 . This value of "2" is maintained for T ₁ /2 time, and becomes "1" again at time t ₁₁ .

Therefore, the output S ₃₀ of the second selection circuit 33 is the sampling value of relay input I ₁₁ between times t ₀₁ and _{t 02} , and the sampling value of relay input “2” between times t ₀₂ and _{t 11} . value. The conversion signal S _A is output at time t ₀₃ after the output S ₃₀ becomes the sampling value of the relay input I ₁₁ at time t ₀₁ , and the conversion circuit 4 converts the sampling value of the relay input I ₁₁ into a digital quantity. is started.

Then, at time t ₀₄ when this conversion ends,
At the same time that the end signal _S12 is output, the output _S11 of the conversion circuit 4 becomes a value obtained by converting the relay input _I11 into a digital quantity. Similarly, at time t ₀₅ , which is T ₁ /2 hours after time t ₀₃ , the conversion signal S _A is output, and the sampling value of relay input I ₂₁ is converted into digital data.
At time _t06 , the end signal _S12 is output, and the output _S11 becomes a value obtained by digitally converting the relay input _I21 . Even after time _t11 , the second selection signal S _M2 and conversion signal S _A are output in the same way as above, and the same control as above is performed and the relay input is
I ₁₂ to I _1M and I ₂₂ to I _2M are sequentially converted into digital quantities. This digital amount is calculated by the calculation unit 5 as follows.
is input.

When the end signal S ₁₂ is output at time t ₀₄ ,
The calculation unit 5 learns from the end signal _S12 that one quantity of the relay input has been converted from analog to digital, and performs a process of reading the output _S11 between times _t04 and _t02 . At this time, the calculation unit 5 first determines which of the relay inputs I ₁₁ to I _1M or I ₂₁ to I _2M this output S ₁₁ is.
This is determined based on the selection signal S _M1 and the second selection signal S _M2 . For example, regarding S ₁₁ between times t ₀₄ and _{t 02} , since S _M1 = “1” and S _M2 = “1”, it is the relay input I ₁₁ , and regarding S ₁₁ between times t ₀₆ and _{t 11} , Since S _M1 = "1" and S _M2 = "2", it is determined that it is the relay input I ₂₁ . As described above, the relay inputs I ₁₁ to I _1M and I ₂₁ to I _2M are sequentially and alternately converted into digital quantities and input to the calculation unit 5. This conversion is performed at a fixed sampling period T, which generally corresponds to 12 samplings per cycle or 2 samplings per cycle.

Here, a specific example of the digital protective relay will be explained below.

In Fig. 2, relay inputs I ₁₁ to I _1M are connected to 3
Phase voltage input, and similarly relay input I ₂₁ ~
By setting I _2M to 3-phase current input, 3
Phase distance relays can be configured. That is, according to the configuration shown in FIG. 2, since the voltage input and current input of each phase are simultaneously sampled, it is possible to configure a three-phase distance relay that performs relay determination based on the relationship between voltage and current. Furthermore, by setting the relay inputs I ₁₁ to _{I 1M} to each phase current of one terminal of power equipment, such as a transformer or generator, and setting the relay inputs I ₂₁ to I _2M to each phase current of the other terminal, both terminals It is possible to simultaneously sample each phase current of , and it is also possible to configure a current differential relay. Furthermore, by using the configuration shown in FIG. 2, it is possible to configure various relays that perform relay determination based on the relationship between two quantities of electricity.

It is also clear that single quantity relays, such as overcurrent relays, undervoltage relays, etc., can be constructed in the same manner as conventionally.

Therefore, in the embodiment shown in FIG. 2, a multi-input type relay can be constructed by providing two sample-and-hold circuits, and a sample-and-hold circuit is provided for each input as in the conventional method. There's no need. However, the number of selection circuits has increased compared to the conventional configuration, but as is well known, the selection circuit can be made smaller with fewer parts, so it is easier to use than the sample and hold circuit. It's just a small enough increase.

Therefore, according to the present invention, even if the number of relay inputs increases, the number of sampling circuits can be far reduced compared to the conventional method, resulting in miniaturization of the device and
It is possible to realize a digital protective relay that achieves the desired objectives such as lower cost and higher reliability.

FIG. 4 is a circuit diagram of another embodiment of the present invention. In the figures, the same symbols as the constituent elements in FIGS. 1 and 2 indicate the same constituent elements.

The configuration shown in FIG. 4 is particularly different from the circuit configuration shown in FIG. P sample-and-hold circuits 11, 12, .
This is the point where P outputs of 1P are input to the second selection circuit 3P+4. and the first selection circuit 34,
35...3P+3 are relay inputs I ₁₁ to I _1M , I ₂₁ respectively
~I _2M ,...I _P1 ~I _PM and the first selection signal S _M1 are input, and under the control of the first selection signal S _M1 ,
Outputs S ₃₁ , S ₃₂ , ...S _3P are derived, respectively. The sample and hold circuits 11, 12...1P respectively output the outputs _S31 , _S32 ,... _S3P and the sample and hold signal _Ss.
are input, the input is sampled by the sample hold signal S _S , the sampled value is held, and the sampled value is outputted respectively S ₂₁ ,
Output as S ₂₂ ,...S _2P . The second selection circuit 3P+4 receives the outputs S ₂₁ , S ₂₂ ,...S _2P and the third selection signal _SM3 , and outputs the third selection signal _SM3.
Under the control, the P inputs are output one by one in time series as the output _S30 . and other configurations are second
Same as the figure.

The response in the circuit configuration shown in FIG. 4 described above differs from the response shown in FIG. 2 explained in FIG. 3 only in the following points.

That is, in the circuit configuration shown in FIG. 4, the second selection circuit 3P+4 sequentially outputs the P inputs S ₂₁ , S ₂₂ . . . S _2P one by one, so that the third selection signal S _M3
changes from a value of "1" to a value of "P" for each value of the first selection signal S _M1 , and the conversion signal S _A
will also be output P times.

According to the configuration shown in FIG. 4 explained above, M×P
The P relay inputs can be divided into P groups of M relay inputs, and the P relay inputs can be simultaneously sampled to convert the M×P relay inputs into digital quantities.

Therefore, according to this embodiment, the following various types of relays can be constructed. That is, when performing short-circuit distance protection for n lines connected to a common bus, the bus voltage is input as the voltage, and the current is input for each line. At this time, it is necessary to simultaneously sample the voltage and current for each phase.
Now, considering the case of 10 lines, it is possible to set M=3 and P=10 in FIG. 4.
That is, it is sufficient to provide 10 sampling and holding circuits and 10 first selection circuits. On the other hand, the conventional method requires 30 sample-and-hold circuits, the same number as the number of inputs. In addition, in a normal digital protective relay, one relay provides short circuit protection and ground fault protection, but at this time, the zero-sequence voltage and zero-sequence current only need to be sampled at the same time, so the above numerical value is M = 4. , P=10, and the number of sample and hold circuits may remain at 10. Further, with respect to the first selection circuit, there is no need to increase the number of inputs since a normally available circuit can process up to eight inputs in one circuit. The conventional method requires 40 sample and hold circuits. The protection of the bus bar is normally carried out by a current differential protection method or a phase comparison protection method by inputting the phase currents of all lines connected to the bus bar. At this time, it is necessary to simultaneously sample and input the phase currents of all lines. According to this embodiment, it is sufficient to provide as many first selection circuits and sample and hold circuits as there are lines, and to perform phase switching using the first selection circuits. On the other hand, in the conventional system, sample-and-hold circuits for the number of phases x the number of lines are required, and the number of rotations is usually about 10 to 20, so the number of circuits reduced by this embodiment is extremely large.

Although examples of relays applicable to the embodiment shown in FIG. 4 have been described above, the present invention is not limited to this example, and can be applied to various types of relays that require simultaneous sampling of a large number of relay inputs. It goes without saying that this embodiment can also be applied to various types of relays that require simultaneous sampling. Furthermore, the second
In the embodiment according to the invention described with reference to FIG. 4 and FIG. 4, each relay input is input to only one of the first selection circuits, but the configuration is not limited to this.

Next, another embodiment of the present invention will be described with reference to the circuit configuration shown in FIG. This embodiment is a modification of FIG. 2. That is, the first selection circuit 31 inputs the relay inputs I ₁₁ to I _1M , and also receives the relay inputs I 11 to I 1M.
2 is configured to input relay inputs I ₂₁ to _{I 2 (M-1)} and I _{1 (M-1)} , and the other configuration is completely the same as the circuit configuration shown in FIG. 2.

As can be understood from the description of the response in Figure 3, the relay inputs of the first selection circuits 31 and 32 are
Simultaneous sampling is performed according to the input order. Therefore, according to the configuration of this embodiment, relay inputs I ₁₁ and I ₂₁ , I ₁₂ and I ₂₂ , I _{1 (M-1)} and
I _{2 (M-1)} , I _1M and I _{1 (M-1)} will be sampled simultaneously. That is, relay input I _{1 (M-1)} is
It will be sampled simultaneously with I _2(M-1) and simultaneously with I _1M .

A specific example of a relay having this configuration will be described below. That is, as is well known, the digital protective relay is not only capable of making various relay determinations in the same determination section, but also capable of processing protection sequences and reclosing sequences. Therefore, for example, a relay element for distance protection and a relay element for reclosing may be stored, and relay inputs for these relay elements may be input. At this time, the synchronization for reclosing is performed by relay determination based on the line voltage and one phase of the bus voltage that is the voltage input to the distance relay. Therefore, one phase of the bus voltage needs to be sampled at the same time as the current input and also the line voltage.

Here, as another specific example, if M=4, I ₁₁ =V _R ,
I ₁₂ = V _S , I ₁₃ = V _T , I ₁₄ = V _LINE (line voltage), I ₂₁ =
If I _R , I ₂₂ = I _S , I ₂₃ = I _T , V _R and I _R , I _S , V _T
Since I _T , V _LINE and V _T are simultaneously sampled, each input for a distance relay and a synchronous relay can be obtained.

As explained above, according to the circuit configuration shown in FIG. 5, one relay input can be input to a plurality of first selection circuits, and one relay input can be sampled at different timings. Various relay configurations are possible.

FIG. 6 shows another embodiment of the invention. In FIG. 6, the first selection circuit 31 has relay inputs _I11 to
I _{1 (M-1)} is input, and the relay input I _{1 (M-1)} is the (M-1)th input of the first selection circuit 31 and also becomes the M-th input. The first selection circuit 32 receives relay inputs I ₂₁ to I _2M , and the other configuration is exactly the same as the circuit configuration shown in the second figure.

According to the circuit configuration shown in Figure 6, I ₁₁ and I ₂₁ , I ₁₂ and
I ₂₂ ... I _{1 (M-1)} and I _{2 (M-2)} , and I _{1 (M-1)} and I _2M are respectively sampled simultaneously. Now, assuming M=4, I ₁₁ = V _R , I ₁₂ = V _S , I ₁₃ = V _T , I ₂₁ = I _R , I ₂₂ =
If I _S , I ₂₃ = I _T , and II ₂₄ = V _LIINE (line voltage), it can be seen that simultaneous sampling is performed exactly as in the case shown in FIG. 5 above.

As explained above with respect to the circuit configuration shown in FIGS. 5 and 6, one relay input is inputted to a plurality of first selection circuits, or a relay input is inputted so that it is selected multiple times in the first selection circuit. By inputting , it is possible to sample one relay input multiple times at different times, and a relay corresponding to these configurations can be obtained. Please note that the input method shown in Figure 6 is
It goes without saying that the present invention can be applied to the circuit configuration shown in the figures.

Next, still another embodiment of the present invention will be described with reference to the circuit configuration shown in FIG. This embodiment is a modification of FIG. 4. In the figure, the same symbols as the constituent neighboring elements in FIG. 4 indicate the same constituent elements.

In Figure 7, sample hold circuit 1P+
1 is relay input IP+1 and sample hold signal S _S
is input, the relay input IP+1 is sampled by the sample hold signal S _S , the sampling value is held, and the sampling value is S _{2 (P+1).}
Output as . The second selection circuit 3P+5 includes sample and hold circuits 11, 12, 1P and 1P+1.
outputs S ₂₁ , S ₂₂ ,...S _2P and S _2(P+1) and a fourth selection signal S _M4 are input, and under the control of the fourth selection signal S _M4 , (P+1) inputs are input. are output one by one in chronological order as output _S30 . The other configurations are the same as the circuit configuration shown in FIG.

The response in the circuit configuration shown in FIG.
The response in the circuit configuration shown in the figure differs only in the following points.

That is, since the sample-and-hold circuit 1P+1 directly inputs the relay input IP+1, the sample-and-hold circuits I ₁ to I _P sample M relay inputs and simultaneously input the other relay input IP
+1 is sampled M times. Second selection circuit 3
P+5 is (P+1) inputs S ₂₁ , S ₂₂ ,...S _P ,
Since S _P+1 is output one by one, the fourth selection signal S _M4
changes from a value of "1" to a value of "P+1" for each other value of the first selection signal, and the converted signal
S _A is also output (P+1) times.

According to the circuit configuration shown in FIG. 7 described above (M
×P+1) relay inputs are divided into P groups of M each and one relay input corresponding to the (P+1)th group, and one of each P group and (P+
1) By simultaneously sampling one relay input corresponding to the th group, it is possible to convert (M×P+1) relay inputs into digital quantities.

Here, a specific example of the relay according to this embodiment will be described below. In other words, when providing ground fault protection for direct-to-ground power transmission lines, a distance relay is normally used, but in order to accurately measure distance in the event of a single line ground fault,
Generally, zero-sequence compensation is performed. In order to perform this zero-sequence compensation, calculations are performed using the instantaneous values of the phase current and zero-sequence current, but for this purpose, the zero-sequence current and each phase current must be sampled simultaneously.

Therefore, here, assuming P=2 and M=3, I ₁₁
= V _R , I ₁₂ = V _S , I ₁₃ = V _T , I ₂₁ = I _R , I ₂₂ = I _S , I ₂₃ =
If I _T , I ₃ = I ₀ , V _R and I _R and I ₀ , V _S and I _S and I ₀ , V _T
and I ₀ are sampled at the same time, so it is possible to obtain a distance relay input with zero-sequence compensation. According to the configuration shown in FIG. 7 according to this embodiment, it is also possible to configure a relay in which among the plurality of relay inputs there is a relay input that requires simultaneous sampling with all other relay inputs. In the configuration of this embodiment, an example has been described in which one sample-hold circuit is provided to directly input the relay input, but a plurality of sample-hold circuits may be provided. For example, in the specific example of the relay shown in Figure 7 above, when performing zero-sequence compensation using the zero-sequence current of the own line and the adjacent line, two sample-hold circuits that directly input the relay input must be provided. Bye.

In these configuration examples described above, the case is shown in which the number of inputs of the plurality of first selection circuits are all the same, but they do not necessarily have to be the same. When the number of inputs of the first selection circuits is different, it is only necessary to enable selection of the input by the first selection signal for the first selection circuit having the maximum number of inputs. Further, in this embodiment, the configuration is such that the arithmetic unit reads the conversion circuit output, which is a digital quantity, but the configuration is not limited to this, and the conventionally well-known DMA (Direct
The data may be written to the data memory in the calculation unit using the Memory Access function.

As explained above, according to the present invention, each of the plurality of relay inputs is divided into groups and introduced into the plurality of first selection circuits, and the relay inputs are introduced into the plurality of first selection circuits. Simultaneous sampling is performed by the built-in sample and hold circuit,
Since the circuit configuration is such that these sampled values are converted into digital values via the second selection circuit and the conversion circuit, the number of sample and hold circuits can be extremely small compared to the number of relay inputs, and the device can be made smaller. It is possible to provide a digital protective relay that can be made more compact, lower in price, and more reliable.

[Brief explanation of the drawing]

Fig. 1 is a conventional circuit configuration diagram of a digital protective relay, Fig. 2 is a circuit configuration diagram of an embodiment of a digital protection relay according to the present invention, Fig. 3 is a time chart for explaining response, and Fig. 4 is a circuit diagram of an embodiment of a digital protective relay according to the present invention. The circuit configuration diagrams of the embodiments, FIGS. 5, 6, and 7 each represent still other embodiments. 11, 12,...1P...Sample hold circuit, 31,32,34...3P+3...First selection circuit, 33,3P+4...Second selection circuit, 4...
...Conversion circuit, 5...Arithmetic unit.

Claims (1)

[Scope of Claims] 1. A digital protective relay that performs arithmetic processing by converting a plurality of relay inputs into digital signals and outputting them in time series, wherein the relay converts each of the N relay inputs into each group. At least one or more first selection circuits that are introduced separately, and N pieces that are provided corresponding to the first selection circuits and that sample and hold the output from the first selection circuits. A small number of M sample and hold circuits, a second selection circuit in which the output of the sample and hold circuit is introduced and output one input at a time in time series, and the output of the second selection circuit are introduced to convert it into a digital code. It is characterized by comprising a conversion circuit that performs conversion and output, and an arithmetic unit that introduces the digital code and performs relay determination, and samples N relay inputs in time series in the M sample-hold circuits. Digital protection relay. 2. A patent claim characterized in that one relay input out of a plurality of relay inputs is commonly input to a plurality of first selection circuits, and the one relay input is sampled at different timings. A digital protective relay according to item 1. 3. Divide the plurality of relay inputs into P groups of M groups and one relay input corresponding to the (P+1)th relay input, and connect one of the P relay inputs to the (P+1)th group.
Claim 1 characterized in that one relay input corresponding to the relay input is simultaneously sampled.
Digital protective relays as described in section.