JPS634966B2 - - Google Patents
Info
- Publication number
- JPS634966B2 JPS634966B2 JP57151753A JP15175382A JPS634966B2 JP S634966 B2 JPS634966 B2 JP S634966B2 JP 57151753 A JP57151753 A JP 57151753A JP 15175382 A JP15175382 A JP 15175382A JP S634966 B2 JPS634966 B2 JP S634966B2
- Authority
- JP
- Japan
- Prior art keywords
- variable resistor
- voltage
- converter
- vref
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0619—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by dividing out the errors, i.e. using a ratiometric arrangement
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0845—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of power supply variations, e.g. ripple
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Combined Controls Of Internal Combustion Engines (AREA)
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】
本発明は可変抵抗器出力Ａ／Ｄ変換装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable resistor output A/D conversion device.
従来、内燃機関の電子制御燃料噴射装置におい
ては、例えばスロツトル開度センサ等、可変抵抗
器を用いたセンサが使用され、そのセンサ出力を
Ａ／Ｄ変換器でデジタル化してコントロールユニ
ツトに供給している。 Conventionally, in electronically controlled fuel injection systems for internal combustion engines, a sensor using a variable resistor, such as a throttle opening sensor, is used, and the sensor output is digitized by an A/D converter and supplied to a control unit. There is.
ところで、従来可変抵抗器出力をＡ／Ｄ変換す
る際は、例えば第１図に示すような構成を採用し
ていた。 By the way, conventionally, when A/D converting the variable resistor output, a configuration as shown in FIG. 1, for example, has been adopted.
すなわち、電源電圧Vcc（例えば5V）の供給ラ
イン１に抵抗Roを介して可変抵抗器２の可変抵
抗Rs（Ra＋Rb）を接続し、その出力（Vin）を
Ａ／Ｄ変換器３に入力させる。また、前記供給ラ
イン１に抵抗Rcを介して抵抗Rdを接続し、抵抗
RcとRdとによつて得られる基準電圧Vref（2.5V
位）をＡ／Ｄ変換器３に入力させる。尚、抵抗
RoはＡ／Ｄ変換器３への入力電圧Vinの最大値
を基準電圧Vref以下とするために用いている。 That is, a variable resistor Rs (Ra+Rb) of a variable resistor 2 is connected to a supply line 1 of a power supply voltage Vcc (for example, 5 V) via a resistor Ro, and its output (Vin) is input to an A/D converter 3. In addition, a resistor Rd is connected to the supply line 1 via a resistor Rc, and a resistor
Reference voltage Vref (2.5V
) is input to the A/D converter 3. Furthermore, resistance
Ro is used to keep the maximum value of the input voltage Vin to the A/D converter 3 below the reference voltage Vref.
この場合、例えば８ビツトの分解能（1/256の
精度）をもつＡ／Ｄ変換器３では、そのデジタル
出力Doutは、アナログ入力Vinに対して、次の如
くとなる。尚、Vref／256は最小分解能である。 In this case, for example, in the A/D converter 3 having an 8-bit resolution (accuracy of 1/256), its digital output Dout is as follows with respect to the analog input Vin. Note that Vref/256 is the minimum resolution.
Dout＝Vin／（Vref／256） ……(1)
また、Rb／（Ro＋Rs）＝α、Rd／（Rc＋Rd）
＝βとおくと、
Vin＝α・Vcc ……(2)
Vref＝β・Vcc……(3)となる。 Dout=Vin/(Vref/256)...(1) Also, Rb/(Ro+Rs)=α, Rd/(Rc+Rd)
=β, then Vin=α・Vcc……(2) Vref=β・Vcc……(3).
したがつて、(2)，(3)式を(1)式に代入すれば
Dout＝（256・α）／β……(4)となる。 Therefore, by substituting equations (2) and (3) into equation (1), we get
Dout=(256・α)/β...(4).
すなわち、電源電圧Vccに依存しない式とな
り、Vccに依存しないデジタル出力が得られる。 In other words, the formula is independent of the power supply voltage Vcc, and a digital output that is independent of Vcc can be obtained.
しかしながら、このような従来の可変抵抗器出
力のＡ／Ｄ変換装置の回路構成では、可変抵抗器
をスロツトル開度センサ等のセンサとして考えた
場合、回転角度に対する分圧比Ra／Pbは正確で
あるものの、Rsの絶対値は相当なバラツキをも
つているため、α値（Rb／（Ro＋Rs））はRoの
影響を受け、検出回転角に誤差を生じるという問
題点があつた。 However, in the circuit configuration of such a conventional A/D converter output from a variable resistor, when the variable resistor is considered as a sensor such as a throttle opening sensor, the voltage division ratio Ra/Pb with respect to the rotation angle is accurate. However, since the absolute value of Rs varies considerably, the α value (Rb/(Ro+Rs)) is affected by Ro, resulting in an error in the detected rotation angle.
尚、従来の方式で高精度を得るようとすると、
Ro及びRsの精度を高くとる必要があり、コスト
面で不利となる。また、Roを内蔵し、Rsと共に
Roをトリミングして比率を合わせる方法もある
が、これも歩留り、コスト面で極めて不利であ
る。 Furthermore, if you try to obtain high accuracy using the conventional method,
It is necessary to have high accuracy in Ro and Rs, which is disadvantageous in terms of cost. It also has a built-in Ro, along with Rs.
There is also a method of adjusting the ratio by trimming Ro, but this is also extremely disadvantageous in terms of yield and cost.
本発明はこのような従来の問題点に着目し、こ
れを解決することを目的としてなされたもので、
可変抵抗器の電圧源として基準電圧Vrefを供給
するようにし、またインピーダンスをあわせるた
め電圧利得の無い電流増幅器を用いて基準電圧
Vrefを供給する構成とすることにより、上記問
題点を解決したものである。 The present invention has been made with the aim of focusing on and solving these conventional problems.
The reference voltage Vref is supplied as a voltage source for the variable resistor, and a current amplifier with no voltage gain is used to match the impedance.
The above problem is solved by having a configuration that supplies Vref.
以下、本発明を図面に基づいて説明する。 Hereinafter, the present invention will be explained based on the drawings.
第２図は本発明の一実施例を示している。 FIG. 2 shows an embodiment of the invention.
抵抗RcとRdとの分圧点（基準電圧Vref）をオ
ペアンプによる電流増幅器４の＋側入力端子に接
続し、出力端子を−側入力端子に接続し、負帰還
させる。そして、出力端子を可変抵抗器２に接続
して、その電圧源として用いる。 The voltage dividing point (reference voltage Vref) between the resistors Rc and Rd is connected to the + side input terminal of a current amplifier 4 using an operational amplifier, and the output terminal is connected to the - side input terminal for negative feedback. Then, the output terminal is connected to the variable resistor 2 and used as its voltage source.
すなわち、基準電圧Vrefを電圧利得のない電
流増幅器４によつて電流増幅し、インピーダンス
を下げて、可変抵抗器２の電圧源として用いる。
これにより、可変抵抗器２の電圧源が低インピー
ダンスとなり、Vin≦Vrefの条件を保ちつつ、
Rsの絶対値の影響を受けなくする。 That is, the reference voltage Vref is current-amplified by a current amplifier 4 having no voltage gain, the impedance is lowered, and the reference voltage Vref is used as a voltage source for the variable resistor 2.
As a result, the voltage source of the variable resistor 2 becomes low impedance, and while maintaining the condition of Vin≦Vref,
Make it unaffected by the absolute value of Rs.
ここで、Rb／（Ra＋Rb）＝Ａとおくと、 Vin＝Ａ・Vref ……(5) となり、これを前記(1)式に代入すれば、 Dout＝256・Ａ ……(6) となる。 Here, if we set Rb/(Ra+Rb)=A, Vin＝A・Vref……(5) So, by substituting this into equation (1) above, we get Dout=256・A...(6) becomes.
すなわち、Vccは勿論、Rsにも依存しない式
となり、VccやRsの影響を受けないデジタル出
力が得られる。 That is, the formula does not depend on Vcc or Rs, and a digital output that is not affected by Vcc or Rs can be obtained.
第３図には他の実施例を示す。 FIG. 3 shows another embodiment.
この実施例は、抵抗RcとRdとによつて得られ
る基準電圧Vrefを電流増幅器４を介し可変抵抗
器２の電圧源として供給することは前述の実施例
と同じであるが、電流増幅された基準電圧Vref
をＡ／Ｄ変換器３に供給するようにしている。 This embodiment is the same as the previous embodiment in that the reference voltage Vref obtained by the resistors Rc and Rd is supplied as the voltage source for the variable resistor 2 via the current amplifier 4, but the current amplified Reference voltage Vref
is supplied to the A/D converter 3.
動作は同じであるが、この方式の方がオペアン
プのオフセツト入力電圧の影響を受けない利点が
ある。 Although the operation is the same, this method has the advantage of not being affected by the offset input voltage of the operational amplifier.
以上説明したように本発明によれば、Ａ／Ｄ変
換器への基準電圧Vrefを電圧利得のない電流増
幅器に入力し、その出力電圧を可変抵抗器の電圧
源として、可変抵抗器による分圧点をＡ／Ｄ変換
器でＡ／Ｄ変換するようにしたため、電源電圧
Vccは勿論、可変抵抗器の全抵抗値Rsの影響を
全く受けないデジタル出力が得られ、高精度で分
圧比をＡ／Ｄ変換できるという効果が得られる。
特に可変抵抗器の場合、回転角に対する分圧比の
精度は高くとれるが、Rsの精度はとりにくいと
いう問題があるから、好適で、コスト面でも有利
である。 As explained above, according to the present invention, the reference voltage Vref to the A/D converter is input to a current amplifier with no voltage gain, and the output voltage is used as the voltage source of the variable resistor, and the voltage is divided by the variable resistor. Since the point is A/D converted by an A/D converter, the power supply voltage
It is possible to obtain a digital output that is completely unaffected by the total resistance value Rs of the variable resistor as well as Vcc, and it is possible to achieve the effect that the voltage division ratio can be A/D converted with high accuracy.
In particular, in the case of a variable resistor, the accuracy of the voltage division ratio with respect to the rotation angle can be high, but there is a problem that it is difficult to maintain the accuracy of Rs, so this is suitable and advantageous in terms of cost.
第１図は従来例を示す回路図、第２図は本発明
の一実施例を示す回路図、第３図は他の実施例を
示す回路図である。
１……電源電圧Vccの供給ライン、２……可変
抵抗器、３……Ａ／Ｄ変換器、４……電流増幅
器、Vref……基準電圧、Vin……アナログ入力、
Dout……デジタル出力。
FIG. 1 is a circuit diagram showing a conventional example, FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIG. 3 is a circuit diagram showing another embodiment. 1... Supply line of power supply voltage Vcc, 2... Variable resistor, 3... A/D converter, 4... Current amplifier, Vref... Reference voltage, Vin... Analog input,
Dout...Digital output.
Claims (1)
器によりＡ／Ｄ変換する装置において、前記Ａ／
Ｄ変換器への前記基準電圧が入力される電圧利得
の無い電流増幅器を設け、この電流増幅器の出力
電圧を前記可変抵抗器の電圧源として、前記可変
抵抗器による分圧点を前記Ａ／Ｄ変換器でＡ／Ｄ
変換することを特徴とする可変抵抗器出力のＡ／
Ｄ変換装置。1 In a device that A/D converts the output of a variable resistor using an A/D converter based on a reference voltage, the A/D converter
A current amplifier without voltage gain is provided to which the reference voltage to the D converter is input, and the output voltage of this current amplifier is used as the voltage source of the variable resistor, and the voltage dividing point by the variable resistor is connected to the A/D converter. A/D with converter
A variable resistor output characterized by converting A/
D conversion device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15175382A JPS5941927A (en) | 1982-09-02 | 1982-09-02 | A/D converter with variable resistor output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15175382A JPS5941927A (en) | 1982-09-02 | 1982-09-02 | A/D converter with variable resistor output |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5941927A JPS5941927A (en) | 1984-03-08 |
| JPS634966B2 true JPS634966B2 (en) | 1988-02-01 |
Family
ID=15525535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15175382A Granted JPS5941927A (en) | 1982-09-02 | 1982-09-02 | A/D converter with variable resistor output |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5941927A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6399430U (en) * | 1986-12-18 | 1988-06-28 | ||
| US5172115A (en) * | 1991-02-15 | 1992-12-15 | Crystal Semiconductor Corporation | Ratiometric A/D converter with non-rationometric error offset |
| KR100315696B1 (en) * | 1999-09-13 | 2001-12-12 | 조영석 | Analog and Digital circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5830768B2 (en) * | 1974-10-31 | 1983-07-01 | キヤノン株式会社 | Kijiyunden Atsuhendou Hosei Cairo |
-
1982
- 1982-09-02 JP JP15175382A patent/JPS5941927A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5941927A (en) | 1984-03-08 |
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