JPS6349806B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an address conversion method for converting a virtual address having a segment number, page number, and displacement information into a real address.

[Technical background of the invention and its problems]

Generally, virtual storage systems have been configured as shown in FIG. In such a system, processors 11, 11..., input/output channels (hereinafter referred to as CH) 12, 12..., etc. send data onto the system bus 14 in order to access the memory device (hereinafter referred to as MEM) 13. The address received was a real address. Therefore, the processors 11, 11, . . . perform address conversion processing for converting virtual addresses into real addresses in order to realize virtual memory.
..., CH12, 12... were carried out respectively. For this reason, in the system shown in FIG. 1, each processor and each CH must have an address translation function, which has the disadvantage of increasing costs.

Therefore, in order to eliminate the drawbacks of the system shown in FIG. 1, a virtual storage system including a virtual storage control device (hereinafter referred to as VSP) 21 as shown in FIG. 2 has been considered. In this system,
VSP21 has an address translation function, and VSP2
In 1, processors 11, 11... and CH1
2, 12, etc., a virtual address is converted into a real address. Therefore, in the system shown in Fig. 2, the processors 11, 11...
There is no need to provide an address conversion function to CH12, 12, . . . , and costs can be reduced. Note that 22, 22... are processors 11, 1
1...The cache memory provided on the side, 23 is
This is a paging device managed by VSP21.

In the system shown in FIG. 2, the addresses handled by processors 11, 11, . . . and CH 12, 12, . Unlike the system shown in FIG. 1, the address to be sent is a virtual address. Therefore, the processor 11 uses the cache memory 22.
It is also necessary to use a virtual address when accessing (cache access). but,
Conventionally, virtual addresses were not assigned to all information (all real address positions) on the MEM 13 in a one-to-one correspondence, so such information was stored in the cache memory 22 using virtual addresses.
It has been extremely difficult to enter or read data from the cache memory 22. For example, the page table is located only on the MEM13, that is, the real storage device, so no virtual address is assigned to the page table (that is, the page table is not visible from the virtual storage device), and the page table It was not possible to cache entries by virtual address. For this reason, the system shown in FIG. 2 has poor feasibility.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to provide an address conversion method that can realize a virtual memory system in which a memory control device has a function of converting virtual addresses to real addresses. .

Another object of the present invention is to provide an address translation method that can support a large-scale virtual storage space.

Still another object of the present invention is the properties of segments that are compatible with their intended use.More specifically, segments are used for arranging programs that require extremely high-speed processing even though they are small in scale, or segments that do not require high-speed processing. An object of the present invention is to provide an address translation method that can perform address translation according to the type of segment, such as whether it is a segment used for arranging a large-scale program or the like.

[Summary of the invention]

The present invention provides a memory control device with a function to convert virtual addresses into real addresses, thereby realizing a system that does not require an address conversion function in a processor or input/output channel. Virtual addresses are assigned to all information in real memory, such as tables. Therefore, in the present invention, the segment table is placed in the V=R segment, the page table for the normal segment is placed in another independent segment (page table segment), and the page table of this page table segment is placed in the V=R segment. These two types of page tables are used to perform address conversion using a two-level paging method that converts a virtual address into a real address. By doing this,
Virtual addresses can be assigned to (each entry in) the two types of page tables mentioned above in a one-to-one correspondence, and the size of the page table placed in the V=R segment, which has a limited capacity, can be small.

Furthermore, in addition to the above-mentioned two-level paging method, the present invention provides a method in which the segment number of a virtual address is set to V=R segment so that efficient address conversion can be performed depending on the characteristics (segment type) corresponding to the purpose of the segment. , the V=R method address conversion that outputs the displacement in the virtual address as it is as a real address, the relocation method address conversion that maps the entire segment onto real memory in a continuous state, and furthermore, 1 The memory control device has performance for level paging address conversion, and can be selected depending on the characteristics (segment type) corresponding to the purpose of the segment. Also, the page table used in the above one-level paging method is V=R
This page table is placed in a segment so that virtual addresses can be assigned in a one-to-one correspondence to (each entry in) this page table.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows the configuration of the virtual storage system. In the figure, 30, 30... are processors having cache memories 31, 31...
0... is CH (input/output channel). The processors 30, 30..., CH40, 40... handle only the virtual address of the virtual address VA and the real address RA, and therefore have an address conversion function to convert the virtual address VA to the real address RA. I don't have it. 50 is MEM
(memory device), and the MEM 50 includes a segment table (hereinafter referred to as ST) 51, a first page table (hereinafter referred to as PT A) 52, and a second page table (hereinafter referred to as PT _A ) 52.
Page table (hereinafter referred to as PT _B ) 53, and third page table (hereinafter referred to as PT _C )
54 is placed. ST51, PTA52, PTB5
3. The PTC 54 is also placed in a virtual storage device (virtual address space) 90 that is divided and managed in segments as shown in FIG. As a result, the above files stored in this virtual storage device 90 are
Tables such as ST51 can be viewed even from processor 30 and CH40, which handle only virtual addresses. This means that even from processors 30 and CH40 that handle only virtual addresses, VSP70, which will be described later, has an address translation function.
By passing the above
Indicates that it is possible to view tables such as ST51.

A virtual address VA indicating an arbitrary address position in the virtual storage device 90 is a segment number SN (16 bits) and a page number as shown in FIG.
It consists of PN (13 bits) and displacement BN (11 bits). Segment number as we know
A virtual address VA with an SN of 0 matches the real address RA.

Referring to Figure 11 again, ST51, PTB5
3. The PTC 54 stores the segment whose segment number SN is 0 in the virtual storage device 90, so-called V=R.
located in the segment. Therefore, MEM
ST51, PTB53 on 50 (real storage device),
A virtual address VA is assigned to each entry in the PTC 54 in a one-to-one correspondence. In addition to the above V=R segment, the segments configuring the virtual storage device 90 include segment number SN.
There are normal segments with an even number (excluding "0") and page table segments with an odd number. The normal segments are classified into type 1 normal segments to which the relocation method described below is applied, type 2 normal segments to which the 1-level paging method is applied, and type 3 normal segments to which the 2-level paging method is applied. There is. The page table segment itself is used as the _PTA 52 for the above-mentioned type 3 normal segment. That is, PTA ₅₂ is an independent segment on the virtual address space. In this embodiment, the segment number SN of the target segment (type 3 normal segment) is 2i (i is a positive integer) as shown in FIG. 11, and the segment number SN of the page table segment is 2i+1. PTA 52 is a page table for segment 2i (type 3 normal segment), and is placed in page table segment 2i+1. The page table for this page table segment 2i+1 is the PTB 53 placed in the V=R segment. Also, the first
Each segment number of species, type 2 normal segment
SN are 2j (j is a positive integer, j≠i) and 2k, respectively.
(k is a positive integer, k≠i, j). The page table for type 2 normal segment 2k is V=
This is the PTC 54 placed in the R segment. In this way, in this embodiment, the page table (PT _A 5
2, PT _B 53, PT _C 54) also have segment numbers
SN is given.

In FIG. 3, 60 is a paging device, 70
is a VSP (virtual storage controller) connected to MEM50, 80 is a processor 30, 30..., CH4
This is a system bus for connecting buses 0, 40, etc., and VSP70. The VSP 70 converts the virtual address sent onto the system bus 80 from the processors 30, 30, . . . , CH 40, 40, . Has a function. As is clear from the above description, in this embodiment, the processor 30,
30..., CH40, 40... virtual address
It does not have an address conversion function to convert VA to real address RA, and this address conversion function is
I am concentrating on VSP70.

When a memory read access is required in the processor 30, the cache memory 31 is accessed using the virtual address VA. In the case of a cache miss in which the target information does not exist in the cache memory 31, or in the case of memory write access, the processor 30 sends the virtual address VA onto the system bus 80. VSP
70 converts the virtual address VA on the system bus 80 into a corresponding real address RA, and accesses the MEM 50 using this real address RA. If it is a memory read, the VSP 70 reads the target information from the MEM 50 and sends it to the processor 30, and if it is a memory write, the VSP 70 reads the target information from the MEM 50.
Write information to. This is CH
Even when CH 40 requires memory access, it is similar to the case of processor 30 except that CH 40 is not provided with a cache memory and no cache access is performed. When a memory write access is performed from either the processor 30 or CH 40, if information in which the write information and the virtual address VA are the same exists in the cache memory 31, the corresponding information in the cache memory 31 is also updated. Ru.

In the VSP 70 shown in FIG. 3, 71 is a virtual address register (hereinafter referred to as VAR) in which a 40-bit virtual address VA transferred via the system bus 80 is stored. Also, 72 is
ST located on MEM50 (real storage device)
This is a segment table starting point address register (hereinafter referred to as STOR) in which starting point address information No. 51 is set. 73 is a first address conversion unit (hereinafter referred to as AT _A ) activated when converting the address for the virtual address VA of the V=R segment;
74 is the virtual address VA of the first type normal segment
This is a second address translation unit (hereinafter referred to as AT _B ) that is activated when converting an address for. 75,
Reference numerals 76 denote a third address translation unit (hereinafter referred to as AT _C ) and a fourth address translation unit (hereinafter referred to as _AT ). 77 is a 32-bit real address register (hereinafter referred to as RAR) in which a real address RA for output to the MEM 50 is set; 78 is a control unit (hereinafter referred to as CNT) forming the center of the VSP 70; CNT78 has a built-in microprogram memory (not shown), and under microprogram control AT _A73 ,
Controls AT _B 74, AT _C 75, AT _D 76, etc.
The CNT 78 determines whether the segment number SN in the virtual address VA stored in the VAR 71 is SN = 0 (all "0"), and if SN = 0, that is, V = R segment, AT _A 73 to perform V=R method address conversion. As is clear, in the V=R segment, the virtual address
VA matches real address RA. In this example, the virtual address corresponding to the V=R segment
VA is the segment number SN (16 bits) for SN = 0.
and a 24-bit intra-segment relative address (PN
(corresponding to the concatenation information with BN), and the relative address within this segment is the real address.
The purpose is to show RA. However, since the real address RA handled in this embodiment has a 32-bit configuration, the AT _A 73 uses the lower 32 bits of the virtual address VA set in the VAR 71 as the real address RA.
Output to RAR77 as

As mentioned above, the virtual address VA in the V=R segment that is the target of address conversion in the V=R method
matches the real address RA and does not require any actual address translation processing, so address translation can be performed extremely quickly. Therefore, the V=R method is suitable for accessing tables such as ST51 that need to be referenced without performing substantial address conversion, and for accessing programs that require ultra-high-speed processing. However, V = R segment (MEM corresponding to
Since the size of the area (area within 50) is limited, the amount of programs that can be applied is significantly limited.

On the other hand, if SN≠0, that is, V=a segment other than the R segment, CNT78 is based on the segment number SN and the contents of STOR72.
Refer to the corresponding entry in ST51 on MEM50. The segment descriptor, which is the content of each entry in ST51, is 2 as shown in Figure 5.
It consists of bit-structured conversion type designation information (hereinafter referred to as conversion type number) T, page table starting point address PTO of 22-bit structure, and so on. The translation type number T is either T=0, 1, or 2, where T=0 indicates relocation method address translation, T=1 indicates 1-level paging method address translation, and T=2 indicates 2-level paging method address translation. It is designed to specify address translation for each address. Note that when T=0, the corresponding entry in ST51 contains the page table starting address PTO.
Instead, origin information ORIGIN (the most significant bit is "0") indicating the starting position of the corresponding segment on the MEM 50 (real storage device) by a real page number is written. As a result of referring to ST51, the CNT 78 activates the AT _B 74 to perform relocation type address translation if the translation type number T in the corresponding entry is T=0. Similarly, T=1 for CNT78
If so, start AT _C 75 and perform address translation using the 1-level paging method, and if T=2,
AT _D 76 is activated to perform two-level paging type address translation. That is, AT _B 74,
CNT78 has a relocation type address conversion function, AT _C75 and CNT78 have a one-level paging type address conversion function, and AT _D
76, CNT78 has a two-level paging type address translation function.

FIG. 6 is a functional configuration diagram schematically showing the address conversion function of AT _B74 and CNT78.
0 is an adder. Segment number SN in virtual address VA placed in VAR71 and
The contents of the corresponding entry (segment descriptor) in ST51 are read based on the contents of STOR72, and the conversion type number T in the segment descriptor is read out.
is T=0, then in the same segment descriptor
ORIGIN (lower 21 bits) and the above virtual address
The page number PN in VA is directed to an adder 100. Therefore, the adder 100 adds ORIGIN and
PN is added, and the page frame number PFN is obtained. And the displacement in this page frame number PFN and the above virtual address VA
Connection information with BN is RAR7 as real address RA
The number is placed at 7. This is relocation-based address translation.

As described above, in relocation-based address conversion, there is no need to refer to a page table, so high-speed address conversion is possible, and therefore it is suitable for accessing programs that require high-speed processing. However, since it is not a paging method, a large continuous area is required on the MEM 50 in order to allocate an area to the MEM 50, so the applicable programs are limited to those with a small size.

Figure 7 is a functional configuration diagram schematically showing the address translation function of AT _C75 and CNT78.
0 is an adder, and 201 is a 24-bit register. Virtual address placed in VAR71
When VA corresponds to the second type normal segment, the conversion type number T in the segment descriptor read from ST51 is T=1. In this case, the PTO in the segment descriptor and the PN in the virtual address VA are directed to the adder 200. PTO and PN are added by adder 200, and the result of this addition (22 bits) is placed in the upper 22 bits of register 201 of 24 bits. "00" is placed in the lower two bits of this register 201, which means that the above addition result has been multiplied by four. This is because the size of each entry in _PTC 54 is 4 bytes in this embodiment (the same applies to _PTA 52 and PT _B 53). In this case, PTO is the starting address of _PTC 54 located in the V=R segment, and therefore the value obtained by adding PTO and PN and multiplying the addition result by 4, that is, the contents of register 201 is _PTO 5
The real address of the target entry in 4 is RA ₀ (=
virtual address VA ₀ ). register 2
The target page frame number PFN is written in the entry of PT _C 54 specified by 01,
Concatenation information between this PFN and the BN in the virtual address VA is placed in the RAR 77 as the real address RA. This is address translation using the one-level paging method.

FIG. 8 is a functional configuration diagram schematically showing the address conversion function of AT _D 76 and CNT 78.
0 and 301 are 24-bit and 32-bit registers, respectively. If the virtual address VA set in VAR71 is the third type normal segment,
The conversion type number T in the segment descriptor read from ST51 is T=2. In this case, only the upper 18 bits of PTO (22 bits) in the segment descriptor are meaningful (the lower 4 bits are all "0", for example), and the starting address on the V=R segment of _PTB 53 is 64 Specify in bytes. The upper 18 bits of this PTO are placed in the upper 18 bit area of the 24-bit register 300.
The following 4-bit area of this register 300 contains the upper 4 bits of PN (13 bits) in the virtual address VA.
A bit (this is called HPN) is set.
“00” is set in the lower two bits of register 300, and the contents of this register 300, that is,
The concatenated information of PTO, HPN, and “00” becomes the real address RA ₀ (=virtual address VA ₀ ) of the target entry in PT _B 53. The page frame number PFN1 (21 bits) of the page where the page table (PT _A 52) for the target segment (type 3 normal segment 2i) is placed is written in the entry of PT _B 53 specified by the register 300. This PFN1 and the lower 9 bits of the PN (13 bits) in the virtual address VA (this is called LPN)
Concatenation information (30 bits) is placed in the upper 30 bits of the 32-bit register 301. “00” is set in the lower two bits of this register 301, and the contents of this register 301 are
The concatenated information of PFN1, LPN, and "00" becomes the real address _RA1 of the target entry in _PTA 52. The target page frame number PFN2 is written in the entry of PT _A 52 specified by the register 301, and this PFN2 and the BN in the virtual address VA
The connection information with the real address RA is placed in the RAR 77. This is the two-level paging method address translation.

In this embodiment, the number of pages constituting one segment is ²¹³ pages because the page frame number PN has a 13-bit configuration. Therefore, the number of entries in the page table for one segment is 2 ¹³ , and in this embodiment where 4 bytes (for 4 addresses) are allocated to 1 entry, the size of the page table for 1 segment is 2 ¹⁵ (bytes).
becomes. For this reason, in the one-level paging method of this embodiment in which such a page table is placed within the V=R segment (so that the page table is also assigned a virtual address), the V=R segment is compressed. Real storage device (MEM)
50) and the segment size (in this case, under the same virtual address space, the number of segments will be smaller) to support a large number of segments, that is, a large virtual address space. This becomes difficult. However, the one-level paging method allows relatively high-speed address conversion because the page table is referenced only once, and is suitable for medium-sized programs that require high-speed processing. In addition, although the relocation method does not have the above-mentioned problems, it has less flexibility in dynamic relocation, so
50) has the disadvantage that it is difficult to operate it efficiently.

In contrast, the two-level paging method can support a large-scale virtual address space as shown below. In this embodiment, the page table (PT _A 5) of segment 2i (type 3 normal)
2) is placed in (page table) segment 2i+1, the page table (PT _B 53) placed in this segment 2i+1 is placed in the V=R segment, and a two-level paging method is enabled by assigning virtual addresses to these page tables. .
Placed in segment 2i+1 above, size 2 ¹⁵
Since the size of one page is 2 ¹¹ (bytes), the number of pages occupied by the (byte) page table (PT _A 52) is 2 ¹⁵ /2 ¹¹ = 2 ⁴ pages. this is,
Page table (PT _B 53) for page table (PT _A 52) placed in segment 2i+1
This shows that the number of entries required is ²⁴ . Therefore, in this embodiment where 4 bytes are allocated to one entry, the above page table (PT _B 5
The size of 3) is 2 ⁶ (bytes). This page table (PT _B 53) is placed in the V=R segment, but its size is 2 ⁶ (bytes) as described above, that is, the page table (PT _C 54) applied in the one-level paging method. 2 ⁶ / 2 ¹⁵ =
Since 1/2 ¹¹ , the two-level paging method can be applied to a very large number of segments without compressing the V=R segment. However, in the two-level paging method, it is necessary to refer to two types of page tables (PTA52, PTB53), so high-speed address translation is difficult compared to one-level paging. Suitable for large-scale programs, etc.

By the way, in the two-level paging method, the page table (PT _B 5
3) 24-bit real address RA ₀ to reference
As is clear, the HPN (4 bits) in the virtual address VA ₀ is 2 ⁴ of the page table (PT _B 53).
This indicates one of the entries. Therefore, the page frame number PFN1 (21 bits), which is the content of the entry, is per page table.
2 There are ⁴ types, each with a different lower 4 bits. On the other hand, the size of the page table (PT _A 52) of segment 2i placed in segment 2i+1 is
²¹⁵ , that is, the number of entries is ²¹³ , and the lower 4 bits of PFN1 in the 32-bit real address _RA1 and
One of these ²¹³ entries is indicated by the link information (13 bits) with the LPN (9 bits).
In this example, (3rd type normal) segment 2i
As shown in Figure 8, any virtual address VA in the SN (16 bits), HPN (4 bits),
If it consists of LPN (9 bits) and BN (11 bits), (page table) segment 2i
Virtual address VA ₁ indicating the start position of the entry corresponding to the above virtual address VA in the page table (PT _A 52) of segment 2i located at +1
The displacement BN (11 bits) is the register 3 in Figure 8.
As is clear from the contents of 01 (real address RA ₁ indicating the start position of the corresponding entry above), the above
This is concatenation information between LPN (9 bits) and “00”.
Meanwhile, the page number PN of the above virtual address VA ₁
is the contents of register 300 (segment
The actual address indicating the start position of the corresponding entry in the page table of segment 2i located at 2i+1, that is, PT _A 52.
RA ₀ ) as evident from the above virtual address VA
This is the middle HPN. PN is 13 bits and HPN is 4 bits, so the page number PN of virtual address VA ₁ is the concatenated information of 9 bits of all “0” information (upper bits) and 4 bits of HPN (lower bits). be. Figure 9 shows this virtual address VA
This shows the relationship between the virtual address VA1 and the virtual address _VA1 . As can be easily understood from the above explanation, according to this embodiment, all page tables (PT _A 52,
A virtual address VA can be assigned to each entry in PT _B 53, PT _C 54) in a one-to-one correspondence. Therefore, each processor 30, 30...
Cache access using virtual address VA can be performed at . This allows processor 3
A virtual memory system in which CHs 40, 40, . . . 0, 30, .

Next, a case will be described in which the virtual address VA ₁ in the (page table) segment 2i+1 is converted to the real address RA ₁ . In this case, CNT7
AT _D 76 is activated by 8 (3rd type normal)
Convert virtual address VA in segment 2i to real address
Some operations similar to those performed when converting to RA are performed. FIG. 10 is a functional configuration diagram schematically showing the address translation function for the virtual address VA ₁ by the AT _D 76 and CNT 78, and 400 is a subtracter. In this embodiment, the segment table entry of ST51 exists only for even-numbered segments, so when converting the virtual address VA ₁ in odd-numbered segment (page table segment) 2i+1, the subtracter 4
00, the segment number SN in the virtual address VA ₁ is decremented by 1 to use the segment table entry (in ST51) for the segment number 2i. The upper 18 bits of PTO in the segment descriptor read from ST51 are stored in the 24-bit register 300 as in the case of FIG.
It is placed in the upper 18 bit area of The subsequent 4-bit area of this register 300 contains the lower 4 bits of PN in virtual address VA ₁ (see FIG. 9).
(corresponding to HPN) is set. “00” is set in the lower two bits of register 300, and the contents of this register 300 are the real address RA ₀ (=virtual address VA ₀ ) of the target entry in PT _B 53.
becomes. PT _B 5 specified in register 300
In entry 3, the target page frame number PFN1 is written, and the connection information between this PFN1 and the BN in the virtual address VA ₁ (corresponding to the connection information between LPN and "00" in Figure 9). is the real address RA ₁
It is placed in RAR77 as . This address translation is required when updating the _PTA 52, for example.

In the explanation so far, it is assumed that all the target pages exist in the real storage device (MEM50), but if they do not exist in the real storage device, a page fault exception occurs and the following operation is performed. . That is, the VSP 70 performs page-out or page-in between the MEM 50 and the paging device 60. During this time, the processor 30 that requested the memory reference retains the currently executing task and executes another task.

In addition, in the above embodiment, AT _A 7 is included in the VSP 70.
3, AT _B 74, AT _C 75, and AT _D 76 have been described, but FIGS. 6 to 8
As can be understood from the diagram and the functional configuration diagram of FIG.
1,300, etc., and CNT78 controls the hard mechanism according to the properties of the segment, and ST51, PT _A52 ,
By referring to PT _B 53, PT _C 54, etc., the above four types of address translation may be performed. Furthermore, in the embodiment described above, a case has been described in which segments with even segment numbers are used as normal segments and segments with odd segment numbers are used as page table segments, but the way they are divided is not limited to the above embodiment. . Furthermore, in the above embodiment, it was explained that whether or not the address conversion is based on the V=R method is determined based on the segment number in the virtual address VA, but as with other address conversion methods, the segment number in the segment descriptor is The conversion type number T may specify the V=R method. In this case, even if the virtual address is in the V=R segment, ST51
(segment table) will be referenced.

〔Effect of the invention〕

As detailed above, according to the address conversion method of the present invention, it is possible to realize a virtual memory system in which the memory control device has the function of converting virtual addresses to real addresses, and moreover, it is possible to realize a virtual memory system that has a large-scale virtual memory space. can be supported.

Further, according to the present invention, optimal address translation can be performed according to the characteristics (segment type) corresponding to the purpose of the segment.

[Brief explanation of drawings]

Fig. 1 and Fig. 2 are system configuration diagrams showing a conventional example, Fig. 3 is a block diagram showing an embodiment of the present invention, Fig. 4 is a diagram showing a virtual address format, and Fig. 5 is a segment descriptor. Figures 6 to 8 are functional configuration diagrams schematically showing the address conversion functions of the relocation method, 1-level paging method, and 2-level paging method, respectively. A diagram showing the relationship between a virtual address and a virtual address in a page table segment corresponding to the virtual address, and FIG. 10 is a functional configuration diagram schematically showing an address conversion function that converts the virtual address in the page table segment to a real address. , FIG. 11 explains the various segments that make up the virtual storage device, as well as the virtual storage device and the memory device (real storage device).
FIG. 3 is a diagram for explaining the positional relationship of various tables placed in the . 11, 11..., 30, 30... processor, 1
3,50...Memory device (MEM), 14,80
...System bus, 21,70...Virtual storage controller (VSP), 22,22...,31,31...Cache memory, 51...Segment table (ST), 52...First page table (PT) _A ), 5
3...Second page table ( _PTB ), 53...Third page table ( _PTC ), 73...First address translation unit ( _ATA ), 74...Second address translation unit ( _ATB ), 75...Third address translation unit (AT _C ),
76...Fourth address translation unit ( _ATD ), 78...
Control unit (CNT).

Claims (1)

[Scope of Claims] 1. In a virtual memory system in which a memory control device has a function of converting a virtual address having a segment number, page number, and displacement information into a real address, a V in which a virtual address matches a real address is provided. = a virtual storage device consisting of three types of segments: an R segment, a normal segment, and a page table segment that itself is used as the first page table for the normal segment, and a page table for the page table segment, which is the V a second page table placed in the =R segment; a third page table for the normal segment to which the 1-level paging method is applied and placed in the V=R segment; and a third page table placed in the V=R segment.
A segment table placed within the segment,
A V=R type first address conversion means that outputs a predetermined field of the virtual address as it is as a real address, and a relocation type address conversion means in which the entire segment is mapped onto the real storage device in a continuous state, a second address conversion means for obtaining a real address based on the segment table reference result based on the segment number in the virtual address and the page number and displacement information in the virtual address; One-level paging that refers to the third page table based on the table reference result and the page number in the virtual address, and obtains a real address based on the third page table reference result and displacement information in the virtual address. a third address translation means of the method;
The second page table is referenced based on the segment table reference result based on the segment number in the virtual address and the upper bits of the page number in the virtual address, and the second page table reference result and the virtual A fourth address in a two-level paging system in which the first table is referenced based on the lower bits of the page number in the address, and the real address is obtained from the reference result of the first page table and the displacement information in the virtual address. An address translation method comprising: a translation means; and a control means for selecting one of the first to fourth address translation means according to the characteristics of a segment. 2. The address translation method according to claim 1, wherein a translation type designation field for specifying an address translation method is provided in each entry of the segment table. 3. Conversion type designation information specifying any one of the relocation method, one-level paging method, or two-level paging method is set in the conversion type designation field. Address translation method described. 4 The control means determines whether the corresponding segment is V= by the segment number in the virtual address.
It is determined whether or not it is an R segment, and if V=R segment, the first address conversion means is selected, and if V=R segment, the segment table is referred to based on the segment number, and the corresponding The address according to claim 3, wherein one of the second, third, or fourth conversion means is selected depending on the content of the conversion specification field in the corresponding entry of the segment table. Conversion method.