JPS6349915B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as IC).
In particular, the present invention relates to an integrated circuit device incorporating a closed-gate junction field effect transistor (hereinafter referred to as J-FET).

Recently, composite ICs have been announced that combine various elements with different functions to provide new functions.
One of these is composite ICs that incorporate J-FETs into various amplifiers with high input impedance and low cross-modulation, or high-speed integration circuits that take advantage of high slew rates.

Compared to bipolar transistors, J-FETs
It has features such as high input impedance, high switching speed, and low current noise, but among these J-FET features, the first J-FET has a structure that takes advantage of the high frequency characteristics.
In contrast to the open gate type in which the gate and the second gate are electrically connected, the first gate and the second gate are electrically separated, and the first gate with a large pn junction area is electrically connected to the source region. A so-called closed gate type J-FET is being considered, which operates by connecting the two gates and using the second gate, which has a small junction area, as the gate of the J-FET.

The structure and operating principle of a conventional closed gate J-FET will be described below with reference to the drawings.
FIG. 1a is a plan pattern diagram of a conventional closed gate type n-channel J-FET, and FIG. 1b is a sectional view taken along line B--B in FIG. 1a. In the figure, 1 is a p-type semiconductor substrate, 2 is an n-type semiconductor layer formed thereon, 3 is a p-type isolation region for separating a part of the n-type semiconductor layer 2 from other parts, and 4 is a p-type semiconductor layer.
a p-type second gate region formed by diffusing p-type impurities into a part of the n-type semiconductor layer 2 surrounded by the type isolation region 3 in an annular shape from the surface thereof so as not to reach the p-type semiconductor substrate 1; Reference numeral 5 denotes an n-type drain region consisting of a portion of the n-type semiconductor layer 2 surrounded by the p-type second gate region 4, and 6 consists of a portion sandwiched between the p-type isolation region 3 and the p-type second gate region 4. n-type source region,
7 is a channel region consisting of a portion sandwiched between the p-type second gate region 4 and the p-type semiconductor substrate 1; 8 is a surface insulating film; 9 is between the p-type second gate region 4 and the n-type channel region 7; p-n junctions, 14, 15 and 1
Reference numerals 6 denote a second gate electrode, a drain electrode, and a source electrode, which are formed so as to penetrate the surface insulating film 8 and connect to the p-type second gate region 4, the n-type drain region 5, and the n-type source region, respectively. The p-type semiconductor substrate 1 has a function as a first gate region, and the p-type semiconductor substrate 1 passes through the p-type isolation region 3 and extends over the surface of the p-type isolation region 3 via a source electrode 16. and is electrically connected to the source region 6.

In this FET, a depletion layer is extended to the channel region 7 by applying a reverse bias voltage between the n-type source region 6 and the p-type second gate region 4, and the n-type source region 6 and the n-type drain region 5 are This is a voltage-driven element that is operated so that the conductance through the channel region 7 between them changes. and,
If the figure of merit indicating the maximum frequency at which the J-FET operates is M, then M = g _n /C _G where, g _n : Mutual conductance C _G : Gate capacitance = Gate-source capacitance C _GS + Gate-drain capacitance Represented by C _GD . As you can see from the above formula, J-FET
In order to improve the high frequency characteristics of
It is necessary to reduce C _G and especially C _GD due to the mirror effect, but closed gate J-FETs have a structure with a small gate junction area as mentioned above, so both C _GS and C _GD are small, It is characterized by particularly good high frequency characteristics.

However, this closed gate type J-FET
When a reverse bias voltage is applied to the gate (second gate region) 4, a depletion layer extends from the pn junction 9, but when this depletion layer reaches the first gate region 1 connected to the source region 6, A punch-through phenomenon occurs and current begins to flow. This punch-through phenomenon occurs at a reverse bias voltage of several volts, so the gate of a closed-gate J-FET
The source-to-source breakdown voltage _BVGC had the drawback of being only a few volts.

For this reason, closed gate type J-
FETs cannot be used as they are in circuits that require high BV _GS , and closed gate type J-
Partly because the effectiveness of FETs was not well recognized, conventionally open gate type J
−FET was used.

This invention was made in view of the above points, and in order to take advantage of the features of the closed gate J-FET, it is an object of the present invention to provide a closed gate J-FET that effectively improves the withstand voltage between the gate and source. It is intended to.

Fig. 2 is a planar pattern diagram showing an embodiment of the present invention, Fig. 2b is a sectional view taken along the line B-B, and Fig. 1 shows parts equivalent to the conventional example with the same symbols and their explanations are omitted. do. This embodiment differs from the conventional example shown in FIG. 1 by providing an n-type island region 10 within the p-type isolation region 3 and forming a p-n junction 11 between the two.
The p-type isolation region 3, which is the anode side of the diode constructed in this way, is connected to the source region 6 of the J-FET via the electrode 16 extending above it.
The cathode electrode 16a formed on the surface of the n-type island region 10 on the cathode side of the diode is used as the apparent source electrode of this embodiment.

FIG. 3a is an equivalent circuit showing the voltage application state of this embodiment. In an n-channel FET, the operating voltage is applied between the gate G and the source S so that the gate G side is negative and the source S side is positive. , is applied between the source S and the drain D so that the source S side is negative and the drain D side is positive. Under such voltage application conditions, the reverse breakdown voltage of the diode is
BV _D is the gate-source breakdown voltage of a conventional closed type J-FET when no diode is inserted.
Assuming BV _GS , the apparent gate-source breakdown voltage BV′ _GS of this embodiment is as follows.

BV' _GS = BV _GS + BV _D On the other hand, the drain D/source S circuit has a diode inserted in the forward direction, and when the bias voltage V' _DS is applied to the drain D/source S circuit, the diode Since the build potential V _T of pn junction 11 acts as a reverse bias,
While V' _DS is smaller than V _T , the drain D-source S current I' _DS does not flow. I' _DS starts to flow for the first time when V' _DS becomes larger than V _T and the J-FET starts its operation, but the voltage V' _DS between gate G and drain D when I' _DS starts flowing is V′ _DS = V′ _DS +
Since V′ _GS , even if V′ _GS is zero V, V′ _DG V′ _DS
(≒V _T ) is applied. As a result, the second
At the pn junction 9 between the gate region 4 and channel region 7
This means that a reverse bias voltage equal to V' _DS is applied, and I' _DS of the J-FET in this embodiment is equal to that of the conventional J-FET.
It is smaller than that of FET. Figure 3b is a diagram showing the output characteristics of this embodiment.It does not operate unless V' _DS becomes 0.6V or more, which corresponds to the build potential of the p-n junction. For small signal applications other than
This amount of power loss is not a problem. Also,
The saturated drain current I _DSS is I _DS when V _GS = 0V
In this example, as mentioned above, V′ _SG =
It becomes smaller by the amount of V _T (≒0.6V) applied, but
This will not be a problem at all if _I'DSS is set large and controlled in advance at the manufacturing stage, and the FET can be operated without problems.

In the above embodiments, an n-channel J-FET has been described, but the present invention can also be applied to a p-channel J-FET.

As detailed above, this invention compensates for the shortcoming of the conventional closed-gate J-FET, which has a small BV _GS and has a narrow range of application, by using a structure in which a diode is connected in series with the source. By utilizing J-FET, it is possible to fully utilize its feature of good high frequency characteristics. Furthermore, the build potential between the second gate junction and the diode junction is inserted between the source and gate, so if the voltage is within this range, even if the gate and source are forward biased, the input impedance will remain the same. does not decrease, which has the effect of expanding the degree of freedom in circuit design. Incidentally, since the present invention only requires the insertion of one diode, the manufacturing process and other aspects of the integrated circuit can be manufactured in exactly the same manner as in the prior art, by only partially changing the mask pattern.

[Brief explanation of the drawing]

Figure 1a shows the conventional closed gate type J-
A planar pattern diagram of the FET, FIG. 1b is a sectional view taken along the line B-B of FIG. 1a, FIG. 3. A is a cross-sectional view taken along the line B-B in FIG. 3, and FIG.
FIG. b is an output characteristic diagram of this embodiment, and FIG. 4 is an output characteristic diagram of a conventional J-FET shown for reference. In the figure, 1 is a semiconductor substrate, 2 is a semiconductor layer,
3 is an isolation region, 4 is a second gate region, 5 is a drain region, 6 is a source region, 10 is a semiconductor region, 1
6 is a source electrode. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type constituting a first gate region, a semiconductor layer of a second conductivity type formed on this semiconductor substrate, and other parts formed in this semiconductor layer and having a first conductivity type. a second gate region of the first conductivity type formed in an annular shape at a predetermined distance from the semiconductor substrate within a portion of the semiconductor layer surrounded by an isolation region that is electrically isolated from the semiconductor substrate; , a junction field effect in which a portion of the semiconductor layer surrounded by the annular second gate region is a drain region, and a portion of the semiconductor layer sandwiched between the isolation region and the second gate region is a source region. A transistor, a semiconductor region of a second conductivity type is formed on a part of the surface of the isolation region, and a diode is configured between the transistor and the isolation region, and a source electrode formed on the surface of the source region is connected to the isolation region. A semiconductor integrated circuit device, characterized in that the diode extends to the surface of the region so that the diode can be connected in series to the source circuit of the junction field effect transistor.