JPH0328820B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device using a closed-gate junction field effect transistor (hereinafter referred to as "J-FET").

Recently, composite ICs have been announced that combine various elements with different functions to provide new functions.
One of these is various types of amplifiers with high input impedance and low cross-modulation, or composite ICs that incorporate J-FETs into high-speed integration circuits that take advantage of high slew rates.

J-FETs have features such as higher input impedance, faster switching speed, and lower current-related noise than bipolar transistors. As opposed to an open gate type FET in which the first gate and the second gate are electrically connected, the first gate and the second gate are electrically separated, and the first gate with a large Pn junction area is used as the source. A so-called closed gate type J-FET is being considered, which operates by using a second gate that is electrically connected to the region and has a small junction area as the gate of the J-FET.

The structure and operating principle of a conventional closed gate J-FET will be described below with reference to the drawings.
Figure 1a is a plan pattern diagram of a conventional closed-gate n-channel J-FET, and Figure 1b is a diagram of a conventional closed-gate n-channel J-FET.
FIG. 3 is a sectional view taken along line BB in FIG. In the figure, 1 is a p-type semiconductor layer, 2 is an n-type semiconductor layer formed thereon, 3 is a p-type isolation region for separating a part of the n-type semiconductor layer 2 from other parts, and 4 is a p-type semiconductor layer. A p-type second gate region is formed by diffusing p-type impurities from the surface into a part of the n-type semiconductor layer 2 surrounded by the type isolation region 3 so that the p-type impurity does not reach the p-type semiconductor layer 1. It consists of multiple rectangular areas arranged in a shape. 5 and 6 are p-type second
An n-type drain region and an n-type source region each consisting of a portion of the n-type semiconductor layer 2 formed to sandwich the gate region 4 are shown. 7 is a channel region consisting of a portion sandwiched between the p-type second gate region 4 and the p-type semiconductor layer 1; 8 is a surface insulating film; 9 is between the p-type second gate region 4 and the n-type channel region 7; The p-n junctions 14, 15 and 16 pass through the surface insulating film 8 to form the p-type second gate region 4 and the n-type drain region 5.
and a second gate electrode, a drain electrode, and a source electrode formed so as to be connected to the n-type source region 6, respectively. The p-type semiconductor layer 1 has a function as a first gate region, and the p-type semiconductor layer 1 has a function as a first gate region.
A source electrode 1 is formed passing through the p-type isolation region 3 and extending over the surface of the p-type isolation region 3.
It is electrically connected to the source region 6 via 6.

In this FET, a depletion layer is extended to the channel region 7 by applying a reverse bias voltage between the n-type source region 6 and the p-type second gate region 4, and the depletion layer is extended to the channel region 7. This is a voltage-driven element that operates by changing the conductance through the channel region between them.

The maximum operating frequency at which the J-FET operates is expressed by the figure of merit M: M = g _n /C _G where g _n : Mutual conductance C _G : Gate capacitance = Gate-source capacitance C _GS + Gate-drain capacitance It is expressed as capacitance C _GD . As you can see from the above formula, J-FET
In order to improve the high frequency characteristics of
It is necessary to reduce C _G , especially C _GD due to the Miller effect, but in a closed gate J-FET, as mentioned above, the second gate with a small junction area is used as the gate of the J-FET. Capacity C _G
It has a small structure and has particularly good high frequency characteristics.

However, this closed gate type J-FET
When a reverse bias voltage is applied to the gate (second gate region) 4, a depletion layer extends from the pn junction 9, but when this depletion layer reaches the first gate region 1 connected to the source region 6, a punch occurs. A through phenomenon occurs and current begins to flow. Since this punch-through phenomenon occurs at a reverse bias of several volts, the gate-source breakdown voltage _BVGS of a closed gate type J-FET has a disadvantage of only a few volts.

For this reason, closed gate type J-
FETs cannot be used as they are in circuits that require high _BVGS , and closed gate type J-
Since the effectiveness of FETs was not well recognized, conventionally open gate type J-FETs were used.

This invention was made in view of the above-mentioned drawbacks, and in order to take advantage of the features of the closed-gate J-FET, it is an object of the present invention to provide a closed-gate J-FET that effectively improves the withstand voltage between the gate and source. It is intended to.

Fig. 2a is a planar pattern diagram showing an embodiment of the present invention, and Fig. 2b is a sectional view taken along line B-B of the same, parts equivalent to those of the conventional example in Fig. 1 are designated by the same reference numerals, and explanations thereof are given. is omitted. The difference between this embodiment and the conventional example shown in FIG. 1 is that an n-type island region 10 formed of a p-type isolation region 3 and a p-type semiconductor layer 1 is provided, and a p-n junction 11 is formed between the two. , the p-type region on the anode side of the diode constructed in this way is connected to the source region 6 of the J-FET via the electrode 16 extending above it, and the n-type region on the cathode side of the diode The cathode electrode 16a formed on the surface of the island region 10 is used as an apparent source electrode in this embodiment.

Figure 3a is an equivalent circuit showing the voltage application state of this embodiment. In an n-channel FET, the voltage application for its operation is such that between the gate G and source S, the gate G side is negative and the source S side is positive. is applied to
Further, between the source S and the drain D, the voltage is applied so that the source S side is negative and the drain D side is positive. Under such voltage application conditions, the reverse breakdown voltage of the diode is BV _D , and the gate voltage of the conventional closed gate J-FET when no diode is inserted is
Assuming that the source-to-source breakdown voltage is _BVGS , the apparent gate-source breakdown voltage _BVGS ' of the embodiment of the present invention is as follows.

BV _GS ′ = BV _GS + BV _D On the other hand, a diode is inserted between the drain D and source S in the forward direction, and when a bias voltage V _DS ′ is applied between the drain D and source S, Since the built-in potential V _T of the pn junction 11 of the diode acts as a reverse bias, the drain D-source S current I _DS ' does not flow while V _DS ' is smaller than V _T . When V _DS ′ becomes larger than V _T , I _DS ′ starts to flow and the J-FET starts its operation, but the gate-drain voltage V _DG ′ until I _DS ′ starts flowing is
Since V _DG ′=V _GS ′+V _DS ′, even if V _GS ′ is zero V, V _DG ′=V _DS ′ (≈V _T ) is applied. As a result, a reverse bias voltage equal to V _DS ' is applied to the pn junction 9 between the second gate region 4 and the channel region 7, and V _GS '= of the J-FET according to the embodiment of the present invention. I _DSS ', which is I _DS ' at the time of OV, is smaller than I _DSS of the conventional J-FET.

Figure 3b is a diagram showing the output characteristics of the embodiment of the present invention, and it does not operate unless V _DS exceeds the build-in potential of the pn junction, approximately 0.6 V, and during this time, power is consumed as heat loss and other power losses. However, for small signal applications other than power, this level of power loss is not a problem.

In addition, in this example, the saturated drain current I _DSS , which is I _DS when V _GS = OV, is the same as that of the conventional J-FET whose output characteristics are shown for reference in Figure 4, as described above.
Therefore, it becomes smaller by the amount that V _SG ′=V _T (≒0.6V) is applied, but if I _DSS ′ is set large and controlled in advance at the manufacturing stage, this will not be a problem at all and it will work as an FET without any problems. be able to.

In this way, in this embodiment, the diode is configured so that the source region of the J-FET and its anode are connected, so that the withstand voltage between the source and gate of the J-FET can be substantially improved. In addition, since the semiconductor region that is the second gate is formed into a striped region in which a plurality of rectangular regions are arranged, the gate length can be increased using a limited substrate space by reducing the stripe width and increasing the rectangular region. It can be easily done with.

In the above embodiments, an n-channel J-FET has been described, but the present invention can also be applied to a p-channel J-FET. Furthermore, the diode has an n-type island region 10 in the p-type isolation region 3 as shown in FIG.
It is also possible to have a structure in which a is formed.

As detailed above, this invention compensates for the shortcoming of the conventional closed-gate J-FET, which has a small BV _GS and has a narrow range of application, by using a structure in which a diode is connected in series with the source. By utilizing J-FET, it is possible to fully utilize its feature of good high frequency characteristics. Furthermore, the built-in potential between the junction of the second gate part and the diode junction is inserted as a reverse bias between the source and the gate, so if the voltage value is within this range, the gate and source will be forward biased. Even if the input impedance is changed, the input impedance does not decrease, which has the effect of expanding the degree of freedom in circuit design.

In addition, since the semiconductor region that is the second gate of the J-FET is a planar stripe-like region with a plurality of rectangular regions arranged, by increasing the number of rectangular regions, the gate length can be made sufficiently long with limited substrate space. There is also the effect that the desired voltage amplification factor can be set.

[Brief explanation of drawings]

Figure 1a shows the conventional closed gate type J-
A planar pattern diagram of the FET, FIG. 1b is a sectional view taken along the line B-B of FIG. 1a, FIG. 3. A is a cross-sectional view taken along the line B-B in FIG. 3, and FIG.
Figure b is an output characteristic diagram of this embodiment, Figure 4 is an output characteristic diagram of a conventional J-FET shown for reference, and Figure 5 is a sectional view showing the configuration of the diode section of another embodiment of the present invention. be. In the figure, 1 is a first semiconductor layer, 2 is a second semiconductor layer, 3 is an isolation region, 4 is a second gate region,
5 is a drain region, 6 is a source region, 10 and 1
0a is the cathode region of the diode, 14 is the second gate electrode, 15 is the drain electrode, 16 and 16a
is the source electrode. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A second conductivity type operating region separated by a first conductivity type separation region is formed on a first conductivity type substrate region, and a first conductivity type operating region is selectively formed on a surface portion of the second conductivity type operating region.
forming a conductivity type semiconductor region; the first conductivity type substrate region and the first conductivity type semiconductor region are respectively used as first and second gate regions; and the second conductivity type operation is performed on both sides of the second gate region. In a semiconductor device comprising a closed gate J-FET in which regions are respectively used as a source region and a drain region, the first conductivity type semiconductor region is formed by arranging a plurality of rectangular regions in a stripe shape, A second conductivity type semiconductor formed in the first conductivity type isolation region so as to selectively extend from a part of the surface of the isolation region to the first conductivity type substrate region, with the first conductivity type isolation region serving as an anode. A diode having the region as a cathode is provided, and the first
A source electrode is formed so as to extend to the surface of the conductive type separation region, and the source electrode allows the above-mentioned J-
A semiconductor device characterized in that a first gate region of a FET and the source region are connected, and an anode of the diode and the source region are connected.