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JPS6350916B2 - - Google Patents
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JPS6350916B2 - - Google Patents

Info

Publication number
JPS6350916B2
JPS6350916B2 JP13786482A JP13786482A JPS6350916B2 JP S6350916 B2 JPS6350916 B2 JP S6350916B2 JP 13786482 A JP13786482 A JP 13786482A JP 13786482 A JP13786482 A JP 13786482A JP S6350916 B2 JPS6350916 B2 JP S6350916B2
Authority
JP
Japan
Prior art keywords
channel
time division
information
input
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13786482A
Other languages
Japanese (ja)
Other versions
JPS5928791A (en
Inventor
Yoshinori Yoshida
Keiichi Myahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP13786482A priority Critical patent/JPS5928791A/en
Publication of JPS5928791A publication Critical patent/JPS5928791A/en
Publication of JPS6350916B2 publication Critical patent/JPS6350916B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Description

【発明の詳細な説明】 本発明は、時分割通話路に関し、特にインチヤ
ネル制御に適用し得る時分割空間スイツチからな
る時分割通話路方式に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time-division channel, and more particularly to a time-division channel system comprising a time-division space switch that can be applied to channel control.

従来、この種の時分割空間スイツチは、第1図
に示すように、論理ゲートGATEと、その論理
ゲートGATEを制御する通話路制御装置SWCよ
りの制御データを保持するメモリCTLMとを有
し、その制御データによつて論理ゲートGATE
の開閉を行なうことにより、入力時分割多重回線
IN1〜oを出力多重回線OUT1〜nへ各チヤネル毎に
スイツチングする構成となつている。そのため、
これらの交換動作の制御は、この時分割スイツチ
に接続された通話路制御装置で集中管理され、
又、通話路接続の呼損制御(チヤネル整合処理)
もこの制御装置の制御下となり、交換制御機能の
分散化が困難となる欠点があつた。
Conventionally, as shown in FIG. 1, this type of time-division space switch has a logic gate GATE and a memory CTLM that holds control data from a channel control device SWC that controls the logic gate GATE. Logic gate GATE by its control data
By opening and closing the input time division multiplex line,
The configuration is such that IN 1 to o are switched to output multiplex lines OUT 1 to n for each channel. Therefore,
Control of these switching operations is centrally managed by a communication path control device connected to this time division switch.
Also, call loss control (channel matching processing) for communication path connections.
It also had the disadvantage that it was under the control of this control device, making it difficult to decentralize the exchange control function.

本発明は、斯かる欠点に鑑みてなされたもの
で、時分割空間スイツチの入力時分割多重回線の
各チヤネルのチヤネル情報として出力路を制御す
る制御情報を含む構成とし、本情報をもとに自律
的に出方路へスイツチングする構成とすることに
より、上記欠点を解決し、交換制御機能の分散化
を可能とする時分割通話路方式を提供することを
目的とする。
The present invention has been made in view of such drawbacks, and has a configuration that includes control information for controlling the output path as channel information of each channel of the input time division multiplex line of the time division space switch, and based on this information. It is an object of the present invention to provide a time-division communication path system that solves the above-mentioned drawbacks and enables decentralization of switching control functions by autonomously switching to an outgoing path.

即ち、本発明は、各チヤネルのチヤネル情報を
通話路制御情報と通信情報とから成る構成とし、
n本の多重度kの時分割多重回線を入力とすると
共に、n本の各入力チヤネル情報を保持し、該入
力チヤネル情報の通話路制御情報により出力すべ
きチヤネル情報を選択する構成とした時分割スイ
ツチ機能ユニツトを設け、且つ、該時分割スイツ
チ機能ユニツトをm個配備すると共に、各ユニツ
トに上記n本の時分割多重回線をそれぞれ入力さ
せて、n×mの時分割空間スイツチを構成して成
るものである。
That is, the present invention configures the channel information of each channel to consist of call path control information and communication information,
When n time-division multiplexed lines with multiplicity k are input, information on each n input channel is held, and channel information to be output is selected based on call path control information of the input channel information. A division switch functional unit is provided, and m time division switch function units are provided, and each unit is inputted with the above n time division multiplex lines to form an n×m time division space switch. It consists of

以下、本発明を図面に示す実施例に基づいて説
明する。
Hereinafter, the present invention will be explained based on embodiments shown in the drawings.

第2図は本発明の一実施例を示すブロツク図で
ある。図において本発明時分割通話路方式は、m
個の時分割スイツチ機能ユニツトSU1〜SUmを
備えて成り、各時分割スイツチ機能ユニツトSU1
〜SUmには、シリアルパラレル変換回路S/P1
〜S/Pnと、制御回路CTLと、出力ゲート回路
G1〜Gnと、パラレルシリアル変換回路P/Sと
を備えて構成される。
FIG. 2 is a block diagram showing one embodiment of the present invention. In the figure, the time division communication path system of the present invention is m
The time-division switch function unit SU 1 to SUm is comprised of three time-division switch function units SU 1 to SUm.
~SUm has a serial-parallel conversion circuit S/P 1
~S/Pn, control circuit CTL, and output gate circuit
It is configured to include G 1 to Gn and a parallel/serial conversion circuit P/S.

時分割スイツチ機能ユニツトSU1〜SUmは、
多重度kの入力時分割多重回線IN1〜INnがシリ
アルパラレル変換回路S/P1〜S/Pnにマルチ
接続され、各ユニツトSU1〜SUmはチヤネル毎
に動作する。
The time division switch function units SU 1 to SUm are
Input time division multiplex lines IN 1 -INn with multiplicity k are multi-connected to serial-parallel conversion circuits S/P 1 -S/Pn, and each unit SU 1 -SUm operates for each channel.

上記シリアルパラレル変換回路S/P1〜S/
Pnは、上記多重回線IN1〜INnからの入力チヤネ
ル情報を保持する。このチヤネル情報は、出方路
を示す制御情報と通信情報とから成る。前者は制
御回路CTLへ、後者は出力ゲート回路G1〜Gnへ
分配される。
The above serial-parallel conversion circuit S/P 1 ~S/
Pn holds input channel information from the multiplex lines IN 1 to INn. This channel information consists of control information indicating the outgoing route and communication information. The former is distributed to the control circuit CTL, and the latter is distributed to the output gate circuits G 1 to Gn.

上記制御回路CTLは、上記制御情報を調べ、
どの出方路かを調べると共に、複数の同一出方路
使用要求がないかを調べる。この結果、複数の要
求があつた時は、所定のプライオリテイー(優先
順位)ルールによつて、どれか一つを選択し、そ
の入力チヤネルには接続可情報を、一方、他の入
力チヤネルに対しては接続不可情報をそれぞれ付
加し、出力チヤネル情報として該当するスイツチ
機能ユニツトSU1〜SUmへ制御バスBUSを介し
て通知する。
The control circuit CTL examines the control information,
In addition to checking which outgoing route it is, it is also checked to see if there are multiple requests to use the same outgoing route. As a result, when multiple requests are received, one is selected according to a predetermined priority rule, and connectability information is sent to that input channel, while information to other input channels is sent. For each, connectability information is added and notified as output channel information to the corresponding switch function units SU 1 to SUm via the control bus BUS.

上記各ユニツトSU1〜SUmのパラレルシリア
ル変換回路P/S1〜P/Smは、それぞれ対応す
る出力時分割多重回線OUT1〜OUTmに接続さ
れており、上記選択された出力チヤネル情報がセ
ツトされ、対応する回線OUT1〜OUTmの出力
となる。
The parallel-to-serial conversion circuits P/S 1 to P/Sm of the units SU 1 to SUm are connected to the corresponding output time division multiplex lines OUT 1 to OUTm, and the selected output channel information is set. , the outputs of the corresponding lines OUT 1 to OUTm.

この本発明時分割通話路方式は、一般的に、第
3図に示すように、n=mとして使用され、又、
入力時分割多重回線IN1〜INnと出力時分割多重
回線OUT1〜OUTnは、各々<IN、OUT1>〜<
INn、OUTn>のペアとして使用され、これらが
複数の交換装置SWEQ1〜SWEQnに接続される。
これらの交換装置SWEQ1〜SWEQnは、独立に
時分割空間スイツチSSWに接続アクセスを行な
う。
The time-division channel system of the present invention is generally used with n=m as shown in FIG.
The input time division multiplex lines IN 1 ~ INn and the output time division multiplex lines OUT 1 ~ OUTn are <IN, OUT 1 > ~ <, respectively.
INn, OUTn> are used as a pair, and these are connected to a plurality of switching devices SWEQ 1 to SWEQn.
These switching devices SWEQ 1 to SWEQn independently connect and access the time division space switch SSW.

第4図に上述したチヤネル情報の一構成例を示
す。同図に示すものは、フレーム内にk個のチヤ
ネル情報が多重化されている。チヤネル情報は、
制御データフイールドCTLFと通信情報フイール
ドDATAとからなる。制御データフイールド
CTLFは、動作モード指定MOD及び出方路指定
アドレスOUTDTから構成される。動作モード
MODとしては、入力チヤネルの場合、バス接続
の要求、プライオリテイデータ等の情報から成
り、一方、出力チヤネルの場合、パス接続可情
報、呼損情報等から成る。一例を示すと、入力チ
ヤネルのプライオリテイとして一旦パス接続可と
なつた後は、プライオリテイの一番高いデータを
付加して送出すれば、そのチヤネルを通路中継続
して使用することができる。
FIG. 4 shows an example of the structure of the channel information described above. In what is shown in the figure, k pieces of channel information are multiplexed within a frame. Channel information is
It consists of a control data field CTLF and a communication information field DATA. control data field
CTLF consists of an operation mode designation MOD and an output route designation address OUTDT. action mode
In the case of an input channel, the MOD consists of information such as a bus connection request and priority data, while in the case of an output channel, it consists of information such as path connection availability information and call loss information. For example, once the priority of an input channel allows path connection, if data with the highest priority is added and transmitted, that channel can be used continuously throughout the path.

本発明は、以上説明したように、チヤネル情報
を通話路制御情報と通信情報とから成る構成と
し、該通話路制御情報を用いて自律的に出方路を
選択する機能を有する時分割スイツチ機能ユニツ
トを備えたことにより、交換制御機能の分散化に
適した時分割通話路を構成できる効果がある。
As explained above, the present invention has a time-division switch function in which channel information is composed of call route control information and communication information, and has a function of autonomously selecting an outgoing route using the call route control information. The provision of the unit has the effect of configuring a time-division communication path suitable for decentralizing switching control functions.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の時分割空間スイツチを示すブロ
ツク図、第2図は本発明時分割通話路方式の一実
施例を示すブロツク図、第3図は本発明時分割通
話路方式の交換装置との一般的な接続例を示すブ
ロツク図、第4図はチヤネル情報の構成の一例を
示す説明図である。 SU1〜SUm……時分割スイツチ機能ユニツト、
S/P1〜S/Pn……シリアルパラレル変換回路、
CTL……制御回路、G1〜Gm……出力ゲート回
路、P/S1〜P/Sm……パラレルシリアル変換
回路。
FIG. 1 is a block diagram showing a conventional time-division space switch, FIG. 2 is a block diagram showing an embodiment of the time-division channel system of the present invention, and FIG. 3 is a block diagram showing a switching device of the time-division channel system of the present invention. FIG. 4 is an explanatory diagram showing an example of the structure of channel information. SU 1 ~ SUm……Time division switch function unit,
S/P 1 ~ S/Pn...Serial parallel conversion circuit,
CTL...Control circuit, G1 ~Gm...Output gate circuit, P/ S1 ~P/Sm...Parallel-serial conversion circuit.

Claims (1)

【特許請求の範囲】 1 各チヤネルのチヤネル情報を通話路制御情報
と通信情報とからなる構成とし、 n本の多重度k(kは1以上の整数)の入力時
分割多重回線を入力すると共に、該回線からのn
本の各入力チヤネル情報を保持し、該入力チヤネ
ル情報の通話路制御情報により通信情報を出力す
べきチヤネルを選択する時分割スイツチ機能ユニ
ツトを設け、 かつ該時分割スイツチ機能ユニツトをm個配備
すると共に、該m個の時分割スイツチ機能ユニツ
トにわたつてn本の上記入力時分割多重回線をマ
ルチ接続し、m本の出力時分割多重回線を上記m
個の時分割スイツチ機能ユニツトの各々に一対一
に対応させて接続することによりn×mの時分割
空間スイツチを構成し、m本の出力時分割多重回
線へn本の入力の任意の入力チヤネルを出力する
ことを特徴とする時分割通話路方式。
[Claims] 1. The channel information of each channel is composed of communication path control information and communication information, and when n input time division multiplex lines with multiplicity k (k is an integer of 1 or more) are input, , n from the line
A time division switch function unit that holds information on each input channel of the book and selects a channel to which communication information is to be output based on communication path control information of the input channel information is provided, and m pieces of the time division switch function units are provided. At the same time, the n input time division multiplex lines are multi-connected across the m time division switch functional units, and the m output time division multiplex lines are connected to the m time division multiplex function units.
By connecting each of the time division switch functional units in a one-to-one correspondence, an n×m time division space switch is configured, and any input channel of n inputs is connected to m output time division multiplex lines. A time-division channel system characterized by outputting .
JP13786482A 1982-08-10 1982-08-10 Time division channel system Granted JPS5928791A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13786482A JPS5928791A (en) 1982-08-10 1982-08-10 Time division channel system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13786482A JPS5928791A (en) 1982-08-10 1982-08-10 Time division channel system

Publications (2)

Publication Number Publication Date
JPS5928791A JPS5928791A (en) 1984-02-15
JPS6350916B2 true JPS6350916B2 (en) 1988-10-12

Family

ID=15208524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13786482A Granted JPS5928791A (en) 1982-08-10 1982-08-10 Time division channel system

Country Status (1)

Country Link
JP (1) JPS5928791A (en)

Also Published As

Publication number Publication date
JPS5928791A (en) 1984-02-15

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