JPS6351608B2 - - Google Patents
Info
- Publication number
- JPS6351608B2 JPS6351608B2 JP58018149A JP1814983A JPS6351608B2 JP S6351608 B2 JPS6351608 B2 JP S6351608B2 JP 58018149 A JP58018149 A JP 58018149A JP 1814983 A JP1814983 A JP 1814983A JP S6351608 B2 JPS6351608 B2 JP S6351608B2
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- signal
- output
- value
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Dc Digital Transmission (AREA)
- Analogue/Digital Conversion (AREA)
Description
本発明は、デジタル通信方式における多値振幅
信号を識別する多値識別器に関し、特に受信々号
を増幅してアナログデジタル変換器に入力させる
直流増幅器の利得およびオフセツトを適切に制御
するための回路に関する。
従来の多値識別器は、第１図に示すように構成
されている。すなわち、2n値の多値振幅信号１が
直流増幅器４によつて所定のレベルに増幅され、
直流増幅器４の出力がクロツク２に同期してアナ
ログデジタル変換器（Ａ／Ｄ）５によつてデジタ
ル信号に変換出力される。アナログデジタル変換
器５はｎビツト出力の変換器であり、入力信号を
2n値に識別してｎビツトのデジタル信号３に変換
出力する。上述の従来の多値識別器は、直流増幅
器４の出力が温度変化等によつて変動すると、正
しく識別するためのマージンが減少し、甚だしい
ときは識別誤りを生じるという欠点がある。この
欠点は、入力信号の振幅多値化が大になるに従つ
て著しくなる。また、入力信号のレベル変動によ
つても識別誤りを発生するから、増幅器４の利得
を適切にするためには、例えば所定符号の信号が
所定レベルに増幅されるようにデータ伝送に先立
つて調整作業が必要となる。
本発明の目的は、上述の従来の欠点を解決し、
受信々号を増幅する直流増幅器の利得とオフセツ
トを自動的に調整することによつて、アナログデ
ジタル変換器の入力レベルを常時最適に保ち、良
好な多値識別を行なう多値識別器を提供すること
にある。
本発明の識別器は、2n（ｎは正の整数）値の多
値振幅信号を増幅する直流増幅器を備えて、該直
流増幅器の出力レベルによつて2n値の多値識別を
行なう多値識別器において、前記直流増幅器は利
得およびオフセツトが独立に制御可能に構成さ
れ、該直流増幅器の出力レベルをｎ＋１ビツトの
デジタル値に変換出力するアナログデジタル変換
器と、該アナログデジタル変換器の１つのビツト
出力または複数のビツト出力の組合わせによつて
前記直流増幅器のオフセツトを制御するオフセツ
ト制御回路および前記直流増幅器の利得を制御す
る利得制御回路とを備えたことを特徴とする。
次に、本発明について、図面を参照して詳細に
説明する。
第２図は、本発明の一実施例を示すブロツク図
である。すなわち、2nの多値振幅信号１を直流増
幅器４に入力させ、直流増幅器４の出力レベルは
ｎ＋１ビツト出力のアナログデジタル変換器５′
でクロツク信号２に同期してサンプリングされて
ｎ＋１ビツトのデジタル信号３′に変換出力され
る。該ｎ＋１ビツトのデジタル信号３′を制御回
路６に入力させ、制御回路６は、上記デジタル信
号の１ビツト出力または複数ビツト出力の組合わ
せによつて前記直流増幅器４のオフセツトを制御
するための制御信号８および利得を制御するため
の制御信号９を出力する。制御信号８，９をそれ
ぞれ低域通過フイルタ７を介して平滑化した制御
信号８′，９′が直流増幅器４に供給される。直流
増幅器４は、制御信号８′，９′によつてオフセツ
トおよび利得が制御される直流増幅器である。本
実施例では、直流増幅器４の利得およびオフセツ
トが最適に制御されるから、アナログデジタル変
換器５′は常時最適な識別レベルで識別可能とな
る。従つて、多値数が多くても正確に識別するこ
とができる。
上述の制御回路６は、例えば第３図に示すよう
に構成することができる。第３図は、４値の多値
識別器に対して３ビツト出力のデジタルアナログ
変換器５′を用いた構成例である。この場合、デ
ジタルアナログ変換器５′は、所定の入力電圧を
８段階に等分に区分して３ビツトのデジタル信号
に変換出力するが、最下位ビツト出力をオフセツ
The present invention relates to a multi-value discriminator for identifying multi-value amplitude signals in digital communication systems, and in particular to a circuit for appropriately controlling the gain and offset of a DC amplifier that amplifies a received signal and inputs it to an analog-to-digital converter. Regarding. A conventional multivalued discriminator is configured as shown in FIG. That is, a multi-level amplitude signal 1 of 2n values is amplified to a predetermined level by a DC amplifier 4,
The output of the DC amplifier 4 is converted into a digital signal by an analog-to-digital converter (A/D) 5 in synchronization with the clock 2. The analog-to-digital converter 5 is an n-bit output converter, and converts the input signal into
2 It identifies the n value and converts it into an n-bit digital signal 3 and outputs it. The above-mentioned conventional multi-level discriminator has the drawback that when the output of the DC amplifier 4 fluctuates due to temperature changes or the like, the margin for correct discrimination decreases, and in severe cases, a discrimination error occurs. This drawback becomes more noticeable as the input signal becomes more multivalued in amplitude. In addition, since identification errors also occur due to level fluctuations in the input signal, in order to make the gain of the amplifier 4 appropriate, for example, it is necessary to adjust the gain of the amplifier 4 prior to data transmission so that the signal of a predetermined code is amplified to a predetermined level. Work is required. The purpose of the present invention is to solve the above-mentioned conventional drawbacks and
To provide a multi-value discriminator that always maintains the input level of an analog-to-digital converter at an optimum level and performs good multi-value discrimination by automatically adjusting the gain and offset of a DC amplifier that amplifies a received signal. There is a particular thing. The discriminator of the present invention includes a DC amplifier that amplifies a multi-value amplitude signal of 2 n (n is a positive integer) value, and performs multi-value discrimination of 2 n values based on the output level of the DC amplifier. In the value discriminator, the DC amplifier is configured such that its gain and offset can be controlled independently, and includes an analog-to-digital converter that converts the output level of the DC amplifier to an n+1-bit digital value, and one of the analog-to-digital converters. The present invention is characterized by comprising an offset control circuit that controls the offset of the DC amplifier by one bit output or a combination of a plurality of bit outputs, and a gain control circuit that controls the gain of the DC amplifier. Next, the present invention will be explained in detail with reference to the drawings. FIG. 2 is a block diagram showing one embodiment of the present invention. That is, the 2n multi-level amplitude signal 1 is input to the DC amplifier 4, and the output level of the DC amplifier 4 is set to the analog-to-digital converter 5' with an n+1 bit output.
The signal is sampled in synchronization with the clock signal 2 and converted into an n+1 bit digital signal 3'. The n+1-bit digital signal 3' is input to a control circuit 6, and the control circuit 6 performs control for controlling the offset of the DC amplifier 4 by a combination of one bit output or a plurality of bit outputs of the digital signal. A signal 8 and a control signal 9 for controlling the gain are output. Control signals 8' and 9', which are obtained by smoothing the control signals 8 and 9 through a low-pass filter 7, are supplied to the DC amplifier 4. The DC amplifier 4 is a DC amplifier whose offset and gain are controlled by control signals 8' and 9'. In this embodiment, since the gain and offset of the DC amplifier 4 are optimally controlled, the analog-to-digital converter 5' can always be identified at an optimal identification level. Therefore, even if the number of multivalues is large, accurate identification is possible. The above-mentioned control circuit 6 can be configured as shown in FIG. 3, for example. FIG. 3 shows an example of a configuration in which a 3-bit output digital-to-analog converter 5' is used for a 4-value multi-value discriminator. In this case, the digital-to-analog converter 5' divides the predetermined input voltage equally into eight stages and converts it into a 3-bit digital signal, but offsets the least significant bit output.
【表】
今、アナログデジタル変換器５′の入力レベル
に正のオフセツトがある場合は、第３ビツト（最
下位ビツト）は＋１になることが多くなる。ま
た、オフセツトが負であれば逆に第３ビツトは−
１になる頻度が多くなる。従つて、第３ビツト出
力を制御信号８とし、これを低域通過フイルタ７
で平滑化した制御信号８′で直流増幅器４のオフ
セツトを制御すれば、直流増幅器４のオフセツト
を最適にすることができる。すなわち、この場合
は、最下位ビツト出力と低域通過フイルタとでオ
フセツト制御回路を構成し、これによつて直流増
幅器のオフセツトを制御して、４値のアナログ信
号の中心レベルを最適化することができる。
次に、増幅器の利得が過大である場合は、入力
アナログ信号の上、下限間の幅が拡大するから、
入力アナログ信号が中心レベルV1より高く、従
つて最上位ビツト出力が＋１となるような入力に
対しては、第３ビツト出力が＋１になることが多
くなる。一方、入力アナログ信号が中心レベル
V1より低く、従つて最上位ビツト出力が−１と
なるような入力信号に対しては、第３ビツト出力
は−１となることが多くなる。この結果、排他的
論理和回路１０は、上記いずれの場合にも−１を
出力することが多くなるから、排他的論理和回路
１０の出力を利得制御用の制御信号９とし、これ
を低域通過フイルタ７で平滑化した制御信号９′
により直流増幅器４の利得を減少させるように制
御すれば適切な利得に制御することができる。逆
に、増幅器の利得が過小である場合は、上述と同
様に第１ビツト出力が１となるような入力信号に
対しては第３ビツト出力が−１になることが多
く、第１ビツト出力が−１となるような入力信号
に対しては第３ビツト出力が１となることが多い
から、排他的論理和回路１０の出力は＋１となる
ことが多くなる。従つて、これを平滑化した制御
信号９′によつて直流増幅器４の利得が増大され、
最適な利得に制御される。この場合、排他的論理
和回路１０と低域通過フイルタとで利得制御回路
を構成している。上述の制御は、通常のデータ伝
送中に自動的に行なわれるから、アナログデジタ
ル変換器５′の入力信号は、常時最適のレベル範
囲に保たれ、かつその中心値も最適化される。
一般に、2n値の多値振幅信号の場合において
も、入力信号をｎ＋１ビツトのデジタル信号に変
換出力させれば、その最下位ビツト出力によつて
オフセツト調整をすることができ、最上位ビツト
出力と最下位ビツト出力の排他的論理和をとるこ
とによつて利得調整をすることができる。従つ
て、多値数が多い場合であつても、最適レベルの
信号を作成し正確に多値識別することが可能とな
るという効果がある。[Table] Now, if there is a positive offset in the input level of the analog-to-digital converter 5', the third bit (the least significant bit) will often be +1. Also, if the offset is negative, the third bit will be -
1 more often. Therefore, the third bit output is used as the control signal 8, and this is passed through the low-pass filter 7.
By controlling the offset of the DC amplifier 4 using the smoothed control signal 8', the offset of the DC amplifier 4 can be optimized. That is, in this case, an offset control circuit is configured with the least significant bit output and a low-pass filter, and the offset of the DC amplifier is controlled thereby to optimize the center level of the 4-value analog signal. I can do it. Next, if the gain of the amplifier is excessive, the width between the upper and lower limits of the input analog signal will expand.
For inputs where the input analog signal is higher than the center level V1 , and therefore the most significant bit output is +1, the third bit output will often be +1. On the other hand, the input analog signal is at the center level.
For input signals that are lower than V 1 and therefore the most significant bit output is -1, the third bit output will often be -1. As a result, the exclusive OR circuit 10 often outputs -1 in any of the above cases, so the output of the exclusive OR circuit 10 is used as the control signal 9 for gain control, and this is used as the low frequency Control signal 9' smoothed by pass filter 7
By controlling the gain of the DC amplifier 4 to reduce it, the gain can be controlled to an appropriate value. Conversely, if the gain of the amplifier is too small, the third bit output will often be -1 for an input signal for which the first bit output is 1, as described above, and the first bit output will be -1. Since the third bit output is often 1 for an input signal in which the value is -1, the output of the exclusive OR circuit 10 is often +1. Therefore, the gain of the DC amplifier 4 is increased by the smoothed control signal 9'.
Controlled to optimal gain. In this case, the exclusive OR circuit 10 and the low-pass filter constitute a gain control circuit. Since the above-mentioned control is automatically performed during normal data transmission, the input signal of the analog-to-digital converter 5' is always maintained within the optimum level range, and its center value is also optimized. In general, even in the case of a multi-value amplitude signal with 2n values, if the input signal is converted to an n+1 bit digital signal and output, offset adjustment can be performed using the least significant bit output, and the most significant bit output The gain can be adjusted by taking the exclusive OR of the output of the least significant bit. Therefore, even when the number of multilevel values is large, it is possible to create a signal at an optimal level and perform multilevel discrimination accurately.
第１図は従来の多値識別器の一例を示すブロツ
ク図、第２図は本発明の一実施例を示すブロツク
図、第３図は４値識別器に適用した場合の制御回
路の構成例を示す図、第４図は入力信号の識別レ
ベルを示す図である。
図において、１……2n値の多値信号、２……ク
ロツク信号、３……ｎビツトのデジタル信号、
３′……ｎ＋１ビツトのデジタル信号、４……直
流増幅器、５，５′……アナログデジタル変換器、
６……制御回路、７……低域通過フイルタ、８…
…オフセツト用の制御信号、８′……平滑化され
たオフセツト用の制御信号、９……利得制御用の
制御信号、９′……平滑化された利得制御用の制
御信号、１０……排他的論理和回路。
Fig. 1 is a block diagram showing an example of a conventional multi-value discriminator, Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is an example of the configuration of a control circuit when applied to a four-value discriminator. FIG. 4 is a diagram showing the discrimination level of the input signal. In the figure, 1...2 n -value multi-value signal, 2... clock signal, 3... n-bit digital signal,
3'...n+1 bit digital signal, 4...DC amplifier, 5,5'...analog-digital converter,
6...Control circuit, 7...Low pass filter, 8...
...Control signal for offset, 8'...Smoothed control signal for offset, 9...Control signal for gain control, 9'...Smoothed control signal for gain control, 10...Exclusive logical OR circuit.
Claims (1)
する直流増幅器を備えて、該直流増幅器の出力レ
ベルによつて2n値の多値識別を行う多値識別器に
おいて、前記直流増幅器は利得およびオフセツト
が独立に制御可能に構成され、該直流増幅器の出
力レベルをｎ＋１ビツトのデジタル値に変換出力
するアナログデジタル変換器と、該アナログデジ
タル変換器出力の最下位ビツト（LSB）を平滑
化して前記直流増幅器のオフセツトを制御する第
一の低域通過手段と、前記アナログデジタル変換
器出力の最下位ビツト（LSB）と最上位ビツト
（MSB）の排他的論理和をとる手段と、該排他的
論理和出力を平滑化して前記直流増幅器の利得を
制御する第二の低域通過手段とを備えたことを特
徴とする多値識別器。The multi-value discriminator is equipped with a DC amplifier that amplifies a multi-value amplitude signal of 1 2 n (n is a positive integer) value, and performs multi-value discrimination of 2 n values according to the output level of the DC amplifier, The DC amplifier is configured such that its gain and offset can be controlled independently, and includes an analog-to-digital converter that converts the output level of the DC amplifier to an n+1-bit digital value, and a least significant bit (LSB) of the output of the analog-to-digital converter. first low-pass means for smoothing the output of the DC amplifier to control the offset of the DC amplifier; and means for taking an exclusive OR of the least significant bit (LSB) and the most significant bit (MSB) of the output of the analog-to-digital converter. , and second low-pass means for smoothing the exclusive OR output to control the gain of the DC amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1814983A JPS59144218A (en) | 1983-02-08 | 1983-02-08 | Multilevel discriminator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1814983A JPS59144218A (en) | 1983-02-08 | 1983-02-08 | Multilevel discriminator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59144218A JPS59144218A (en) | 1984-08-18 |
| JPS6351608B2 true JPS6351608B2 (en) | 1988-10-14 |
Family
ID=11963550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1814983A Granted JPS59144218A (en) | 1983-02-08 | 1983-02-08 | Multilevel discriminator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59144218A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61236217A (en) * | 1985-04-11 | 1986-10-21 | Nec Corp | Offset voltage correction circuit |
| JPS6272227A (en) * | 1985-09-26 | 1987-04-02 | Fujitsu Ltd | Automatic gain control circuit |
| JP4886927B2 (en) * | 2000-05-31 | 2012-02-29 | 三陽機器株式会社 | Push-pull cable connection mechanism |
| EP1473831A1 (en) * | 2003-04-28 | 2004-11-03 | CoreOptics, Inc., c/o The Corporation Trust Center | Method and circuit for controlling amplification |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE369338B (en) * | 1973-04-11 | 1974-08-19 | Munters Ab Carl | |
| JPS5597731A (en) * | 1979-01-22 | 1980-07-25 | Hitachi Ltd | Analog-digital converter |
-
1983
- 1983-02-08 JP JP1814983A patent/JPS59144218A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59144218A (en) | 1984-08-18 |
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