JPH0669187B2 - Multi-value identification circuit - Google Patents

Description

The present invention relates to a multilevel discriminating circuit for discriminating and reproducing a multilevel amplitude modulated signal in a digital communication system, and particularly to amplifying a received multilevel amplitude modulated signal and outputting it to an analog digital converter. It relates to a circuit for properly controlling the gain of the DC amplifier and the DC voltage offset.

<Prior Art> A conventional multilevel discriminator is configured as shown in FIG. That is, the 2n-valued (n is an integer of 2 or more) multi-valued amplitude signal from the signal input terminal 11 is amplified to a predetermined level by the DC amplifier 12, and the output of the DC amplifier 12 is output from the clock input terminal 13. Converted to a digital signal by an analog / digital converter (A / D) 14 in synchronism with the clock,
Is output. The analog digital converter 14 is an n-bit output converter, which discriminates the input signal into 2n values and outputs n + 1.
Converted to bit digital signal 15 and output. Control circuit
16 outputs a control signal 17 for controlling the DC voltage offset of the DC amplifier 12 and a control signal 18 for controlling the gain by the combination of one-bit output or multiple-bit output of the digital signal 15. The control signals 17 and 18 are low-pass filters 21 and
It is smoothed via 22 and is supplied to the DC amplifier 12 as control signals 23, 24. The control signals 23 and 24 automatically adjust the offset and gain of the DC amplifier 12, respectively. As a result, the input level of the analog / digital converter 14 can always be kept optimum.

The above-mentioned conventional multi-level discrimination circuit is effective for output signal fluctuations of low frequency components caused by temperature fluctuations, etc., but once it falls into the pseudo pull-in state due to sudden disturbance due to fading, etc. It has the drawback of being stable and continuing to generate identification errors. This drawback becomes very remarkable as the amplitude multi-valued of the received signal becomes large. Further, when the pseudo pull-in state occurs, it is necessary to perform the sequential adjustment work in order to make the offset of the DC amplifier 12 appropriate. In addition,
The pseudo pull-in state is a state in which the feedback loop is pseudo stable because the time average of the control signals 23 and 24 becomes 0 in the false pull-in state. As an example, when the input signal is a quaternary amplitude signal, in the pseudo pull-in state, the relationship between the eye pattern waveform and the discrimination level of the analog digital converter 14 is shown in FIG. 2 (offset to the positive side) and FIG. 3 (negative side). There are two states, designated as offset).

<Summary of the Invention> In order to solve the above-mentioned conventional drawbacks, the present invention includes a determination circuit for detecting a pseudo pull-in state, and a switching circuit for switching an offset control signal according to the output of the determination circuit, thereby causing a pseudo pull-in state. The present invention provides a multilevel discriminating circuit capable of promptly returning to the normal pull-in state even in the case of occurrence, and always maintaining an optimum input signal level for performing good multilevel discriminating and reproducing.

According to the present invention, the most significant bit of the input signal or output signal of the analog-digital converter for performing multi-level discrimination is smoothed by the smoothing means, and the smoothed output is the average voltage at the time of normal pull-in and the positive side and the negative side. Whether or not it is between both intermediate values with each average voltage at the time of pseudo pull-in is compared by the comparing means, and by the comparison output, it is offset to either the smoothing output of the most significant bit or the smoothing output of the least significant bit. The control signal is switched by the switching circuit.

<Embodiment> Next, an embodiment of the present invention will be described in detail with reference to the drawings starting from FIG. FIG. 4 shows an embodiment of the present invention.
The 2n-valued multi-level amplitude signal from the signal input terminal 11 is a DC amplifier.
The input signal of the DC amplifier 12 is sampled in the n + 1-bit output analog-to-digital converter 14 in synchronization with the clock signal at the clock input terminal 13 and n +.
It is converted and output as a 1-bit digital signal 15. That n
The + 1-bit digital signal 15 is input to the control circuit 25, and the control circuit 25 controls the offset of the DC amplifier 12 by the combination of the 1-bit output or the multi-bit output of the digital signal 15. And a control signal 18 for controlling the gain. A control signal 24 obtained by smoothing the gain control signal 18 via a low-pass filter 22 is supplied to the DC amplifier 12. The offset control signals 26 and 27 are input to the switching circuit 28, and the determination signal 31 output from the determination circuit 29 selects and outputs the optimum offset control signal 32 according to the pull-in state.

The determination circuit 29 is n + 1 of the analog digital converter 14.
By monitoring a part of the signal 33 of the bit digital signal 15, it is determined whether the normal pull-in state or the pseudo pull-in state, and the decision signal 31 is output. A control signal 23 obtained by smoothing the selected offset control signal 32 through the low pass filter 21 is supplied to the DC amplifier 12. The DC amplifier 12 has its DC voltage offset and gain controlled by control signals 23 and 24.

In this embodiment, as described below, the gain and offset of the DC amplifier 12 are optimally controlled even in the pseudo pull-in state, so that the pseudo pull-in state can be quickly returned to the normal pull-in state. The digital converter 14 can always discriminate at the optimal discrimination level. Therefore, a stable identification function can be realized with a simple circuit configuration even if the number of amplitude multi-values of the input signal increases.

The control circuit 25 and the switching circuit 28 described above can be configured, for example, as shown in FIG. FIG. 5 shows an example of a configuration in which a 3-bit output analog-digital converter 14 is used as a 4-valued multi-level discriminator. In this case, the analog-digital converter 14 equally divides a predetermined input voltage into eight steps and converts it into a 3-bit digital signal. The relationship between the input voltage and the discrimination level is shown in FIG. As shown in FIG.
When the input voltage V _U , V _D is divided into 8 levels from 0 to 7, V _U ,
Let V _{1 be} the voltage that bisects V _D , and V ₂ and V ′ ₂ be the voltages that bisect V _U and V ₁ and V ₁ and V _D , respectively. V ₁ is the most significant bit. The levels V ₂ and V ′ ₂ are the identification levels of the second bit. Normal four-level discrimination is possible by using the output of these two bits, but in this embodiment, the voltage V _{U is used.}
Between ~V _2, between _{V 2 ~V 1, V 1 ~V} ' between _2, V' and the least significant bit output by by connexion discriminate between ₂ ~V _D to the voltage further bisecting each. The relationship between the input signal of 0 to 7 stages and the output signal 15 of 3 bits is as shown in the table below.

The least significant bit output and the most significant bit output thus obtained are input to the exclusive OR circuit 34 in the control circuit 25, and the output is used as the gain control signal 18. The highest bit output and the lowest bit output are set to offset control signals 26 and 2, respectively.
7 is supplied to the switching circuit 28. The judgment circuit 29 is 0 in the normal pull-in state according to the pull-in state, and + in the pseudo pull-in state.
A judgment signal 31 of 1 is output, and the switching circuit 28 opens the gate 35 during normal pull-in, the lowest bit output 27 is opened, and the gate 36 is opened during pseudo pull-in, and the highest bit output 26 is selected, and as the offset control signal 32. Is output.

In the normal pull-in state, that is, when the gate 35 is opened, if the input signal level of the analog-digital converter 14 has a slight positive DC voltage offset, the lowest bit 27 becomes +1 as shown in the above table. Is high. Therefore, the output of the low-pass filter 21 becomes positive, the offset of the DC amplifier 12 is controlled to the negative side, and the input signal level of the converter 14 is optimized. Conversely, if the input signal level has a slight negative offset, the least significant bit 27
The ratio of becoming 1 is high. Therefore, the output of the low-pass filter 21 becomes negative, the offset of the DC amplifier 12 is controlled to the positive side, and the input signal level of the converter 14 is optimized.

When the gate 36 is opened in the pseudo pull-in state, for example, in the pseudo pull-in state in which it is largely offset to the positive side as shown in FIG. 2, the received signal level is higher than the discrimination level V _{1 at a} high rate, and therefore the highest bit is set. 26 has a high ratio of +1.
Therefore, the output of the low-pass filter 21 becomes positive, the offset of the DC amplifier 12 is controlled to the negative side, and the pseudo pull-in state can be quickly returned to the normal pull-in state. Similarly, in the pseudo pull-in state in which the negative side is largely offset as shown in FIG. 3, the most significant bit 26 has a high ratio of -1, so that the output of the low-pass filter 21 becomes negative, and the offset of the DC amplifier 12 is offset. Is controlled to the positive side, and it is possible to quickly return to the normal retracted state.

As the configuration of the above-mentioned determination circuit 29, there are a method of using the mark ratio of the highest bit 33, a method of using the average voltage value of the lowest bit 27, and the like. First, a method of using the mark ratio will be described. When the mark rate of the highest bit 33 of the received signal is close to 0.5, the mark rate of the highest bit is also close to 0.5 in the normal pull-in state. However, in the pseudo pull-in state, the most significant bit is biased to the code of either +1 or -1, so that the mark rate deviates from 0.5. Therefore, as shown in FIG. 7, the mark rate of the highest bit 33 is detected, and the mark rate is
0.5 ± α (α is determined by the multi-valued number of input signals)
It is determined that the area is in the normal pull-in state, and other mark ratios are in the pseudo pull-in state.

The determination circuit 29 using the mark ratio can be configured as shown in FIG. 8, for example. In this case, the highest bit 33 is D
Type flip-flop 37 and is sampled in synchronism with the clock signal at the clock input terminal 13. The Q output digital signal and its output inversion signal are the count up terminal CU and the count down terminal of the pulse counter 38.
Entered on CD. The counter 38 counts the number of pulses input to the count-up terminal and the count-down terminal, and the count value of the counter 38 is added by the number of input pulses of the count-up terminal and subtracted by the number of input pulses of the count-down terminal. When the count value of the counter 38 reaches the preset upper limit value or lower limit value, the counter 38 outputs the carry signal 41 or the carry signal 42. The carry signal 41 and the carry signal 42 are always 1, and become 0 when a carry occurs and when a carry occurs. These carry signal 41, digit signal 4
2 is input to the AND circuit 43, the output signal of the AND circuit 43 is supplied to the T-type flip-flop 44, and its output signal is the judgment signal.
31. In the normal state, the output 31 of the flip-flop 44 is 0, but if the offset of the DC amplifier 12 largely shifts to the positive side (negative side), the ratio of the most significant bit 33 to +1 (-1) increases and the counter 38 Then, a carry signal 41 (carry signal 42) is generated, the flip-flop 44 is inverted, the output 31 becomes 1, and the gate 36 in FIG. 5 is opened.

Note that α for determining the normal pull-in area is the pulse counter
It is determined by the set values of the upper limit value and the lower limit value of 38 count values.

Next, a method of using the average voltage value will be described. The determination circuit 29 in the case of a four-valued input signal can be configured as shown in FIG. 9, for example. That is, the highest-order bit 26 of the analog-digital conversion 14 is branched, smoothed via the low-pass filter 45, and then supplied to the voltage comparators 46 and 47. Each of the comparators 46 and 47 outputs its input signal by (v ₀ + v ₊ )
/ 2, and _{(v 0 + v -) /} 2 becomes the set compared with the voltage value, to the positive in the comparator 46 the input signal is set voltage value, the comparator 47 outputs a +1 respectively if not exceeding the negative side However, if it exceeds, 0 is output. Here, v ₀ , v ₊ , v ₋ are the DC voltage values of the smoothed uppermost bit at the time of normal pull-in and pseudo pull-in, as shown in FIG. v ₀ is the _value during normal pull-in, and v ₊ and v _- are the values during pseudo pull-in (offset to the positive side and negative side, respectively). NAND output of comparators 46 and 47
The signal is supplied to the circuit 48, and the output of the NAND circuit 48 becomes the judgment signal 31. That is, in normal operation, the outputs of both comparators 46 and 47 are 1 and NAN.
The output 31 of the D circuit 48 is 0, and the gate 35 (Fig. 5) is opened.
In the pseudo pull-in state, one output of the comparators 46 and 47 becomes 0, the output of the NAND circuit 48 becomes 1, and the gate 36 is opened.

As is clear from the above description, in the pseudo pull-in state, the level superimposed on the multi-level amplitude modulation signal is high by more than α on the input side of the analog digital (A / D) converter 14.
Or, as a result of lowering by more than α, the probability that the most significant bit B ₁ of the output of the analog digital (A / D) converter 14 is “1” is high, or the probability that it is “0” is high. This was detected to determine whether or not it was in the pseudo pull-in state. Therefore, the multi-level amplitude modulation signal on the input side of the analog digital (A / D) converter 14 is directly branched and supplied to, for example, a judgment circuit 29 having the same configuration as shown in FIG. 9 to generate an average voltage. It is obvious that the pseudo pull-in state may be determined when the average voltage is out of the predetermined range. In this case, it goes without saying that the set voltages of the comparators 46 and 47 and the time constant of the low-pass filter 45 are appropriately changed if necessary.

The decision circuit 29 shown in FIG. 8 can be said to be the decision circuit 29 shown in FIG. 9 configured by a digital circuit. That is, the clock is counted by the counter 38, and the count direction is controlled according to the polarity at that time, that is, by the output of the D-type flip-flop 37, so as to correspond to the output of the low-pass filter 45 in FIG. The digital smoothed output is obtained as the count value of the counter 38, and the counter 38
It is necessary to detect whether the count value of the counter reaches the upper limit value or the lower limit value of the setting by comparing the output of the filter 45 with the comparators 46, 4 in FIG.
This corresponds to the comparison with (V ₀ + V ₊ ) / 2 and (V ₀ + V ₋ ) / 2 in 7 respectively.

<Effects> As described above, according to the present invention, it is possible to realize a multi-valued identification and reproduction function with a fixed circuit deterioration and a simple circuit configuration. Further, even if the pseudo pull-in state occurs, it is possible to quickly recover, so that there is an advantage that a stable identification and reproducing function can be obtained especially when the multi-valued number of the input signal increases.

In order to improve frequency utilization efficiency in the field of digital wireless communication, multilevel modulation / demodulation technology is effective. However, the discrimination margin decreases as the number of amplitude multi-values increases, so that the conventional discriminator is likely to fall into the pseudo pull-in state due to disturbances such as fading. The present invention is particularly effective as a multilevel discriminator in such a multilevel modulation / demodulation system.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional multilevel discriminator, FIG.
FIG. 3 is a diagram showing the relationship between the 4-level eye pattern waveform and the discrimination level in the pseudo pull-in state, FIG. 4 is a block diagram showing an embodiment of the present invention, and FIG. 5 is applied to a 4-level discrimination circuit. FIG. 7 is a diagram showing a configuration example of the control circuit 25 and the switching circuit 28 in the case, FIG. 6 is a diagram showing an input signal discrimination level, and FIG.
FIG. 8 is a diagram showing a mark ratio that gives normal and pseudo pull-in, FIG. 8 is a block diagram showing an embodiment of a judging circuit 29 using the mark ratio, and FIG. 9 is an embodiment of a judging circuit 29 using an average voltage. FIG. 10 is a block diagram showing an example, and FIG. 10 is a diagram showing average voltages that give normal and pseudo pull-in. 11 …… 2n-valued multilevel input signal terminal, 12 …… DC amplifier, 13
...... Clock input terminal, 14 ...... Analog to digital converter, 18 ...... Gain control signal, 23 …… Smoothed offset control signal, 24 …… Smoothed gain control signal, 25 …… Control circuit, 26, 27 ... Offset control signal, 28 ... Switching circuit, 29 ... Judgment circuit, 31 ... Judgment signal, 32 ... Selected offset control signal.

Claims (1)

[Claims] 1. A DC amplifier for amplifying a multivalued amplitude modulation signal of 2n (n is a positive integer of 2 or more) values, and an analog-digital converter for a multivalued 2n value for an output signal of the DC amplifier. In a multi-level discrimination circuit that performs discrimination and automatically controls the offset and gain of the DC amplifier using the output signal of the analog-digital converter, the input signal of the analog-digital converter or the analog-digital converter Whether the smoothing means for smoothing the most significant bit of the output signal and the output of the smoothing means are between the intermediate voltage between the average voltage during normal pull-in and the average voltage during pseudo pull-in on the positive and negative sides. Comparing means for comparing whether or not, and the offset control signal by the output of the comparing means,
A multilevel discriminating circuit comprising: a switching circuit for switching to either the smoothed output of the most significant bit or the smoothed output of the least significant bit of the output of the analog-digital converter.