JPS6352827B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data separation circuit that separates time division multiplexed data signals.

First, a conventional data separation circuit will be described with reference to the drawings.

Referring to FIG. 1, a frame structure of time division multiplexed data, which is an input signal to a data separation circuit, is shown. In Figure 1, A is 64Kb/s multiplexed data, B is 1 frame (20 bits), and C is 64Kb/s multiplexed data.
is a synchronization signal (4 bits/frame), D is 32Kb/
s data (10 bits/frame), E is
12.8Kb/s data (4 bits/frame), F
is 6.4Kb/s data (2 bits/frame). Here, the synchronization signal C is a signal for providing a time reference for time division multiplexing for each frame, and is a fixed pattern of 4 bits in this example.

Referring to FIG. 2, a conventional data separation circuit is shown. As is clear from the frame structure of Figure 1, the circuit in Figure 2 is time-division multiplexed.
This is a data separation circuit that receives 64Kb/s data and separates it into three types of data: 32Kb/s data, 12.8Kb/s data, and 6.4Kb/s data.

The operation of the circuit shown in FIG. 2 will be explained below with reference to FIG. 3 as well.

The 64KHz clock input 228 (○A in Figure 3) is frequency-divided by the clock generation circuit 211, and the frequency is 32KHz.
There are three types of clock pulses: a 12.8 KHz clock 232 (circled in Figure 3), a 12.8 KHz clock 233 (circled in Figure 3), and a 6.4 KHz clock 234 (circled in Figure 3).
Input 64Kb/s time division multiplexed data 227
(○A in FIG. 3) is supplied to shift registers 212-217. At the same time, the 64 Kb/s data input 227 is supplied to the synchronization signal detection circuit 201.
A synchronization signal detection circuit 201 detects a synchronization signal indicating the time reference of a time division multiplexed frame, and supplies a synchronization signal detection pulse 202 (circle C in FIG. 3) to a frame synchronization circuit 203. Frame synchronization circuit 2
03 removes the instability of the synchronization signal detection pulse 202 caused by bit errors in the transmission path, and
A stable frame pulse 204 that defines the time reference for a time division multiplexed frame with a period of frames.
(Fig. 3 ○D) is output. frame counter 20
5 is driven by a 64 KHz clock input 228, preset to state "1" by frame pulse 204, and operates at a period equal to the number of bits in one frame (i.e., 20 bits). The output of the frame counter 205 (○O in Figure 3) is sent to the decoder 2
06 and the switch switching circuit 207. The decoder 206 receives gate signals 229, 23 (i.e., intra-frame multiplexing time position indication signals) indicating multiplexing time positions corresponding to three types of output data.
0,231 (○ki, ○ku, ○ke in Figure 3) is generated. AND circuits 208, 209, and 210 take the AND of the decoder outputs 229, 230, and 231 and the 64KHz clock 228, and generate a burst of 64K.
Generates a Hz clock. The switch switching circuit 207 switches the switches 218 to 22 every frame.
6 is generated (circle circle in Figure 3).
The outputs of the switches 218 to 223 are shown in Figure 3, respectively.

Shift registers 212 and 213 are 32Kb/s
Responsible for data separation. That is, when the switches 218, 219, and 224 are in the state shown in FIG. The shift register 212 writes only the multiplexed time position of 32Kb/s data using the 64KHz clock of
2 is being read. In the next frame, the switch switching circuit 207 switches the switches 218, 219,
224 is switched to the state opposite to that in FIG. 2 (the high-level state indicated by circle in FIG. 3), and the operation of the shift register is reversed, so that the shift register 212 performs a write operation and the shift register 213 performs a read operation. As a result, 32 Kb/s data (circle in FIG. 3) separated from the 64 Kb/s data input 227 is outputted to the output 235 of the switch 224. Similar behavior
This is performed for 12.8 Kb/s data, and the 12.8 Kb/s data separated from the 64 Kb/s data input 227 is output to the output 236 of the switch 225 (see circle in FIG. 3). Furthermore,
Similarly, for the 6.4 Kb/s data, separated 6.4 Kb/s data (circle in FIG. 3) is output to the output 237 of the switch 226.

The data separation circuit shown in Figure 2 requires a pair (two) of shift registers for each output data and uses a large number of switch circuits, so the number of integrated circuit chips used is large. There are disadvantages, and when changing the frame configuration, there is the inconvenience of having to change the circuit configuration of the decoder that determines the time position on the frame.

An object of the present invention is to eliminate the above drawbacks and provide a highly versatile data separation circuit with a simple circuit configuration.

According to the present invention, a first-in first-out memory (hereinafter abbreviated as FIFO) is used instead of a pair of shift registers corresponding to each output data in the conventional circuit. In order to simplify the process, a read-only memory (hereinafter referred to as ROM) is used in place of the decoder in the conventional circuit.
A highly versatile data separation circuit with a simple circuit configuration that can be easily handled by changing data can be obtained.

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 4, the data separation circuit according to one embodiment of the present invention is similar to the circuit of FIG.
This realizes the frame structure shown in the figure.

The operation of the circuit shown in FIG. 4 will be explained below with reference to FIG. 5 as well.

The clock generation circuit 408 receives a 64 KHz clock input 418 (Fig. 5), a 32 KHz clock 421 (Fig. 5), a 12.8 KHz clock 420 (Fig. 5),
A 6.4KHz clock 419 (Figure 5) is generated. 64Kb/s data input 417 (Figure 5)
are input as data inputs of FIFOs 409, 410, and 411. At the same time, the 64 Kb/s data input 417 is also input to the synchronization signal detection circuit 401. Here, a synchronization signal indicating the time reference of the time division multiplexed frame is detected, and a synchronization signal detection pulse 415 (FIG. 5) is supplied to the frame synchronization circuit 402. Frame synchronization circuit 402
eliminates the instability of the synchronization signal detection pulse 415 caused by bit errors in the transmission path, and creates a stable frame pulse 416 (the fifth
Figure) is output. The frame counter 403 is
Driven by a 64KHz clock input 418 and preset to state "1" by a frame pulse 416, the number of bits in one frame (i.e. 20 bits)
It operates at the same cycle. The output of frame counter 403 (FIG. 5) is supplied to the address input of ROM 407. The storage capacity of the ROM 407 is composed of 20 words and 3 bits.
The output 412 (Figure 5) of the ROM 407 is 32Kb/
This is a pattern indicating the temporal position on the frame of the data of s (ie, an intra-frame multiplexed time position indication signal). Similarly, the output 413 of the ROM 407 (fifth
Figure) is a pattern indicating the time position on a frame of 12.8 Kb/s data (i.e., an intra-frame multiplexed time position indication signal), and the output 4 of the ROM 407
14 (FIG. 5) is a pattern indicating the temporal position on the frame of 6.4 Kb/s data (ie, an intra-frame multiplexing time position indicating signal). Nando circuit 4
04, 405, 406 are output 4 of ROM407
12,413,414 and 64KHz clock 418
Take the negative logical AND with. The output of the NAND circuit 404 (Fig. 5) is connected to the write clock input of the FIFO 409, and the output of the NAND circuit 404 is connected to the write clock input of the FIFO 409, and the 64Kb/
Only the 32 Kb/s data portion of the s data input 417 is written. In addition, the NAND circuit 40
The output of 5 (FIG. 5) is connected to the write clock input of FIFO 410 and is one of the 64 Kb/s data inputs 417 multiplexed into FIFO 410.
Only the 12.8 Kb/s data portion is written.
Similarly, the output of the NAND circuit 406 (Fig. 5)
is connected to the write clock input of FIFO411,
Of the 64 Kb/s data input 417 multiplexed into the FIFO 411, only the 6.4 Kb/s data portion is written.

The 32KHz clock output 421 (FIG. 5) of the clock generation circuit 408 is supplied to the read clock input of the FIFO 409, and the 32KHz clock output 421 (FIG. 5) is supplied to the read clock input of the FIFO 409.
s data is read out, and separated 32 Kb/s data 422 (FIG. 5) is output from the FIFO 409. Also, 12.8K of the clock generation circuit 408
The Hz clock output 420 (Figure 5) is a FIFO
410 read clock input and FIFO4
10, 12.8Kb/s data is read out and separated 12.8Kb/s data 423 (Figure 5)
is output from the FIFO 410. Similarly, the 6.4KHz clock output 419 of the clock generation circuit 408
(Fig. 5) is supplied to the read clock input of FIFO 411, 6.4 Kb/s data is read out from FIFO 411, and 6.4 Kb/s data 4 is separated.
24 (FIG. 5) is output from the FIFO 411.

The above embodiment is a data separation circuit for three data outputs, but generally N FIFOs and NAND circuits are used corresponding to N data outputs, and the ROM capacity is reduced to at least (the number of bits in a frame). ×N) bits, and by changing the number of output clocks of the clock generation circuit to a number corresponding to the type of clock speed of the required output data, it can be generalized.

The effects of the present invention will be explained below.

Conventionally, two shift registers (generally twice the number of storage elements) were required for one output data in order to separate data, but in the present invention, one FIFO is used instead of two shift registers. Therefore, separation is possible, and along with this, 2
This eliminates the need for a related circuit for switching between two shift registers (memory elements), making it possible to simplify the circuit and reduce the number of integrated circuit chips used.

Furthermore, in the past, a decoder configured using wired logic was used to determine the data multiplexing time position on a frame, but in the present invention, the decoder is
By replacing it with , it became possible to reduce the number of integrated circuit chips. In addition, it is possible to change the number of output data, change the clock speed of output data, and select centralized or distributed arrangement of data within a frame, which was conventionally done by changing the wiring logic of the decoder. According to the present invention, the frame configuration can be changed easily and quickly by changing the data contents of the ROM.

According to the present invention, the simplification of logic circuits using logic integrated circuits and the reduction in the number of chips of integrated circuits used are as follows:
Smaller equipment, lower power consumption, reduced inspection man-hours,
This greatly contributes to cost reduction.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a time division multiplexed frame structure. FIG. 2 is a block diagram of a conventional data separation circuit for realizing the frame configuration of FIG. 1. In FIG. 2, 201 is a synchronization signal detection circuit, 203 is a frame synchronization circuit, 205 is a frame counter, 206 is a decoder, 207 is a switch switching circuit, 208 to 210 are AND circuits, 21
1 is a clock generation circuit, 212 to 217 are shift registers, and 218 to 226 are changeover switches. Figure 3 is a timing diagram showing the waveforms of each part in Figure 2.
There is a one-to-one correspondence with the figure. FIG. 4 is a block diagram of a data separation circuit according to an embodiment of the present invention. In FIG. 4, 401 is a synchronization signal detection circuit, 402 is a frame synchronization circuit, 403 is a frame counter, 404 to 406 are NAND circuits, and 40
7 is a ROM, 408 is a clock generation circuit, 409
~411 is FIFO. Figure 5 is a timing diagram showing waveforms at each part in Figure 4.
There is a one-to-one correspondence with the figure.

Claims (1)

[Claims] 1. In a data separation circuit that separates a plurality of data signals from an input signal including a time division multiplexed data signal, a synchronization signal detection circuit that detects a synchronization signal that is a time reference for time division multiplexing from the input signal; a frame synchronization circuit that receives the output signal of the detection circuit and generates a frame pulse having a period of at least one frame; and a frame synchronization circuit whose counting is controlled by the frame pulse and is driven by a first clock pulse having a clock speed of the input signal; a frame counter having a period equal to the number of bits of at least one frame; an address input terminal connected to the output terminal of the frame counter; and a plurality of intra-frame multiplexed time position indicating signals corresponding to the plurality of data signals stored therein. a read-only memory, a clock generation circuit that generates a plurality of second clock pulses corresponding to the clock speed of the plurality of data signals from the first clock pulse, and a plurality of clock generation circuits provided corresponding to the plurality of data signals. , receives said input signal at a data input terminal and receives at a write clock input terminal a gated signal of said first clock pulse with a corresponding intra-frame multiplexed time position indication signal from said read-only memory; The first-in first clock receives the second clock pulse at the readout clock input terminal.
out memory, and the plurality of first
A data separation circuit characterized in that the plurality of data signals are separated and outputted to an output terminal of an in-first-out memory.