JPS6355223B2 - - Google Patents
Info
- Publication number
- JPS6355223B2 JPS6355223B2 JP55147830A JP14783080A JPS6355223B2 JP S6355223 B2 JPS6355223 B2 JP S6355223B2 JP 55147830 A JP55147830 A JP 55147830A JP 14783080 A JP14783080 A JP 14783080A JP S6355223 B2 JPS6355223 B2 JP S6355223B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- collector
- conductivity type
- base
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/108—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having localised breakdown regions, e.g. built-in avalanching regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、バイポーラトランジスタのコレクタ
に印加される過電圧にもとずくコレクタ・ベース
間の接合破壊を防止するために、同一島内にリー
チスルータイプの保護領域を設けた半導体装置の
構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a bipolar transistor in which a reach-through type protection area is provided within the same island in order to prevent collector-base junction breakdown due to overvoltage applied to the collector of a bipolar transistor. It concerns the structure of the device.
第１図は、従来の一般的なバイポーラトランジ
スタの断面図である。１はＰ型の半導体基板で、
その上に形成されたＮ型のエピタキシヤル成長層
である半導体層２に、P+型の分離領域３を形成
している。そして、その分離領域３により囲まれ
た半導体層２をコレクタ領域としている。このコ
レクタ領域２内には図に示すように、P+型ベー
ス領域４、N+型エミツタ領域５、N+型コレクタ
コンタクト領域６、N+型コレクタ埋込領域６ａ
が形成されている。７は絶縁膜、Ｃ，Ｂ，Ｅはそ
れぞれコレクタ、ベース、エミツタ電極である。 FIG. 1 is a cross-sectional view of a conventional general bipolar transistor. 1 is a P-type semiconductor substrate,
A P + type isolation region 3 is formed in a semiconductor layer 2 which is an N type epitaxial growth layer formed thereon. The semiconductor layer 2 surrounded by the isolation region 3 is used as a collector region. As shown in the figure, this collector region 2 includes a P + type base region 4, an N + type emitter region 5, an N + type collector contact region 6, and an N + type collector buried region 6a.
is formed. 7 is an insulating film, and C, B, and E are collector, base, and emitter electrodes, respectively.
ところで、このようなバイポーラトランジスタ
の破壊現象として、コレクタ・ベース間の接合破
壊がある。つまり、コレクタ電極Ｃに正の過電圧
が印加されると、コレクタ・ベース間のＮ−Ｐ接
合部に逆バイアスが印加された状態になる。する
とその接合部に空乏層８が広がる（図中斜線部）。
そして、特にベース領域４の周辺部では８ａに示
すように局部に電界が集中し、その部分からコレ
クタ電流のリークが生じ局部的なブレークダウン
が生じる。その時８ａの部分では局部的な発熱に
より接合破壊が生じるわけである。 By the way, as a breakdown phenomenon of such a bipolar transistor, there is junction breakdown between collector and base. That is, when a positive overvoltage is applied to the collector electrode C, a reverse bias is applied to the N-P junction between the collector and the base. Then, a depletion layer 8 spreads at the junction (shaded area in the figure).
Particularly in the periphery of the base region 4, as shown at 8a, the electric field is locally concentrated, and the collector current leaks from that part, causing local breakdown. At that time, bonding failure occurs in the portion 8a due to local heat generation.
そこで従来、そのような接合破壊の保護手段と
して、コレクタ端子に保護用のダイオード等より
なる保護回路を別途設けたりする方法があつた。
しかしながら、そのような保護回路を別に設ける
事は高集積化等を考慮すると、あまり賢明な手段
とはいえない。 Conventionally, as a means of protecting against such junction breakdown, there has been a method of separately providing a protection circuit consisting of a protection diode or the like to the collector terminal.
However, providing such a separate protection circuit is not a very wise measure in consideration of high integration.
そこで本発明は、別に保護回路を設けることな
く、トランジスタの同一島内に形成できる保護機
能を有する簡単な構造の提供にあり、本発明は一
導電型の半導体基板上に設けられた反対導電型の
半導体層、該半導体層表面から該半導体基板に達
する一導電型の分離領域、該分離領域に囲まれた
半導体層であるコレクタ領域、該コレクタ領域内
に設けられた一導電型のベース領域、該ベース領
域内に設けられた反対導電型のエミツタ領域、該
コレクタ領域に導通するコレクタ電極を有する半
導体装置において、該分離領域の基板側部分にコ
レクタ領域内に向けて延在する延在部が設けら
れ、該コレクタ電極の一部に接続され、かつ該分
離領域の延在部に向けて延在する一導電型の破壊
保護領域が該コレクタ領域内に設けられてなり、
該コレクタ電極に過剰電圧が印加されたときコレ
クタ・ベース間の接合破壊電圧より低い電圧で該
分離領域の延在部の上部縁部と該破壊保護領域の
下部縁部間がパンチスルーするようにしたことを
特徴とする半導体装置を提供することによつて達
成される。 Therefore, the present invention provides a simple structure having a protection function that can be formed within the same island of transistors without providing a separate protection circuit. a semiconductor layer, an isolation region of one conductivity type reaching the semiconductor substrate from the surface of the semiconductor layer, a collector region that is a semiconductor layer surrounded by the isolation region, a base region of one conductivity type provided within the collector region; In a semiconductor device having an emitter region of opposite conductivity type provided in a base region and a collector electrode electrically connected to the collector region, an extension portion extending toward the collector region is provided in a substrate side portion of the separation region. a breakdown protection region of one conductivity type, connected to a part of the collector electrode and extending toward an extension of the separation region, is provided in the collector region;
When an excessive voltage is applied to the collector electrode, punch-through occurs between the upper edge of the extended portion of the separation region and the lower edge of the breakdown protection region at a voltage lower than the collector-base junction breakdown voltage. This is achieved by providing a semiconductor device characterized by the following.
以下本発明の一実施例を図面に従つて詳細に説
明する。 An embodiment of the present invention will be described in detail below with reference to the drawings.
第２図は本発明に係るバイポーラトランジスタ
の断面図である。図面の各部に付した番号は、第
１のそれと一致する。このトランジスタが第１図
の従来例と異なる点は、コレクタ電極Ｃの一部に
接続され、P+型分離領域３ａ側に延在するよう
設けられたP+型破壊保護領域１０である。 FIG. 2 is a sectional view of a bipolar transistor according to the present invention. The numbers assigned to each part of the drawing correspond to the first one. This transistor differs from the conventional example shown in FIG. 1 in that a P + -type breakdown protection region 10 is connected to a part of the collector electrode C and is provided to extend toward the P + -type isolation region 3a.
この様なP+型の破壊保護領域１０を設けるこ
とにより、領域１０と３ａとの間のＮ型領域が狭
くなり、コレクタ電極Ｃに過剰電圧が印加される
と図のの如くパンチスルー現象が生じ、基板１
よりGNDに放電される。このパンチスルー現象
は、図中１１の斜線部に示すような空乏層１１が
広がり破壊保護領域１０と分離領域３ａとがＮ型
の半導体層２を介さずに直接導通してしまうもの
である。そして、領域１０と３ａとの間の距離が
パンチスルー電圧を決めるものであるから、この
パンチスルー電圧がコレクタ・ベース間の接合破
壊電圧以下になるようにしている。 By providing such a P + type breakdown protection region 10, the N type region between the regions 10 and 3a becomes narrower, and when excessive voltage is applied to the collector electrode C, a punch-through phenomenon occurs as shown in the figure. generated, substrate 1
is discharged to GND. This punch-through phenomenon occurs when the depletion layer 11 as shown in the shaded area 11 in the figure expands and the breakdown protection region 10 and the isolation region 3a are directly electrically connected without the N-type semiconductor layer 2 interposed therebetween. Since the distance between regions 10 and 3a determines the punch-through voltage, the punch-through voltage is set to be equal to or lower than the collector-base junction breakdown voltage.
第３図は本発明の一実施例であるトランジスタ
の断面図である。本実施例では、P+型の破壊保
護領域１０の他に、分離領域３に導通するP+型
領域３ｂを領域１０と角の部分で対向するよう設
けている。そして、パンチスルー電流は図中の
様に流れる。 FIG. 3 is a sectional view of a transistor that is an embodiment of the present invention. In this embodiment, in addition to the P + -type breakdown protection region 10 , a P + -type region 3 b electrically connected to the isolation region 3 is provided so as to face the region 10 at a corner portion. Then, the punch-through current flows as shown in the figure.
この実施例によれば、領域１０と３ｂとを角の
部分で対向せしめているので、その間の距離を短
かくすることができ、パンチスルー電圧を下げる
ことができる。 According to this embodiment, since the regions 10 and 3b are opposed to each other at the corners, the distance therebetween can be shortened, and the punch-through voltage can be lowered.
以上説明した様に本発明によれば、トランジス
タと同一島内に単に破壊保護領域１０を設けるだ
けで、コレクタ・ベース接合部の接合破壊を防止
することができる。そして、２つの実施例での
P+破壊保護領域は、トランジスタのベース拡散
工程や、分離領域３の上側拡散工程等と同一工程
で形成することができるので、極めて実用的であ
る。 As described above, according to the present invention, junction breakdown at the collector-base junction can be prevented by simply providing the breakdown protection region 10 within the same island as the transistor. And in two examples
The P + breakdown protection region can be formed in the same process as the transistor base diffusion process, the upper side diffusion process of the isolation region 3, etc., and is therefore extremely practical.
第１図は従来のトランジスタの断面図、第２図
は本発明に係るトランジスタの断面図、第３図は
本発明のトランジスタの一実施例を示す断面図で
ある。
図中、１……半導体基板、２……半導体層及び
コレクタ領域、３……分離領域、４……ベース領
域、５……エミツタ領域、１０……破壊保護領
域、Ｃ……コレクタ電極、Ｂ……ベース電極、Ｅ
……エミツタ電極。
FIG. 1 is a sectional view of a conventional transistor, FIG. 2 is a sectional view of a transistor according to the present invention, and FIG. 3 is a sectional view showing an embodiment of the transistor of the present invention. In the figure, 1...Semiconductor substrate, 2...Semiconductor layer and collector region, 3...Isolation region, 4...Base region, 5...Emitter region, 10...Destruction protection region, C...Collector electrode, B ...Base electrode, E
...Emitsuta electrode.
Claims (1)
電型の半導体層、該半導体層表面から該半導体基
板に達する一導電型の分離領域、該分離領域に囲
まれた半導体層であるコレクタ領域、該コレクタ
領域内に設けられた一導電型のベース領域、該ベ
ース領域内に設けられた反対導電型のエミツタ領
域、該コレクタ領域に導通するコレクタ電極を有
する半導体装置において、 該分離領域の基板側部分にコレクタ領域内に向
けて延在する延在部が設けられ、 該コレクタ電極の一部に接続され、かつ該分離
領域の延在部に向けて延在する一導電型の破壊保
護領域が該コレクタ領域内に設けられてなり、 該コレクタ電極に過剰電圧が印加されたときコ
レクタ・ベース間の接合破壊電圧より低い電圧で
該分離領域の延在部の上部縁部と該破壊保護領域
の下部縁部間がパンチスルーするようにしたこと
を特徴とする半導体装置。[Claims] 1. A semiconductor layer of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, an isolation region of one conductivity type reaching the semiconductor substrate from the surface of the semiconductor layer, and a semiconductor surrounded by the isolation region. In a semiconductor device having a collector region which is a layer, a base region of one conductivity type provided in the collector region, an emitter region of an opposite conductivity type provided in the base region, and a collector electrode electrically connected to the collector region, An extension portion extending toward the collector region is provided in the substrate side portion of the separation region, and a conductive conductor connected to a part of the collector electrode and extending toward the extension portion of the separation region. A breakdown protection region of the type is provided in the collector region, the upper edge of the extension of the separation region being at a voltage lower than the collector-base junction breakdown voltage when an excessive voltage is applied to the collector electrode. A semiconductor device characterized in that there is a punch-through between the lower edge of the destruction protection region and the lower edge of the destruction protection region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55147830A JPS5771176A (en) | 1980-10-22 | 1980-10-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55147830A JPS5771176A (en) | 1980-10-22 | 1980-10-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5771176A JPS5771176A (en) | 1982-05-01 |
| JPS6355223B2 true JPS6355223B2 (en) | 1988-11-01 |
Family
ID=15439198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55147830A Granted JPS5771176A (en) | 1980-10-22 | 1980-10-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5771176A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5013076A (en) * | 1973-06-04 | 1975-02-10 |
-
1980
- 1980-10-22 JP JP55147830A patent/JPS5771176A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5771176A (en) | 1982-05-01 |
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