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JPS6355229B2 - - Google Patents
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JPS6355229B2 - - Google Patents

Info

Publication number
JPS6355229B2
JPS6355229B2 JP15249083A JP15249083A JPS6355229B2 JP S6355229 B2 JPS6355229 B2 JP S6355229B2 JP 15249083 A JP15249083 A JP 15249083A JP 15249083 A JP15249083 A JP 15249083A JP S6355229 B2 JPS6355229 B2 JP S6355229B2
Authority
JP
Japan
Prior art keywords
recess
laser
electronic circuit
layer
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15249083A
Other languages
Japanese (ja)
Other versions
JPS6045083A (en
Inventor
Hideaki Matsueda
Takashi Kajimura
Naoki Kayane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP15249083A priority Critical patent/JPS6045083A/en
Publication of JPS6045083A publication Critical patent/JPS6045083A/en
Publication of JPS6355229B2 publication Critical patent/JPS6355229B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/32Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/026Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Description

【発明の詳細な説明】 〔発明の利用分野〕 半導体レーザと、増幅、変調、安定化、スイツ
チング等の機能を持つ電子回路とをモノリシツク
に形成した平面型半導体集積回路装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a planar semiconductor integrated circuit device in which a semiconductor laser and an electronic circuit having functions such as amplification, modulation, stabilization, and switching are monolithically formed.

〔発明の背景〕[Background of the invention]

半導体レーザと電子回路とをモノリシツクに作
り付ける場合、n型基板を用いた2階建構造にす
る方法(H.Matsueda:Japan J.A.P.20(’81)
S20−1p.193)と半絶縁性(SI)基板を用いる方
法(A.Yariv:IE3 Spectrum、May(’82)
p.38)とが提案されている。集積度を上げるため
には、後者の方が大面積が利用出来る等の理由か
ら有利である。しかし従来、素子表面に段差を生
じるため実現が困難であつた。
When fabricating a semiconductor laser and an electronic circuit monolithically, a two-story structure using an n-type substrate (H.Matsueda: Japan JAP20 ('81))
S20-1p.193) and the method using semi-insulating (SI) substrates (A. Yariv: IE 3 Spectrum, May ('82)
p.38) is proposed. In order to increase the degree of integration, the latter is more advantageous because a larger area can be used. However, conventionally, this has been difficult to realize because it creates a step difference on the element surface.

〔発明の目的〕[Purpose of the invention]

半導体レーザダイオードと電子回路とを平面的
に、段差を生じる事なく、同一基板上に形成した
平面型半導体レーザ集積回路装置に関する。電子
回路部には、変調、増幅、安定化、スイツチング
等の機能を持たせ、半導体レーザの多機能化を実
現する。
The present invention relates to a planar semiconductor laser integrated circuit device in which a semiconductor laser diode and an electronic circuit are formed on the same substrate without forming a step. The electronic circuit section has functions such as modulation, amplification, stabilization, and switching, making the semiconductor laser multifunctional.

〔発明の概要〕[Summary of the invention]

半絶縁性の基板にあらかじめ段付きの凹みを形
成しておき、選択的エピタキシヤル結晶成長技術
によつて、この凹みの中に、ちようど納まるよう
に、導電性の半導体層及びダブルヘテロ構造の半
導体レーザとを作り付ける。特にMOCVD法
(Metalorganic Chemical Vapour Deposition)
による結晶成長が好都合である。しかる後に、凹
み以外の部分の新鮮な半絶縁性基板表面に、電子
回路を形成し、全体として、段差のない平面的な
光・電子集積回路となす。
A stepped recess is previously formed in a semi-insulating substrate, and a conductive semiconductor layer and a double heterostructure are deposited in the recess using selective epitaxial crystal growth techniques. Built-in semiconductor laser. Especially MOCVD method (Metalorganic Chemical Vapor Deposition)
crystal growth is advantageous. Thereafter, electronic circuits are formed on the surface of the fresh semi-insulating substrate in areas other than the recesses, and the whole becomes a planar opto-electronic integrated circuit with no steps.

〔発明の実施例〕[Embodiments of the invention]

半絶縁性のGaAs基板1にCVDあるいはスパツ
タ法によつて形成したSiO2、SiN4、PSG(リンガ
ラス)、あるいはAl2O3等の厚さ1000Å〜5000Å
の膜をマスク3として用いて、第1図1に示すよ
うに幅の広い凹みをエツチングによつて形成す
る。この部分の深さは0.5μm〜3μmである。次
に、上述のマスクをつけた状態でMOCVD法に
よつて、第1図2に示すように凹み部分をSe(或
いはTe、Sn等でも良い)をドープしたn+型の導
電性GaAs2でちようど埋め込む。この埋込みは
他に、LPE(液相エピタキシヤル結晶成長)法、
MBE(分子線エピタキシヤル)法等による事も可
能である。このn+導電層2のキヤリア濃度は高
い程、直列抵抗が下がるので良いが、1019cm-3
桁にあれば実用になる。次に第1図3に示すよう
に、凹み部の一部分に、より深い凹み15をエツ
チングで形成する。深さは、2μm〜10μmである。
しかる後に再び選択成長の技術によつて第1図4
に示す如く深い方の凹み中にちようど納まるよう
に、ダブルヘテロ構造のレーザ素子を作り付け
る。ダブルヘテロ構造の構成そのものは通常の半
導体レーザにおけるそれと同様で良い。すなわち
Seをドープしたキヤリヤ濃度1×1018cm-3のn型
Ga0.6Al0.4Asで厚さ0.5μm〜2.0μmのクラツド層
4、キヤリヤ濃度1016cm-3のGa0.96Al0.04Asで厚さ
0.1μmの活性層5、Znをドープしたキヤリヤ濃度
3〜5×1017cm-3のP型Ga0.72Al0.28Asで厚さ
0.5μm〜2.0μmのクラツド層6、及びキヤリヤ濃
度1×1017cm-3のP型GaAsで厚さ0.1μm〜1.0μm
のキヤツプ層7である。
A layer of SiO 2 , SiN 4 , PSG (phosphorus glass), Al 2 O 3 , etc. with a thickness of 1000 Å to 5000 Å formed on a semi-insulating GaAs substrate 1 by CVD or sputtering.
Using the film as a mask 3, a wide recess is formed by etching as shown in FIG. The depth of this part is 0.5 μm to 3 μm. Next, using the MOCVD method with the above-mentioned mask attached, the recessed portions are made of n + type conductive GaAs2 doped with Se (or Te, Sn, etc.) as shown in Figure 1. Please embed it. This embedding can be done using LPE (liquid phase epitaxial growth) method,
It is also possible to use the MBE (molecular beam epitaxial) method. The higher the carrier concentration of this n + conductive layer 2, the better because the series resistance will be lower, but it is practical if it is on the order of 10 19 cm -3 . Next, as shown in FIG. 1, a deeper recess 15 is formed in a portion of the recess by etching. The depth is 2 μm to 10 μm.
After that, by using the selective growth technique again, Fig. 1 4
As shown in the figure, a double heterostructure laser element is built so that it fits exactly into the deeper recess. The structure of the double heterostructure itself may be similar to that of a normal semiconductor laser. i.e.
n-type with Se-doped carrier concentration 1×10 18 cm -3
Cladding layer 4 with a thickness of 0.5 μm to 2.0 μm of Ga 0.6 Al 0.4 As and a thickness of Ga 0.96 Al 0.04 As with a carrier concentration of 10 16 cm -3
Active layer 5 of 0.1 μm, P-type Ga 0.72 Al 0.28 As with carrier concentration 3-5×10 17 cm -3 doped with Zn.
A cladding layer 6 of 0.5 μm to 2.0 μm and a P-type GaAs with a carrier concentration of 1×10 17 cm −3 and a thickness of 0.1 μm to 1.0 μm.
This is the cap layer 7 of.

次にレーザのP側電流経路を形成するため、第
1図5に示すように、Znを拡散し不純物領域8
を形成する。その深さは深い凹部と浅い凹部の境
界から、深い凹部の方へ2μm〜5.0μm寄つた所が
好適である。また、深い凹部の両端でレーザ各層
が近接し混ざり合う部分には、第1図5に9で示
すように、プロトンあるいは酸素をイオン打込み
する事によつて、電流リークを阻止する事が望ま
しい。
Next, in order to form the P-side current path of the laser, Zn is diffused into the impurity region 8 as shown in FIG.
form. The depth is preferably 2 μm to 5.0 μm closer to the deep recess from the boundary between the deep recess and the shallow recess. Further, it is desirable to prevent current leakage by implanting protons or oxygen ions into the portions where the laser layers come close to each other and mix at both ends of the deep recess, as shown at 9 in FIG. 1.

しかる後に、凹部以外の新鮮な半絶縁性基板表
面に、周知の方法で電子回路を形成する。先ず、
Siのイオン打込によつて、オーミツク電極層11
を作り、さらに、能動層10を作る。電子回路部
のオーミツク電極13は、先ず、AuGeNi/Au
積層膜を蒸着しリフトオフした後、400℃で3分
間アロイングする事によつて形成した。シヨトキ
イ電極14及びレーザのP側電極12は、Ti/
Pt/Au積層膜を蒸着し、リフトオフする事で形
成した。また電子回路内や電子回路部とレーザ部
分との接線・配線はMo/Au積層膜を蒸着し、イ
オンミリングによつてパターンを形成する方法に
よつた。
Thereafter, an electronic circuit is formed on the surface of the fresh semi-insulating substrate other than the recessed portions by a well-known method. First of all,
By implanting Si ions, the ohmic electrode layer 11
, and further, an active layer 10 is formed. The ohmic electrode 13 of the electronic circuit section is first made of AuGeNi/Au.
After the laminated film was deposited and lifted off, it was formed by alloying at 400°C for 3 minutes. The shot key electrode 14 and the P-side electrode 12 of the laser are Ti/
It was formed by depositing a Pt/Au laminated film and lifting it off. In addition, for the tangent lines and wiring inside the electronic circuit and between the electronic circuit section and the laser section, a Mo/Au laminated film was deposited and a pattern was formed by ion milling.

第2図は他の実施例である。半絶縁性半導体基
板に最初から段付きの凹部16,17を設けてお
く(第2図1)。この凹部に前例と同様にn+導電
層2を形成する(第2図2)。次いでこのn+導電
層を第2図3に示すように、深い方の凹み内に一
部分残す。この量は即ち、第2図5に15で示し
た導電層の厚さであり、30μm以下で薄い方が直
列抵抗の低減のためには望ましい。他は全く第1
の実施例と同じである。即ち、第2図4は凹部内
にダブルヘテロ構造を積層した状態、第2図5は
電子回路を製造し配線を施こした状態を示す図で
ある。第2図において第1図と同一符号は同一部
位を示す。
FIG. 2 shows another embodiment. Stepped recesses 16 and 17 are provided in the semi-insulating semiconductor substrate from the beginning (FIG. 2, 1). An n + conductive layer 2 is formed in this recess in the same manner as in the previous example (FIG. 2). A portion of this n + conductive layer is then left in the deeper recess, as shown in FIG. This amount is the thickness of the conductive layer shown at 15 in FIG. 2, and a thinner layer of 30 μm or less is desirable for reducing series resistance. Everything else is first
This is the same as the embodiment. That is, FIG. 2 shows a state in which double heterostructures are stacked in the recess, and FIG. 2 shows a state in which an electronic circuit has been manufactured and wiring has been performed. In FIG. 2, the same symbols as in FIG. 1 indicate the same parts.

いずれの実施例においても、他の半導体材料た
とえばInP/InGaAsP等を用いて同様の構造を作
る事も出来た。
In any of the examples, similar structures could be made using other semiconductor materials such as InP/InGaAsP.

〔発明の効果〕〔Effect of the invention〕

(1) 半絶縁性基板上に、段差を作らずに、ダブル
ヘテロ構造のレーザ素子を、微細パターンを有
する電子回路と共に作り付ける事が出来た。
(1) It was possible to fabricate a double-heterostructured laser element together with an electronic circuit having a fine pattern on a semi-insulating substrate without creating a step.

(2) レーザと駆動回路とを含め、一体化する事に
よつて、2GHz以上の高速動作が実現した。
(2) High-speed operation of 2GHz or higher was achieved by integrating the laser and drive circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は本発明による平面型半導体
レーザ集積回路装置の製造プロセスを示す断面図
である。 1:半絶縁性(SI)基板、2:n+型導電層、
3:選択成長のためのマスク、4:レーザn側ク
ラツド層(GaAlAs)、5:レーザ活性層
(GaAlAs)、6:レーザP側クラツド層
(GaAlAs)、7:レーザキヤツプ層(GaAs)、
8:レーザP側拡散領域、9:電流リーク阻止用
のイオン打込み領域、10:電子回路部における
能動層、11:電子回路部及びレーザn側電極部
のオーミツク電極層、12:レーザp側金属電
極、13:レーザn側金属電極及び電子回路オー
ミツク金属電極、14:電子回路部シヨツトキイ
金属電極。
1 and 2 are cross-sectional views showing the manufacturing process of a planar semiconductor laser integrated circuit device according to the present invention. 1: Semi-insulating (SI) substrate, 2: n + type conductive layer,
3: Mask for selective growth, 4: Laser n-side cladding layer (GaAlAs), 5: Laser active layer (GaAlAs), 6: Laser P-side cladding layer (GaAlAs), 7: Laser cap layer (GaAs),
8: Laser P-side diffusion region, 9: Ion implantation region for current leak prevention, 10: Active layer in electronic circuit section, 11: Ohmic electrode layer of electronic circuit section and laser n-side electrode section, 12: Laser p-side metal Electrode, 13: Laser n-side metal electrode and electronic circuit ohmic metal electrode, 14: Electronic circuit section shot key metal electrode.

Claims (1)

【特許請求の範囲】 1 半絶縁性半導体基板に浅い第1の凹部と深い
第2の凹部を有し、前記浅い第1の凹部には導電
性半導体層が埋設され、前記深い第2の凹部内に
は活性層をクラツド層ではさんだ形態のダブルヘ
テロ構造を形成し、前記半絶縁性半導体基板のレ
ーザを構成した部分以外の領域に電子回路を有
し、且前記第1の凹部内に形成された導電性半導
体層を介して前記レーザ部と電子回路部が接続さ
れて成ることを特徴とする平面型半導体レーザ集
積回路装置。 2 前記第2の凹部内の前記第1の凹部に接する
壁面にも前記導電性半導体層を有することを特徴
とする特許請求の範囲第1項記載の平面型半導体
レーザ集積回路装置。
[Scope of Claims] 1. A semi-insulating semiconductor substrate has a shallow first recess and a deep second recess, a conductive semiconductor layer is buried in the shallow first recess, and a conductive semiconductor layer is embedded in the deep second recess. A double heterostructure is formed in which an active layer is sandwiched between cladding layers, and an electronic circuit is formed in a region other than a portion of the semi-insulating semiconductor substrate that constitutes a laser, and is formed in the first recess. A planar semiconductor laser integrated circuit device, characterized in that the laser section and the electronic circuit section are connected through a conductive semiconductor layer. 2. The planar semiconductor laser integrated circuit device according to claim 1, wherein the conductive semiconductor layer is also provided on a wall surface of the second recess that is in contact with the first recess.
JP15249083A 1983-08-23 1983-08-23 Planar type semiconductor laser integrated circuit device Granted JPS6045083A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15249083A JPS6045083A (en) 1983-08-23 1983-08-23 Planar type semiconductor laser integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15249083A JPS6045083A (en) 1983-08-23 1983-08-23 Planar type semiconductor laser integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6045083A JPS6045083A (en) 1985-03-11
JPS6355229B2 true JPS6355229B2 (en) 1988-11-01

Family

ID=15541608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15249083A Granted JPS6045083A (en) 1983-08-23 1983-08-23 Planar type semiconductor laser integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6045083A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61270886A (en) * 1985-05-25 1986-12-01 Mitsubishi Electric Corp Semiconductor laser device

Also Published As

Publication number Publication date
JPS6045083A (en) 1985-03-11

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