JPS6355252B2 - - Google Patents

Description

Detailed Description of the Invention The present invention relates to a phase synchronized circuit using a digital circuit, and more specifically, a phase synchronized circuit that requires a particularly high signal-to-noise ratio, such as a clock synchronization circuit in a digital signal transmission line, a carrier phase synchronization circuit, etc. This invention relates to a digital automatic phase control circuit that can be applied to.

Most conventional phase-locked circuits were constructed of analog circuits due to the current technological background, but recently many high-speed digital integrated circuits have been developed, and they have improved circuit size, economy, and ease of assembly and adjustment. Due to its many advantages, there is a gradual trend towards digital circuits. However, digital phase synchronization circuits, which are becoming more widely used, are not completely free from problems. Due to its nature, a digital phase-locked circuit is essentially called a phase-locked loop (PLL) because it drives a voltage-controlled oscillator (VCO) with a binary digital signal. (omitted) to generate phase jitter. Therefore, in order to suppress this, when designing a PLL, it is necessary to
Appropriately select the parameters of the low-pass filter in
A method is used to narrow the equivalent noise bandwidth (hereinafter referred to as BL) of the PLL, but this naturally has a limit because it impairs the pull-in characteristics of the PLL. Therefore, systems that require a high signal-to-noise ratio in PLLs are currently often configured with conventional analog circuits.

The present invention utilizes the advantages of digital circuits as they are, and is characterized by excellent pull-in characteristics and tracking characteristics.The purpose of the present invention is to provide a high-quality, highly versatile digital automatic phase control circuit. It's about doing.

In PLL, as in normal control systems, the pull-in (transient) characteristics and tracking characteristics are contradictory to each other, and in actual design, it is best to set them to a compromise that optimizes both as necessary. It will be done.
In a PLL using normal parameters, the BL is approximately proportional to the loop gain (hereinafter expressed as K). Tracking characteristics can be improved by narrowing the BL,
In other words, phase jitter is suppressed and a PLL with a high signal-to-noise ratio can be constructed, but on the other hand, the pull-in characteristics are inevitably degraded. Also,
Binary automatic phase control
Control, hereinafter abbreviated as APC. ) PLL with signal
Since the circuit generates more phase jitter than when using an analog APC signal, the BL must be set even narrower, which further impairs the pull-in characteristics. The present invention was developed to solve a series of problems as described above, and its configuration includes a voltage controlled oscillator, and a quasi-phase control signal obtained by comparing the phases of the output of the voltage controlled oscillator and the input signal. Detecting the integrated voltage deviation of the first flip-flop to be read, the second and subsequent flip-flops to read the quasi-phase control signal via a switch provided at the input, and the output of the previous flip-flop. an arithmetic control circuit for controlling a switch of the next flip-flop;
a weighting circuit for weighting the output of each subsequent flip-flop, and a low-pass filter having an input connected to a composite output of the weighting circuit and an output connected to an input of the voltage controlled oscillator;
When the frequency deviation of the input signal is not large and the state is not out of synchronization, the phase control signal is output only from the first flip-flop, and when the frequency deviation of the input signal is large or the state is out of synchronization, the phase control signal is output from the second flip-flop. The phase control signal is also output from the flip-flops after the flip-flop to control the phase.
By changing the range) in two ways as necessary, both the pull-in and tracking characteristics are improved, making it possible to realize a sufficiently high-quality PLL even with binary digital signals.

In other words, this is a circuit that equivalently changes BL by varying K, and also suppresses the occurrence of unnecessary phase jitter itself by changing the operating range of the APC voltage.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 shows an embodiment in which the present invention is applied to a carrier wave recovery circuit in a PSK phase modulation system.
Here, the quasi-APC signal is the APC signal (analog or digital) of a conventional PLL, and if it is fed back to the VCO via a low-pass filter, a normal PL can be configured.

FF1 and FF2 are D-type flip-flops, R ₁ ,
R ₂ and _RT are resistors (weighting circuits) that appropriately weight the output of each FF, R _I and C are integrators for the output voltage of FF1, and R _B1 , R _B2 , R _B3 , and R _B4 are between NAND gates. This is to detect the deviation of the integrated voltage by applying an appropriate potential difference to the voltage.

G1 to G5 are NAND gates, and the arithmetic control section 5 is composed of these G1 and G2, the R _B1 to R _B4 , and the integrating circuit _R1C .

Further, G3, G4, and G5 constitute a switch 6 that is controlled by the output of G1.

In this example, when there is no large frequency deviation in the input signal of the phase-locked circuit and the PLL is properly synchronized,
Since the mark rate (time rate at high level) of the output of FF1 is approximately 1/2, the output voltage of the integrator 7 remains at the gate threshold voltage. On the contrary, if the input signal has a large frequency shift or a phase shift, the threshold voltage of the arithmetic control section 5 fluctuates either upward or downward. In this configuration, in the former case, there is a voltage drop in R _B2 and R _B3 , so both of the two inputs of G1 are high.
The CONT signal and signal become high and low levels, respectively, and the output of FF2 is fed back to input D through the switches G4 and G5, and FF2 operates as a mere binary counter. In this case, FF2 is simply a pulse with a duty ratio of 50% at half the frequency of the clock signal, and since this is usually a sufficiently high frequency compared to the BL band, the low-pass filter in the PLL is The output is completely smoothed and contains only the DC component, which no longer contributes to the APC signal. In other words, there is no large frequency deviation in the input signal of the phase-locked loop;
When the PLL is properly synchronized, only the FF1 output operates as an APC signal.

Here, the resistance for weighting the FF output is R ₂ < R ₁
If you select , the loop gain K will be set during normal operation.
is small, and the dynamic range of APC voltage is also small.
It can be suppressed to be smaller than that of a binary digital signal that is the original output of an integrated circuit.

On the other hand, in the latter case, when the frequency deviation of the input signal becomes large or when the synchronization is lost, the output voltage of the integrator 7 will have a DC offset in either the upper or lower direction from the gate threshold voltage. , the two inputs of G1 are high and low levels, CONT, and the signals are low and low, respectively.
Becomes a high level. And FF2 is not a binary counter, but a quasi-APC through gates G3 and G5.
Read the signal.

Therefore, FF2 will now contribute to the APC signal. After going through this process and returning to normal operation, only the FF1 output contributes to APC again.

FIG. 2 is a block configuration diagram when the number of FFs is expanded to N.

By increasing the number of N, it is possible to approximate an analog circuit while maintaining good pull-in characteristics and tracking characteristics. Each flip-flop (FF1~ _FFN )
SW1, N-2, and N-1 connected to the inputs correspond to the switches composed of gates G3, G4, and G5 in Figure 1, and are calculated when the mark rate in the previous FF deviates. Controlled by control circuit 5
Switches to the side that reads APC signals. When the frequency deviation of the input signal is not large and there is no loss of synchronization, switch 6 is connected to the position shown, and FF2
The reason that the subsequent flip-flops operate only as binary counters and do not directly contribute to the APC signal is that N=
This is exactly the same as the second embodiment (FIG. 1). In addition,
The more circuits that are added, the more noise sources are created, so it is preferable to keep the number of FFs to the minimum necessary.

As described above, the present invention allows a PLL having a high signal-to-noise ratio to be configured even though it is a circuit in which a binary digital signal is configured as an APC signal. Therefore, in this case, which can be suitably applied to a system that requires such a thing, the present invention can be easily applied since it is only necessary to add the present invention to a part of the conventional circuit.

Furthermore, it is possible to obtain excellent pull-in characteristics and tracking characteristics that could not be easily achieved with conventional analog circuits. Furthermore, the present invention can be achieved without impairing the advantages of digital integrated circuits, such as circuit miniaturization, reduced power consumption, and ease of assembly and adjustment.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an embodiment of a digital automatic phase control circuit according to the present invention, and FIG. 2 is a circuit block diagram of an embodiment in which the number of flip-flops is expanded to N. 1...Flip-flop, 2...Gate, 3...
...Low-pass filter, 4...Voltage controlled oscillator, 5... Arithmetic control unit, 6... Switch, 7... Integrator, R ₁
~N, _RT , R _I , R _B1 ~ _B4 ...Resistor, C...Capacitor.

Claims (1)

[Claims] 1 a voltage controlled oscillator; a first flip-flop that directly reads a quasi-phase control signal obtained by comparing the phase of the output of the voltage controlled oscillator with the input signal; at least one flip-flop from the second flip-flop that reads a phase control signal; an arithmetic control circuit that detects the integrated voltage deviation of the output of the previous flip-flop and controls the switch of the next flip-flop; and a low-pass filter having an input connected to the composite output of the weighting circuit and an output connected to the input of the voltage controlled oscillator; outputting a phase control signal only from the first flip-flop when the frequency deviation of the signal is not large and there is no out-of-synchronization state;
A digital automatic phase control circuit characterized in that when an input signal has a large frequency deviation or is out of synchronization, a phase control signal is output from the second and subsequent flip-flops for phase control.