JPS6355869B2 - - Google Patents
Info
- Publication number
- JPS6355869B2 JPS6355869B2 JP57232399A JP23239982A JPS6355869B2 JP S6355869 B2 JPS6355869 B2 JP S6355869B2 JP 57232399 A JP57232399 A JP 57232399A JP 23239982 A JP23239982 A JP 23239982A JP S6355869 B2 JPS6355869 B2 JP S6355869B2
- Authority
- JP
- Japan
- Prior art keywords
- source electrode
- mos
- contact
- type
- contact region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/84—Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明はMOS集積回路に関し、特にエンハン
スメントMOSトランジスタとデイプレツシヨン
MOSトランジスタとを含むMOS集積回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to MOS integrated circuits, and in particular to enhancement MOS transistors and depletion transistors.
The present invention relates to a MOS integrated circuit including a MOS transistor.
従来、エンハンスメントMOSトランジスタ
（以下Ｅ−MOSTと記す）とデイプレツシヨン
MOSトランジスタ（以下Ｄ−MOSTと記す）と
のレシオ（ratio）構成からなるMOS集積回路
（以下Ｅ／Ｄ・MOS・ICと記す）においては、電
流を定常的に流しているため、Ｅ−MOSTのソ
ース電位の電圧降下などが回路の動作不良の原因
となるという問題があつた。 Conventionally, enhancement MOS transistors (hereinafter referred to as E-MOST) and depletion
In a MOS integrated circuit (hereinafter referred to as E/D・MOS・IC) that has a ratio configuration with a MOS transistor (hereinafter referred to as D-MOST), current flows steadily, so E-MOST There was a problem in that a voltage drop in the source potential of the circuit caused malfunction of the circuit.
第１図は従来のMOSインバータの一例の回路
図である。 FIG. 1 is a circuit diagram of an example of a conventional MOS inverter.
このMOSインバータはＰチヤンネルＥ−
MOST１とＰチヤンネル−MOST２とが直列接
続され、ソースに電源VDD，VSSが接続され、ゲ
ートに入力された信号はドレインから反転して取
出される。 This MOS inverter has P channel E-
MOST1 and P channel-MOST2 are connected in series, the sources are connected to power supplies VDD and VSS , and the signal input to the gate is inverted and taken out from the drain.
第２図は半導体基板に形成したMOSインバー
タの断面図である。 FIG. 2 is a sectional view of a MOS inverter formed on a semiconductor substrate.
N-型半導体基板１１にＥ−MOSTのＰ型ソー
ス領域１２、Ｐ型ドレイン領域１３、Ｄ−
MOSTのＰ型ソース領域１４、Ｐ型ドレイン領
域１５及びN+型接触用領域１６を形成する。表
面にフイールド絶縁膜１７、ゲート絶縁膜１８を
設け、VSS電源コンタクト１９、出力電極２０、
入力電極２１、ソース電極２２、VDD電源コンタ
クト２３を設ける。N+型接触用領域１６にVDD電
源が入力されて基板電位が保持される。Ｅ−
MOSTのソース電極２２はVDD電源が入力するの
で、ソース電極２２はソース領域１２の近くの基
板表面と接続しても良い筈であるが、実際には電
圧降下が起るので、VDD電源が直接入力するVDD
電源コンタクト２２とソース電極とをアルミニウ
ム配線（図示せず）でつないでいた。このため、
マスク設計の自由度が低下するのみならずチツプ
寸法の増大を招くという欠点があつた。 N - type semiconductor substrate 11, E-MOST P type source region 12, P type drain region 13, D-
A P type source region 14, a P type drain region 15, and an N + type contact region 16 of the MOST are formed. A field insulating film 17 and a gate insulating film 18 are provided on the surface, a V SS power contact 19, an output electrode 20,
An input electrode 21, a source electrode 22, and a VDD power contact 23 are provided. V DD power is input to the N + type contact region 16 to maintain the substrate potential. E-
Since the source electrode 22 of the MOST receives the V DD power supply, it should be possible to connect the source electrode 22 to the substrate surface near the source region 12, but in reality, a voltage drop will occur, so the V DD power supply should be connected to the source electrode 22. directly input V DD
The power contact 22 and the source electrode were connected with aluminum wiring (not shown). For this reason,
This has the disadvantage that it not only reduces the degree of freedom in mask design but also increases chip size.
本発明は上記欠点を除去し、アルミニウム配線
数を減らし、マスク設計の自由度を向上させると
共にチツプ寸法を小さくしたMOS集積回路を提
供するものである。 The present invention eliminates the above-mentioned drawbacks, reduces the number of aluminum wiring lines, increases the degree of freedom in mask design, and provides a MOS integrated circuit with reduced chip size.
本発明のMOS集積回路は、一導電型半導体基
板に設けられたエンハンスメントMOSトランジ
スタ及びデイプレツシヨンMOSトランジスタと、
前記半導体基板に設けられた一導電型で高不純物
濃度の接触用領域と、前記接触用領域に直接にオ
ーミツク接触して基板電位に接続するソース電極
と、前記接触用領域にオーミツク接触しかつ前記
ソース電極とは別に設けられ電源に接続する電源
電極とを含んで構成される。 The MOS integrated circuit of the present invention includes an enhancement MOS transistor and a depletion MOS transistor provided on a semiconductor substrate of one conductivity type,
a contact region of one conductivity type and high impurity concentration provided on the semiconductor substrate; a source electrode that is in direct ohmic contact with the contact region and connected to the substrate potential; and a source electrode that is in ohmic contact with the contact region and connected to the substrate potential. It is configured to include a power supply electrode provided separately from the source electrode and connected to a power supply.
次に本発明の実施例について図面を用いて説明
する。 Next, embodiments of the present invention will be described using the drawings.
第３図は本発明の一実施例の断面図、第４図は
第１図に示す一実施例の等価回路図である。第３
図、第４図において第２図、第１図と同じものに
対しては同じ番号、符号を付してある。 FIG. 3 is a sectional view of an embodiment of the present invention, and FIG. 4 is an equivalent circuit diagram of the embodiment shown in FIG. Third
In FIGS. 2 and 4, the same parts as in FIGS. 2 and 1 are given the same numbers and symbols.
この実施例では、N+型接触用領域１６′を延長
してソース領域１２に接合させている。そしてソ
ース電極２２′はソース領域１２に接触すると共
にN+型接触用領域１６′にも接触している。N+
型接触用領域１６′にはVDD電源が接続されるか
ら、N+型接触用領域１６′の抵抗を介してソース
電極２２′はVDD電源と接続していることになる。
第４図で抵抗２６はN+型接触用電極２３からN+
型接触用領域１６′を通つてソース電極２２′へ至
るまでの抵抗を表わす。この抵抗２６はＥ−
MOST１のオン抵抗に比べて充分小さくなるよ
うに設計する。即ち高キヤリア濃度にして抵抗値
を下げるようにする。 In this embodiment, the N + type contact region 16' is extended and joined to the source region 12. The source electrode 22' is in contact with the source region 12 and also in contact with the N + type contact region 16'. N +
Since the V DD power source is connected to the type contact region 16', the source electrode 22' is connected to the V DD power source via the resistance of the N + type contact region 16'.
In Fig. 4, the resistor 26 is connected to the N + type contact electrode 23 .
It represents the resistance through the mold contact region 16' to the source electrode 22'. This resistor 26 is E-
Design it so that it is sufficiently smaller than the on-resistance of MOST1. That is, the resistance value is lowered by increasing the carrier concentration.
尚、図示していないが、他の領域にもN+型接
触用領域１６′と同様のN+型接触用領域を設け、
そこにもVDD電源コンタクトを設け、アルミニウ
ム等の配線で結合することにより半導体基板の電
位を均一にすると共に半導体基板のインピーダン
スを小さくすることができる。 Although not shown, an N + type contact area similar to the N + type contact area 16' is provided in other areas.
By providing a V DD power contact there as well and connecting it with wiring such as aluminum, it is possible to make the potential of the semiconductor substrate uniform and to reduce the impedance of the semiconductor substrate.
上記実施例は、ＰチヤンネルＥ／Ｄ・MOS・
ICで説明したが、本発明はＮチヤンネルＥ／
Ｄ・MOS・ICについても、またＣ−MOS・ICに
ついても同様に適用できる。 In the above embodiment, P channel E/D・MOS・
Although explained in terms of IC, the present invention also applies to N-channel E/
The same applies to D-MOS-IC and C-MOS-IC.
以上詳細に説明したように、本発明によれば、
配線数を減らし、設計の自由度を上げ、チツプ寸
法を小さくしたMOS集積回路が得られるのでそ
の効果は大きい。 As explained in detail above, according to the present invention,
The effect is significant because it reduces the number of wiring lines, increases the degree of freedom in design, and provides a MOS integrated circuit with a smaller chip size.
第１図は従来のMOSインバータの一例の回路
図、第２図は第１図に示すMOSインバータを半
導体基板に実現したものの断面図、第３図は本発
明の一実施例の断面図、第４図は第３図に示す一
実施例の等価回路図である。
１……エンハンスメントMOSトランジスタ、
２……デイプレツシヨンMOSトランジスタ、１
１……Ｎ型半導体基板、１２……Ｐ型ソース領
域、１３……Ｐ型ドレイン領域、１４……Ｐ型ソ
ース領域、１５……Ｐ型ドレイン領域、１６，１
６′……Ｎ型接触用領域、１７……フイールド絶
縁膜、１８……ゲート絶縁膜、１９……VSS電源
コンタクト、２０……出力電極、２１……入力電
極、２２……ソース電極、２３……VDD電源コン
タクト、２６……抵抗。
Fig. 1 is a circuit diagram of an example of a conventional MOS inverter, Fig. 2 is a sectional view of the MOS inverter shown in Fig. 1 realized on a semiconductor substrate, and Fig. 3 is a sectional view of an embodiment of the present invention. FIG. 4 is an equivalent circuit diagram of the embodiment shown in FIG. 3. 1...Enhancement MOS transistor,
2...depression MOS transistor, 1
1...N-type semiconductor substrate, 12...P-type source region, 13...P-type drain region, 14...P-type source region, 15...P-type drain region, 16,1
6'... N-type contact area, 17... Field insulating film, 18... Gate insulating film, 19... V SS power contact, 20... Output electrode, 21... Input electrode, 22... Source electrode, 23...V DD power contact, 26...Resistor.
Claims (1)
メントMOSトランジスタ及びデイプレツシヨン
MOSトランジスタと、前記半導体基板に設けら
れた一導電型で高不純物濃度の接触用領域と、前
記接触用領域に直接にオーミツク接触して基板電
位に接続するソース電極と、前記接触用領域にオ
ーミツク接触しかつ前記ソース電極とは別に設け
られ電源に接続する電源電極とを含むことを特徴
とするMOS集積回路。1 Enhancement MOS transistor and depletion provided on one conductivity type semiconductor substrate
a MOS transistor, a contact region of one conductivity type and high impurity concentration provided on the semiconductor substrate, a source electrode that is in direct ohmic contact with the contact region and connected to the substrate potential, and an ohmic contact region in the contact region. 1. A MOS integrated circuit comprising: a power supply electrode that is in contact with the source electrode and is provided separately from the source electrode and connected to a power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57232399A JPS59117151A (en) | 1982-12-23 | 1982-12-23 | Metal oxide semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57232399A JPS59117151A (en) | 1982-12-23 | 1982-12-23 | Metal oxide semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59117151A JPS59117151A (en) | 1984-07-06 |
| JPS6355869B2 true JPS6355869B2 (en) | 1988-11-04 |
Family
ID=16938629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57232399A Granted JPS59117151A (en) | 1982-12-23 | 1982-12-23 | Metal oxide semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59117151A (en) |
-
1982
- 1982-12-23 JP JP57232399A patent/JPS59117151A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59117151A (en) | 1984-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0653497A (en) | Semiconductor device equipped with i/o protective circuit | |
| JP2602974B2 (en) | CMOS semiconductor integrated circuit device | |
| JPS6355869B2 (en) | ||
| JPS6362904B2 (en) | ||
| JPH08115985A (en) | Low noise semiconductor integrated circuit | |
| JPH038357A (en) | Semiconductor integrated circuit device | |
| JPH0412627B2 (en) | ||
| JPH03276757A (en) | Semiconductor device | |
| JP3128813B2 (en) | Semiconductor integrated circuit | |
| JPH02294063A (en) | semiconductor integrated circuit | |
| JP3271435B2 (en) | Semiconductor integrated circuit device | |
| KR850007315A (en) | Complementary metal oxide semiconductor integrated circuit device | |
| JPS5944782B2 (en) | semiconductor integrated circuit | |
| JPH0636596Y2 (en) | CMOS semiconductor device | |
| KR850005159A (en) | Semiconductor integrated circuit with power supply passage to board | |
| JPH056964A (en) | Semiconductor integrated circuit device | |
| JPS62104068A (en) | Semiconductor integrated circuit device | |
| JPH01273346A (en) | Semiconductor device | |
| JPH03116863A (en) | Semiconductor integrated circuit device | |
| JPS6042622B2 (en) | Complementary MOS integrated circuit | |
| JPS56108257A (en) | Semiconductor integrated circuit device | |
| JPH0314232B2 (en) | ||
| JPH01231361A (en) | Semiconductor device | |
| JPS6281053A (en) | Semiconductor integrated circuit device | |
| JPH02226760A (en) | Semiconductor logic circuit |