JPS6356719B2 - - Google Patents
Info
- Publication number
- JPS6356719B2 JPS6356719B2 JP19030684A JP19030684A JPS6356719B2 JP S6356719 B2 JPS6356719 B2 JP S6356719B2 JP 19030684 A JP19030684 A JP 19030684A JP 19030684 A JP19030684 A JP 19030684A JP S6356719 B2 JPS6356719 B2 JP S6356719B2
- Authority
- JP
- Japan
- Prior art keywords
- resist layer
- film
- conductive pattern
- present
- liquid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000007788 liquid Substances 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 54
- 239000011229 interlayer Substances 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 7
- 229920006267 polyester film Polymers 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000000740 bleeding effect Effects 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明は多層配線基板、特に微細化加工に適し
た多層配線基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a multilayer wiring board, and particularly to a method for manufacturing a multilayer wiring board suitable for miniaturization.
(ロ) 従来の技術
従来の多層配線基板の製造方法では第2図に示
す多層配線を実現するには第3図の如く、セラミ
ツク等の絶縁基板1上に銅箔等の第1の導電パタ
ーン2を形成し、その上に絶縁材料を2度スクリ
ーン印刷して十分に厚くした絶縁物層3を設け、
更にその上に第2の導電パターン4を形成して構
成していた。(b) Conventional technology In the conventional manufacturing method of a multilayer wiring board, in order to realize the multilayer wiring shown in FIG. 2, as shown in FIG. 2 is formed, and an insulating material layer 3 made sufficiently thick by screen printing an insulating material twice is provided thereon,
Further, a second conductive pattern 4 was formed thereon.
斯上の構造では第1の導電パターン2と第2の
導電パターン4の接続部は絶縁材料のスクリーン
印刷時に選択的に窓5を形成して両者を接触でき
る様にしている。 In the above structure, a window 5 is selectively formed at the connection portion between the first conductive pattern 2 and the second conductive pattern 4 during screen printing of the insulating material so that the two can come into contact with each other.
例えばこの種の技術は特願昭58−118697号等に
開示されている。 For example, this type of technology is disclosed in Japanese Patent Application No. 118697/1983.
しかしながら斯上した製造方法では絶縁材料は
有機溶剤でペースト状としてスクリーン印刷する
ので、窓5のエツヂが鮮明に印刷できず第2図の
如く内側ににじみが発生して窓5がつぶされる危
惧があつた。このため窓5をにじみを考慮して十
分に大きく、例えば直径300μに形成していた。
この結果第1の導電パターン2および第2の導電
パターン4はこの大きさの窓5を形成できるだけ
十分に離間させる必要があり、微細化パターン加
工の障害となつていた。更に第1の導電パターン
2の厚みにより絶縁物層3表面にも段差を生じ、
第2の導電パターン4を微細化パターン加工でき
難い障害もあつた。 However, in the manufacturing method described above, the insulating material is screen printed in the form of a paste using an organic solvent, so the edges of the window 5 cannot be clearly printed, and as shown in Figure 2, there is a risk that bleeding may occur on the inside and the window 5 may be crushed. It was hot. For this reason, the window 5 is formed to be sufficiently large, for example, 300 μm in diameter, in consideration of bleeding.
As a result, the first conductive pattern 2 and the second conductive pattern 4 must be spaced apart from each other sufficiently to form a window 5 of this size, which has been an obstacle to fine pattern processing. Furthermore, due to the thickness of the first conductive pattern 2, a step is created on the surface of the insulating layer 3,
There was also a problem in which it was difficult to process the second conductive pattern 4 into a finer pattern.
本発明は斯る欠点を改善するために第4図イ〜
ホに示す多層配線基板の製造方法を提案した。即
ち第4図イに示す如く、絶縁基板11上に第1の
導電パターン12を形成する。次に第4図ロに示
す如く、第1の導電パターン12間に液状レジス
ト層13をスピンオンにより塗布し、配線層12
間のくぼみを平坦化している。続いて第4図ハに
示す如く、液状レジスト層13上にフイルム状レ
ジスト層14をロールコートしている。フイルム
状レジスト層14はポリエステルフイルム上に感
光性レジストを塗布乾燥したもので、一定の厚み
と平坦面を有しているので、フイルム状レジスト
層14上はほぼ平坦面を形成できる。更に第1図
ニに示す如く、第1の導電パターン12上の液状
レジスト層13およびフイルム状レジスト層14
にホトエツチング技術によりスルーホール15を
形成している。その後第1図ホに示す如く、フイ
ルム状レジスト層14表面に第2の導電パターン
16を形成し、スルーホール15を介して第1の
導電パターン12との接続も行う。 The present invention aims to improve the drawbacks shown in FIG.
We proposed a method for manufacturing a multilayer wiring board shown in E. That is, as shown in FIG. 4A, a first conductive pattern 12 is formed on an insulating substrate 11. Next, as shown in FIG. 4B, a liquid resist layer 13 is applied between the first conductive patterns 12 by spin-on, and the wiring layer 12
Flattening the depression between the two. Subsequently, as shown in FIG. 4C, a film resist layer 14 is roll coated on the liquid resist layer 13. The film-like resist layer 14 is made by coating and drying a photosensitive resist on a polyester film, and has a constant thickness and a flat surface, so that a substantially flat surface can be formed on the film-like resist layer 14. Further, as shown in FIG. 1D, a liquid resist layer 13 and a film resist layer 14 are formed on the first conductive pattern 12.
A through hole 15 is formed in the photoetching technique. Then, as shown in FIG.
(ハ) 発明が解決しようとする問題点
斯上した製造方法では層間絶縁膜を液状レジス
ト層13とフイルム状レジスト層14の2層で形
成することにより、極めて平坦な上面を実現でき
るので、第2の導電パターン16の微細化加工を
実現できる利点を有する。(c) Problems to be Solved by the Invention In the above manufacturing method, an extremely flat top surface can be achieved by forming the interlayer insulating film with two layers, the liquid resist layer 13 and the film resist layer 14. This has the advantage that miniaturization of the conductive pattern 16 of No. 2 can be realized.
しかしその反面第2の導電パターン16とフイ
ルム状レジスト層14の接着強度が大きく採れな
いので、第2の導電パターン16が剥離するおそ
れがあつた。 However, on the other hand, the adhesion strength between the second conductive pattern 16 and the film-like resist layer 14 could not be maintained high, so there was a risk that the second conductive pattern 16 would peel off.
(ニ) 問題点を解決するための手段
本発明は斯点に鑑みてなされ、層間絶縁膜とし
て液状レジスト層とフイルム状レジスト層とを用
い且つフイルム状レジスト層表面を適度に粗化す
ることにより微細化加工に最適の多層配線基板の
製造方法を提供するものである。(d) Means for Solving the Problems The present invention has been made in view of the above points, and uses a liquid resist layer and a film-like resist layer as an interlayer insulating film, and appropriately roughens the surface of the film-like resist layer. The present invention provides a method for manufacturing a multilayer wiring board that is optimal for miniaturization.
(ホ) 作用
本発明では層間絶縁膜として液状レジスト層と
フイルム状レジスト層とを用いるので、微細化加
工に適したホトエツチング技術によりスルーホー
ルを形成できる。また本発明では層間絶縁膜の一
部に液状レジスト層を用いるので、第1の導電パ
ターンの段差を解消でき上面が平坦な層間絶縁膜
と形成でき第2の導電パターンの微細化加工を行
なえる。更に本発明ではフイルム状レジスト層表
面を粗化するので第2の導電パターンの接着力を
強化でき微細化加工に適する。(e) Effect Since the present invention uses a liquid resist layer and a film resist layer as the interlayer insulating film, through holes can be formed by photoetching technology suitable for miniaturization. Furthermore, in the present invention, since a liquid resist layer is used as a part of the interlayer insulating film, it is possible to eliminate the step difference in the first conductive pattern, form an interlayer insulating film with a flat top surface, and perform fine processing of the second conductive pattern. . Furthermore, in the present invention, since the surface of the film-like resist layer is roughened, the adhesive force of the second conductive pattern can be strengthened, making it suitable for microfabrication processing.
(ヘ) 実施例
本発明の第1の工程は第1図イに示す如く、絶
縁基板21上に第1の導電パターン22を形成す
ることにある。絶縁基板21としてはセラミツク
スあるいは表面を酸化膜で被覆したアルミニウム
等を用い、第1の導電パターン22は基板21に
全面に銅箔を貼着した後所望のパターンにエツチ
ングして形成される。なお本工程で第1の導電パ
ターン22を微細化加工を行う場合ホトエツチン
グ技術に依れば良く、銅箔を用いても約50μの線
巾を十分に実現できる。(F) Example The first step of the present invention is to form a first conductive pattern 22 on an insulating substrate 21, as shown in FIG. 1A. The insulating substrate 21 is made of ceramics or aluminum whose surface is coated with an oxide film, and the first conductive pattern 22 is formed by attaching copper foil to the entire surface of the substrate 21 and then etching it into a desired pattern. Note that when microfabrication of the first conductive pattern 22 is performed in this step, photoetching technology may be used, and a line width of approximately 50 μm can be sufficiently achieved even if copper foil is used.
本発明の第2の工程は第1図ロに示す如く、第
1の導電パターン22間に液状レジスト層23を
付着することにある。液状レジスト層23は基板
21表面に滴下した後、スピンオンにより全面に
塗布している。この結果液状レジスト層23は液
体であるので配線層22間のくぼみ部分に充填さ
れ、配線層22上にはほとんど付着されず、配線
層22間を平坦化する様に付着できる。これによ
り配線層22と液状レジスト層23とでほぼ平坦
面を形成できる。液状レジスト層23はベーキン
グされて硬化される。 The second step of the present invention consists in depositing a liquid resist layer 23 between the first conductive patterns 22, as shown in FIG. 1B. The liquid resist layer 23 is dropped onto the surface of the substrate 21 and then applied to the entire surface by spin-on. As a result, since the liquid resist layer 23 is a liquid, it fills the recessed portions between the wiring layers 22, hardly adheres to the wiring layers 22, and can adhere so as to flatten the space between the wiring layers 22. This allows the wiring layer 22 and the liquid resist layer 23 to form a substantially flat surface. Liquid resist layer 23 is baked and hardened.
本発明の第3の工程は第1図ハに示す如く、液
状レジスト層23上にフイルム状レジスト層24
を付着することにある。フイルム状レジスト層2
4はポリエステルフイルム25上に感光性レジス
トを塗布乾燥したもので一定の厚みを有してい
る。更に本発明の特徴とする点であるが、ポリエ
ステルフイルム25表面は機械的にブラツシング
したり、化学的に酸又はアルカリ溶剤でエツチン
グしたりあるいは逆スパツタして予じめ粗化して
おく。ポリエステルフイルム25は最初は0.5μ以
下の凹凸しか有していないが、上記した粗化処理
により3〜5μの凹凸を形成できる。この表面を
粗化したポリエステルフイルム25上に感光性レ
ジストを塗布乾燥してフイルム状レジスト層24
を形成する。このフイルム状レジスト層24はロ
ールコーターを用いて液状レジスト層23上に接
着され、両者で層間絶縁膜を形成する。なおポリ
エステルフイルム25は付着後剥離して除去し、
フイルム状レジスト層24上面には3〜5μの凹
凸が形成される。本工程で付着されるフイルム状
レジスト層24はほぼ平坦面を有し且つ適当な表
面粗さを有しているのが特徴である。 The third step of the present invention is to form a film resist layer 24 on a liquid resist layer 23, as shown in FIG.
It consists in attaching. Film resist layer 2
4 is a polyester film 25 coated with a photosensitive resist and dried to have a certain thickness. Another feature of the present invention is that the surface of the polyester film 25 is roughened in advance by mechanical brushing, chemical etching with an acid or alkaline solvent, or reverse sputtering. Initially, the polyester film 25 has an unevenness of 0.5 μm or less, but by the above-described roughening treatment, an unevenness of 3 to 5 μm can be formed. A photosensitive resist is applied and dried on the polyester film 25 whose surface has been roughened to form a film-like resist layer 25.
form. This film-like resist layer 24 is adhered onto the liquid resist layer 23 using a roll coater, and the two form an interlayer insulating film. Note that the polyester film 25 is peeled off and removed after attachment.
Irregularities of 3 to 5 μm are formed on the upper surface of the film-like resist layer 24 . The film-like resist layer 24 deposited in this step is characterized by having a substantially flat surface and appropriate surface roughness.
本発明の第4の工程は第1図ニに示す如く、第
1の導電パターン22上の液状レジスト層23お
よびフイルム状レジスト層24にスルーホール2
6を形成することにある。本工程では周知のホト
エツチング技術を利用して、スルーホール26を
形成する予定の第1の導電路22上の両レジスト
層23,24を露光現像し、有機溶剤で溶かして
スルーホール26を形成する。この結果スルーホ
ール26はホトエツチング技術により形成できる
ので、極めて高精度に形成できる利点がある。 In the fourth step of the present invention, as shown in FIG.
6. In this step, using a well-known photoetching technique, both resist layers 23 and 24 on the first conductive path 22 where the through hole 26 is to be formed are exposed and developed, and then dissolved with an organic solvent to form the through hole 26. . As a result, the through-holes 26 can be formed by photo-etching technology, which has the advantage of being able to be formed with extremely high precision.
本発明の第5の工程は第1図ホに示す如く、フ
イルム状レジスト層24の粗化した表面上に第2
の導電パターン27を形成することにある。前述
した液状レジスト層23およびフイルム状レジス
ト層24は永久レジスト層として層間絶縁膜とし
て用いる。第2の導電パターン27はスルーホー
ル26を含むフイルム状レジスト層24全面に銅
あるいはニツケルメツキ層を形成後、所望のパタ
ーンにエツチングして形成される。この際第2の
導電パターン27はほぼ平坦面上に形成されるの
で、ホトエツチング技術を用いても第1の導電パ
ターンに寄因する段差により生ずる露光ぼけを完
全に防止でき、更にフイルム状レジスト層24表
面の粗化により第2の導電パターン27の接着強
度を大巾に向上できるので、微細化加工を容易に
実現できる。また第2の導電パターン27はスル
ーホール26にも同時に形成されるメツキ層によ
り第1の導電パターン22と確実に接続できる。 In the fifth step of the present invention, as shown in FIG.
The purpose is to form a conductive pattern 27. The liquid resist layer 23 and the film resist layer 24 described above are used as a permanent resist layer and an interlayer insulating film. The second conductive pattern 27 is formed by forming a copper or nickel plating layer on the entire surface of the film-like resist layer 24 including the through holes 26, and then etching it into a desired pattern. At this time, since the second conductive pattern 27 is formed on a substantially flat surface, it is possible to completely prevent exposure blur caused by the step caused by the first conductive pattern even if photoetching technology is used, and furthermore, the film-like resist layer Since the adhesive strength of the second conductive pattern 27 can be greatly improved by roughening the surface of the pattern 24, miniaturization can be easily realized. Furthermore, the second conductive pattern 27 can be reliably connected to the first conductive pattern 22 by a plating layer that is simultaneously formed on the through holes 26 as well.
(ト) 発明の効果
本発明の第1の効果は層間絶縁膜を液状レジス
ト層23とフイルム状レジスト層24の2層とす
ることにより、極めて平坦な上面を有する層間絶
縁膜を実現できるので、第2の導電パターン27
の微細化加工を実現できる利点を有する。(G) Effects of the Invention The first effect of the present invention is that by forming the interlayer insulating film into two layers, the liquid resist layer 23 and the film resist layer 24, an interlayer insulating film having an extremely flat upper surface can be realized. Second conductive pattern 27
It has the advantage of realizing finer processing.
本発明の第2の効果は層間絶縁膜を永久レジス
ト層で構成することにより、ホトエツチング技術
でスルーホール26を形成できるので、スルーホ
ール26を極めて高精度に形成でき微細化加工に
適する利点を有する。 The second effect of the present invention is that by forming the interlayer insulating film with a permanent resist layer, the through-holes 26 can be formed using photoetching technology, which has the advantage that the through-holes 26 can be formed with extremely high precision and are suitable for miniaturization processing. .
本発明の第3の効果は層間絶縁膜のフイルム状
レジスト層24表面を適当に粗化できるので第2
の導電パターン27の接着強度を向上でき微細パ
ターンでも剥離を防止できる利点を有する。 The third effect of the present invention is that the surface of the film-like resist layer 24 of the interlayer insulating film can be appropriately roughened.
This has the advantage that the adhesive strength of the conductive pattern 27 can be improved and peeling can be prevented even with a fine pattern.
本発明の第4の効果は層間絶縁膜を両レジスト
層23,24で形成できるので、高温加熱処理を
必要とせず、あらゆる絶縁基板21への適用がで
きる利点を有する。 The fourth advantage of the present invention is that since the interlayer insulating film can be formed using both resist layers 23 and 24, high-temperature heat treatment is not required and the present invention can be applied to any type of insulating substrate 21.
第1図イ,ロ,ハ,ニ,ホは本発明の多層配線
基板の製造方法を説明する断面図、第2図は従来
の多層配線基板を説明する上面図、第3図は第2
図A−A線断面図、第4図イ,ロ,ハ,ニ,ホは
従来の改良した多層配線基板の製造方法を説明す
る断面図である。
主な図番の説明、21は絶縁基板、22は第1
の導電パターン、23は液状レジスト層、24は
フイルム状レジスト層、26はスルーホール、2
7は第2の導電パターンである。
Figure 1 A, B, C, D, and Ho are cross-sectional views explaining the method for manufacturing a multilayer wiring board of the present invention, Figure 2 is a top view explaining a conventional multilayer wiring board, and Figure 3 is a cross-sectional view explaining the method for manufacturing a multilayer wiring board of the present invention.
A cross-sectional view taken along the line A--A in FIG. 4, and FIGS. Explanation of the main drawing numbers, 21 is the insulating substrate, 22 is the first
conductive pattern, 23 is a liquid resist layer, 24 is a film resist layer, 26 is a through hole, 2
7 is a second conductive pattern.
Claims (1)
工程、該第1の導電パターン間に液状レジスト層
を付着する工程、該液状レジスト層上に表面を粗
化したフイルム状レジスト層を付着する工程、前
記第1の導電パターン上の液状レジスト層および
フイルム状レジスト層にスルーホールを形状する
工程、該スルーホールを介して前記第1の導電パ
ターンと接続され且つ前記フイルム状レジスト層
の粗化した表面上に延在される第2の導電パター
ンを形成する工程とを具備することを特徴とする
多層配線基板の製造方法。1. A step of forming a first conductive pattern on an insulating substrate, a step of attaching a liquid resist layer between the first conductive patterns, and a step of attaching a film-like resist layer with a roughened surface on the liquid resist layer. forming a through hole in the liquid resist layer and the film resist layer on the first conductive pattern, which is connected to the first conductive pattern through the through hole and is roughened in the film resist layer; A method for manufacturing a multilayer wiring board, comprising the step of forming a second conductive pattern extending on the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19030684A JPS6167990A (en) | 1984-09-11 | 1984-09-11 | Method of producing multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19030684A JPS6167990A (en) | 1984-09-11 | 1984-09-11 | Method of producing multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6167990A JPS6167990A (en) | 1986-04-08 |
| JPS6356719B2 true JPS6356719B2 (en) | 1988-11-09 |
Family
ID=16255963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19030684A Granted JPS6167990A (en) | 1984-09-11 | 1984-09-11 | Method of producing multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6167990A (en) |
-
1984
- 1984-09-11 JP JP19030684A patent/JPS6167990A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6167990A (en) | 1986-04-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR920005070B1 (en) | Method of manufacturing double sided wiring substrate | |
| KR20040095716A (en) | Method for producing wired circuit board | |
| JPH05335713A (en) | Laminated board for printed circuit board with one side closed micro through hole, and method for conducting plating on the laminated board for printed circuit board | |
| JPS6356718B2 (en) | ||
| JPS6356719B2 (en) | ||
| JPH09307216A (en) | Wiring board manufacturing method and wiring board | |
| JPS6155797B2 (en) | ||
| JPH08186373A (en) | Manufacture of printed wiring board | |
| JPH0682924B2 (en) | Manufacturing method of composite substrate | |
| JP2004266078A (en) | Conductor pattern forming method | |
| JP3080508B2 (en) | Multilayer wiring board and method of manufacturing the same | |
| JPH0563340A (en) | Manufacture of wiring board provided with functional element | |
| JPH02106091A (en) | Formation of double-sided pattern | |
| JPS5999793A (en) | Printed circuit board | |
| JPH02301187A (en) | Manufacture of both-sided wiring board | |
| JP3828205B2 (en) | Method for manufacturing transfer member and transfer member | |
| JPH07221430A (en) | Manufacture of wiring board | |
| GB2307351A (en) | Printed circuit boards and their manufacture | |
| JPS6138638B2 (en) | ||
| JPH0296389A (en) | Double-side printed circuit board | |
| JPS63301591A (en) | Formation of cover-lay for printed board | |
| JP3130707B2 (en) | Printed circuit board and method of manufacturing the same | |
| JPS6040200B2 (en) | Multilayer circuit board manufacturing method | |
| JP2001105563A (en) | Screen plate and method of manufacturing wiring board using the same | |
| JP3688940B2 (en) | Wiring pattern formation method for flexible circuit board |