JPS6357942B2 - - Google Patents
Info
- Publication number
- JPS6357942B2 JPS6357942B2 JP57164465A JP16446582A JPS6357942B2 JP S6357942 B2 JPS6357942 B2 JP S6357942B2 JP 57164465 A JP57164465 A JP 57164465A JP 16446582 A JP16446582 A JP 16446582A JP S6357942 B2 JPS6357942 B2 JP S6357942B2
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- gold
- pattern
- plating
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/701—Tape-automated bond [TAB] connectors
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemically Coating (AREA)
- Electroplating Methods And Accessories (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法にかかり、主に
テープキヤリヤ式集積回路の製造方法に関するも
のであり、特に金属突起電極の形状の安定化、製
造歩留りの向上に有力な効果を発揮する製造方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and mainly relates to a method of manufacturing a tape carrier type integrated circuit, and is particularly effective in stabilizing the shape of metal protruding electrodes and improving manufacturing yield. The present invention relates to a manufacturing method that exhibits the following characteristics.
一般に第1のフオトレジストによりパターンを
形成し、これをマスクとして第1のメツキにより
金属配線を形成し、第2のフオトレジストにより
突起電極用パターンを形成し、水洗によりメツキ
液を除去した後第2のメツキによつて金属突起電
極を形成する方式の従来技術にかかる半導体装置
の製法においては、第1のメツキ液の残渣がメツ
キ表面の凹凸部分に取りこまれて十分に除去され
ないまま第2のフオトレジストを被着し、露光・
現像処理等が行なわれるため、現像時などにフオ
トレジストパターンの変形が起りやすい。即ち、
第1のメツキ面とフオトレジストの界面にメツキ
液の残渣が存在するため、フオトレジストのメツ
キ面への接着性が低下し、現像時にフオトレジス
トの膨潤が促進され、パターンの移動が起つてし
まう。上記フオトレジストパターンの変形は第2
のメツキによつて形成される金属突起電極形状の
変形となり、リード線と金属突起電極の接着性を
低下させる等、該半導体装置の信頼性に重大な悪
影響を及ぼす。 Generally, a pattern is formed using a first photoresist, using this as a mask, metal wiring is formed by first plating, a pattern for protruding electrodes is formed using a second photoresist, the plating solution is removed by washing with water, and then the plating solution is removed. In the conventional semiconductor device manufacturing method of forming metal protruding electrodes by plating the second plating solution, the residue of the first plating solution is incorporated into the uneven portions of the plating surface and is not sufficiently removed before the second plating solution is applied. photoresist, exposed and
Since development processing and the like are performed, deformation of the photoresist pattern is likely to occur during development. That is,
The presence of plating solution residue at the interface between the first plating surface and the photoresist reduces the adhesion of the photoresist to the plating surface, promoting swelling of the photoresist during development and causing pattern movement. . The modification of the above photoresist pattern is the second
This deforms the shape of the metal protrusion electrode formed by the plating and reduces the adhesion between the lead wire and the metal protrusion electrode, which has a serious adverse effect on the reliability of the semiconductor device.
この様なフオトレジストパターンの変形を防ぐ
方法として、第2のフオトレジスト被着前に超音
波で励振した純水中に浸漬して該基板を洗浄して
メツキ液残渣を低減させる方法、あるいは第2の
フオトレジストパターン形成時の紫外線照射時間
を長くしてフオトレジストの重合度を向上させて
フオトレジストの膨潤を低減させる方法が従来か
ら行なわれている。しかし、前者の方法はメツキ
液残渣低減の効果が十分でなく、フオトレジスト
パターン変形の危険が残り、一方後者は生産性を
著しく低下させる等の種々の欠点があつた。 As a method of preventing such deformation of the photoresist pattern, there is a method of cleaning the substrate by immersing it in pure water excited by ultrasonic waves before applying the second photoresist to reduce the plating solution residue, or a method of reducing the plating solution residue. Conventionally, a method has been used in which the degree of polymerization of the photoresist is improved by increasing the ultraviolet irradiation time during the formation of the photoresist pattern, as described in 2, thereby reducing the swelling of the photoresist. However, the former method is not sufficiently effective in reducing the plating solution residue and there remains a risk of deformation of the photoresist pattern, while the latter method has various drawbacks such as a significant decrease in productivity.
本発明は上記の様な欠点を除き、フオトレジス
トパターンの変形を防いで金属突起電極を歩留り
よく形成する方法を提供するものである。本発明
によれば、第2のフオトレジストのパターン変形
は全く発生せず、従つて上記フオトレジストをマ
スクとして形成される金属突起電極形状の変形も
発生しない。 The present invention eliminates the above-mentioned drawbacks and provides a method for forming metal protruding electrodes with a high yield while preventing deformation of a photoresist pattern. According to the present invention, no pattern deformation of the second photoresist occurs, and therefore no deformation occurs in the shape of the metal protrusion electrode formed using the photoresist as a mask.
すなわち本発明の特徴は、半導体基板上に第1
のフオトレジストパターンを形成する工程と、該
第1のフオトレジストパターンをマスクとして第
1の金メツキにより金層の配線を形成する工程
と、次に該半導体基板を純水中に浸漬して洗浄
し、乾燥した後にプラズマ灰化法により該第1の
フオトレジストを除去する工程と、次に該半導体
基板を回転させながら該基板の表面にキシレンの
溶剤を噴霧した後、乾燥させる工程と、然る後に
第2のフオトレジストパターンを形成する工程
と、次に該第2のフオトレジストパターンをマス
クとして第2の金メツキを行いこれにより前記金
層の配線上に金突起電極を形成する工程とを有す
る半導体装置の製造方法にある。 That is, the feature of the present invention is that the first
forming a first photoresist pattern using the first photoresist pattern as a mask, forming a gold layer wiring by first gold plating, and then cleaning the semiconductor substrate by immersing it in pure water. a step of removing the first photoresist by a plasma ashing method after drying; a step of spraying a xylene solvent onto the surface of the semiconductor substrate while rotating the semiconductor substrate; and a step of drying the substrate. forming a second photoresist pattern, and then performing second gold plating using the second photoresist pattern as a mask, thereby forming a gold protrusion electrode on the wiring of the gold layer. A method of manufacturing a semiconductor device having the following features.
次に、本発明を実施例により説明する。第1図
〜第6図は本発明をテープキヤリヤ式集積回路の
金メツキ配線及び金突起電極の形成に適用した場
合の断面図である。第1図において、一般の方法
で素子を形成済の半導体基板1の上にエツチング
法又はリフトオフ法等でパターニングされた白金
の配線パターン2が設けられている。この基板上
に第1のフオトレジストを被着し、これを通常の
方法で所望の形状にパターン形成してフオトレジ
ストパターン3を形成する(第2図)。この後、
該基板を金メツキ液に浸漬し、基板とメツキ液間
に電流を流して所望の厚さまでメツキ4を行なう
(第3図)。次に該基板を純水中に浸漬して洗浄
し、乾燥した後プラズマ灰化法により第1のフオ
トレジスト3を除去する(第4図)。ここで金メ
ツキ表面には前記洗浄では除去しきれないメツキ
液の薄い残渣41が残つており、このまま第2の
フオトレジストを被着してパターニングを行うと
残渣の存在によりフオトレジストと金メツキ面と
の接着性が悪化し、パターンの変形をおこす。 Next, the present invention will be explained by examples. 1 to 6 are cross-sectional views in the case where the present invention is applied to the formation of gold-plated wiring and gold protrusion electrodes of a tape carrier type integrated circuit. In FIG. 1, a platinum wiring pattern 2 patterned by an etching method or a lift-off method is provided on a semiconductor substrate 1 on which elements have already been formed by a general method. A first photoresist is deposited on this substrate and patterned into a desired shape by a conventional method to form a photoresist pattern 3 (FIG. 2). After this,
The substrate is immersed in a gold plating solution, and a current is passed between the substrate and the plating solution to perform plating 4 to a desired thickness (FIG. 3). Next, the substrate is washed by immersing it in pure water, and after drying, the first photoresist 3 is removed by plasma ashing (FIG. 4). Here, a thin residue 41 of the plating solution that cannot be removed by the cleaning described above remains on the gold plating surface, and if the second photoresist is applied as it is and patterning is performed, the photoresist and the gold plating surface will be separated due to the presence of the residue. The adhesion with the pattern deteriorates and the pattern becomes deformed.
そこで、本発明においては第2のフオトレジス
ト被着に先立ち、該基板表面を有機溶液で洗浄す
る。すなわち、該基板を回転しながらキシレン等
の溶剤を噴霧した後、乾燥させる。これにより第
1の金メツキ4上のメツキ液残渣41は完全に除
去される。然る後に第2のフオトレジストを被着
し、露光・現像処理を行つて所望のフオトレジス
トパターンを形成する。然る後に該基板を通常の
方法で金メツキを行なつて金突起電極6を形成し
(第5図)、さらにフオトレジストを全部除去すれ
ば所望の形状の金配線及び金突起電極を形成する
ことができる(第6図)。 Therefore, in the present invention, the surface of the substrate is cleaned with an organic solution prior to depositing the second photoresist. That is, a solvent such as xylene is sprayed on the substrate while it is being rotated, and then it is dried. As a result, the plating solution residue 41 on the first gold plating 4 is completely removed. Thereafter, a second photoresist is applied and exposed and developed to form a desired photoresist pattern. Thereafter, gold plating is performed on the substrate in a conventional manner to form gold protruding electrodes 6 (FIG. 5), and further, by removing all of the photoresist, gold wiring and gold protruding electrodes of the desired shape are formed. (Figure 6).
以上、説明した様に本発明によればメツキ配線
及びメツキ電極を有する半導体装置を歩留りよ
く、かつ生産性高く製造することができる。 As described above, according to the present invention, a semiconductor device having plated wiring and plated electrodes can be manufactured with high yield and productivity.
第1図乃至第6図は本発明の実施例を製造工程
順に示した断面図である。
尚、図において、1……素子を形成済の半導体
基板、2……リフトオフ法等で形成された基板1
上の白金配線パターン、3……所望の形状にパタ
ーニングされた第1のフオトレジスト、4……第
1のメツキ、41……第1のメツキ上に残留した
メツキ液の残渣、5……所望の形状にパターニン
グされた第2のフオトレジスト、6……第2のメ
ツキにより形成された金突起電極である。
FIGS. 1 to 6 are cross-sectional views showing embodiments of the present invention in the order of manufacturing steps. In the figure, 1...a semiconductor substrate on which elements have been formed, 2...a substrate 1 formed by a lift-off method, etc.
Upper platinum wiring pattern, 3... First photoresist patterned into desired shape, 4... First plating, 41... Residue of plating solution remaining on first plating, 5... Desired. A second photoresist patterned in the shape of 6... is a gold protrusion electrode formed by second plating.
Claims (1)
形成する工程と、前記金属膜による配線パターン
が露出するように半導体基板上に第1のフオトレ
ジストパターンを形成する工程と、該第1のフオ
トレジストパターンをマスクとして第1の金メツ
キにより金層の配線を前記金属膜による配線パタ
ーン上に形成する工程と、次に該半導体基板を純
水中に浸漬して洗浄し、乾燥した後にプラズマ灰
化法により該第1のフオトレジストを除去する工
程と、次に該半導体基板を回転させながら該基板
の表面にキシレンの溶剤を噴霧した後、乾燥させ
る工程と、然る後に第2のフオトレジストパター
ンを形成する工程と、次に該第2のフオトレジス
トパターンをマスクとして第2の金メツキを行い
これにより前記金層の配線上に金突起電極を形成
する工程とを有することを特徴とする半導体装置
の製造方法。1. A step of forming a wiring pattern of a metal film on a semiconductor substrate, a step of forming a first photoresist pattern on the semiconductor substrate so that the wiring pattern of the metal film is exposed, and the first photoresist pattern. A step of forming a gold layer wiring on the wiring pattern of the metal film by first gold plating using as a mask, and then cleaning the semiconductor substrate by immersing it in pure water, drying it, and then applying a plasma ashing method. a step of removing the first photoresist pattern, a step of spraying a xylene solvent onto the surface of the semiconductor substrate while rotating the semiconductor substrate, and then drying it; and then performing second gold plating using the second photoresist pattern as a mask, thereby forming a gold protrusion electrode on the wiring of the gold layer. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57164465A JPS5954246A (en) | 1982-09-21 | 1982-09-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57164465A JPS5954246A (en) | 1982-09-21 | 1982-09-21 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5954246A JPS5954246A (en) | 1984-03-29 |
| JPS6357942B2 true JPS6357942B2 (en) | 1988-11-14 |
Family
ID=15793689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57164465A Granted JPS5954246A (en) | 1982-09-21 | 1982-09-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5954246A (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5239808B2 (en) * | 1973-07-31 | 1977-10-07 | ||
| JPS57113260A (en) * | 1980-12-29 | 1982-07-14 | Nec Corp | Manufacture of semiconductor device |
-
1982
- 1982-09-21 JP JP57164465A patent/JPS5954246A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5954246A (en) | 1984-03-29 |
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