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JPH0584063B2 - - Google Patents
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JPH0584063B2 - - Google Patents

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Publication number
JPH0584063B2
JPH0584063B2 JP59037069A JP3706984A JPH0584063B2 JP H0584063 B2 JPH0584063 B2 JP H0584063B2 JP 59037069 A JP59037069 A JP 59037069A JP 3706984 A JP3706984 A JP 3706984A JP H0584063 B2 JPH0584063 B2 JP H0584063B2
Authority
JP
Japan
Prior art keywords
insulating film
abrasive grains
wiring metal
inorganic insulating
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59037069A
Other languages
Japanese (ja)
Other versions
JPS60180144A (en
Inventor
Yoshinori Teto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kansai Nippon Electric Co Ltd
Original Assignee
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kansai Nippon Electric Co Ltd filed Critical Kansai Nippon Electric Co Ltd
Priority to JP3706984A priority Critical patent/JPS60180144A/en
Publication of JPS60180144A publication Critical patent/JPS60180144A/en
Publication of JPH0584063B2 publication Critical patent/JPH0584063B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 イ 産業上の利用分野 この発明はトランジスタやICなどの半導体素
子の製造方法に関し、特に、半導体素子形成基板
表面にアルミニウム蒸着等で形成する配線パター
ンの下地加工技術に関する。
DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a method for manufacturing semiconductor elements such as transistors and ICs, and more particularly to a technique for forming a base for a wiring pattern formed by aluminum vapor deposition or the like on the surface of a semiconductor element forming substrate.

ロ 従来技術 トランジスタやICなどの半導体素子の表面に
形成される配線パターンは一般にSiO2やSi3N4
絶縁膜を下地に形成され、そのパターンの形状は
益々複雑化、高密度化される傾向にあつて、下地
との密着強度が最近益々重要視されている。
B. Prior art Wiring patterns formed on the surface of semiconductor elements such as transistors and ICs are generally formed on an insulating film of SiO 2 or Si 3 N 4 as a base, and the shape of the pattern becomes increasingly complex and dense. In line with this trend, the strength of adhesion to the substrate has recently become more and more important.

上記パターン化された配線金属の形態例を第1
図に示すと、1はシリコンの半導体基板、2は半
導体基板1上に形成されたSiO2又はSi3N4の無機
絶縁膜(以下、単に絶縁膜という)、3は絶縁膜
2にPR法にて窓開けして形成した窓孔、4は窓
孔3から露出する半導体基板1のシリコン素地m
と絶縁膜2の表面n上に所望パターンで被着形成
した薄膜状の配線金属(パターン)で、通常Al
の蒸着かスパツタ(リング)にて形成される。こ
の配線金属4までの製造工程を第2図乃至第6図
を参照して述べると、先ず第2図に示すように半
導体基板1上の全面に形成された絶縁膜2上にレ
ジスト5を塗布する。次にレジスト5を選択露光
してから、現像して第3図に示すようにレジスト
5の所望部分に窓孔6を形成する。次に窓孔6か
ら露出する絶縁膜2をエツチング除去して絶縁膜
2に窓孔6を形成してから第5図に示すようにレ
ジスト5を除去する。この第2図乃至第5図の
PR工程が完了した後、必要時に半導体基板1の
露出素地mと絶縁膜2上の全面に例えばAl蒸着
にて第6図に示すAl蒸着膜4′を形成し、而る後
Al蒸着膜4′を上述と同様なPR法にて所定パタ
ーンを選択除去して第1図の配線金属4を得る。
The first example of the form of the patterned wiring metal is
As shown in the figure, 1 is a silicon semiconductor substrate, 2 is an inorganic insulating film of SiO 2 or Si 3 N 4 (hereinafter simply referred to as an insulating film) formed on the semiconductor substrate 1, and 3 is an insulating film 2 coated with a PR method. 4 is the silicon substrate m of the semiconductor substrate 1 exposed from the window hole 3.
A thin film wiring metal (pattern) formed on the surface n of the insulating film 2 in a desired pattern, usually made of Al
It is formed by vapor deposition or sputtering (ring). The manufacturing process up to the wiring metal 4 will be described with reference to FIGS. 2 to 6. First, as shown in FIG. do. Next, the resist 5 is selectively exposed and then developed to form a window 6 in a desired portion of the resist 5 as shown in FIG. Next, the insulating film 2 exposed through the window hole 6 is removed by etching to form a window hole 6 in the insulating film 2, and then the resist 5 is removed as shown in FIG. These figures 2 to 5
After the PR process is completed, if necessary, an Al vapor deposition film 4' shown in FIG. 6 is formed on the entire surface of the exposed substrate m of the semiconductor substrate 1 and the insulating film 2 by, for example, Al vapor deposition, and then
A predetermined pattern is selectively removed from the Al vapor deposited film 4' using the same PR method as described above to obtain the wiring metal 4 shown in FIG.

ハ 発明が解決しようとする問題点 このように配線金属4の下地の大部分はSiO2
やSi3N4の絶縁膜2であり、残りの下地は半導体
素子の各種電極面として形成されたシリコン素地
mであつて、シリコン素地mにはAl蒸着後のア
ニール処理(熱処理)にて合金化されて密着性良
く形成される。ところが絶縁膜2上の配線金属4
は絶縁膜2の表面nの汚れ等の影響で密着性が悪
く、PCT(高温高圧下での通電テスト)やHBT
(高温下でバイアスをかけるテスト)などの各種
信頼性試験時や通常の動作時に配線金属4が下地
の絶縁膜2から部分的に剥がれて浮き上がり、後
断線事故や隣接するものとシヨートする事故を招
き、半導体装置の信頼性を悪くする1つの要因に
なつていた。このような配線金属剥がれは下地の
絶縁膜2がSi3N4で配線金属4がAlの場合に特に
多く、また配線パターンの高密度化に伴つて益々
増加する傾向にあつて、早急な改善策が要望され
ていた。
C. Problems to be solved by the invention In this way, most of the base of the wiring metal 4 is SiO 2
or Si 3 N 4 insulating film 2, and the remaining base is a silicon base m formed as various electrode surfaces of semiconductor elements. formed with good adhesion. However, the wiring metal 4 on the insulating film 2
The adhesion is poor due to dirt on the surface of the insulating film 2, and PCT (current conduction test under high temperature and pressure) and HBT
During various reliability tests such as (tests in which bias is applied under high temperature) or during normal operation, the wiring metal 4 may partially peel off from the underlying insulating film 2 and lift up, causing accidents such as subsequent disconnection or accidents where the wiring metal 4 shoots into adjacent objects. This has become a factor that deteriorates the reliability of semiconductor devices. Such peeling of wiring metal is particularly common when the underlying insulating film 2 is Si 3 N 4 and the wiring metal 4 is Al, and it tends to increase more and more as wiring patterns become denser, so immediate improvement is required. Measures were required.

尚、絶縁膜2と配線金属4の密着性を良くする
手段として、絶縁膜2の表面nをプラズマエツチ
ングにより活性化してからAl蒸着する方法があ
るが、この方法は、高価な設備を必要とし、また
表面nの活性化だけは効果が不十分で実用的でな
かつた。
As a means of improving the adhesion between the insulating film 2 and the wiring metal 4, there is a method of activating the surface n of the insulating film 2 by plasma etching and then depositing Al, but this method requires expensive equipment. , and activation of surface n alone was insufficiently effective and impractical.

ニ 発明の構成 本発明は上記問題点を解決するために、半導体
基板上の絶縁膜をPR法で窓開けする前に絶縁膜
表面を絶縁膜とは被エツチング特性の異なる砥粒
によるホーニング加工によつて粗面化する工程
と、絶縁膜上に付着した前記砥粒を薬液にて溶か
し除去する工程を加えた製造方法を提供する。前
記砥粒は粒径が1μm以下の超微細なものが適して
いて、また前記薬液は砥粒を溶かすが、絶縁膜は
溶かさないものが選択される。
D. Structure of the Invention In order to solve the above-mentioned problems, the present invention provides that, before opening an insulating film on a semiconductor substrate using the PR method, the surface of the insulating film is subjected to a honing process using abrasive grains having etching properties different from those of the insulating film. Therefore, a manufacturing method is provided which includes a step of roughening the surface and a step of dissolving and removing the abrasive grains adhering to the insulating film with a chemical solution. The abrasive grains are suitably ultra-fine ones with a grain size of 1 μm or less, and the chemical solution is selected to dissolve the abrasive grains but not the insulating film.

ホ 発明の実施例 本発明の具体的実施例を第7図乃至第13図を
参照して順次説明する。
E. Embodiments of the Invention Specific embodiments of the present invention will be sequentially described with reference to FIGS. 7 to 13.

本発明のホーニング加工工程は、先ず第7図に
示すように、半導体基板1上全面に形成された絶
縁膜2の表面nに相対移動するノズル7から噴射
される金属微粉体の砥粒8を吹き付けて表面nを
順次に粗面化する。砥粒8はFeやCuなどの金属
蒸気を急速冷却で粒径が1μm以下の粉体に凝固さ
せる等の製法で製造された市販品を使用すればよ
い。この砥粒8が吹き付けで絶縁膜2は表層部が
凹凸に削られて粗面n′となる。この粗面n′の粗度
は砥粒8の量、吹き付け速度、吹き付け時間にて
様々にコントロールされる。粗面処理が完了する
と、絶縁膜2上には砥粒8が付着して残つている
ので、これを除去する。この除去は単なるエアー
ブローでは不十分であるので、砥粒8が金属であ
ることを利用して第8図に示すように半導体基板
1の全体を次の薬液9内に浸漬して付着した砥粒
8を溶解させる。薬液9は砥粒8のみを溶解させ
るもので、例えば絶縁膜2がSiO2で砥粒8がAl
の場合はリン酸溶液が、絶縁膜2がSi3N4で砥粒
8がCuの場合は弗酸溶液が有効である。この薬
液9による砥粒洗浄が完了すると半導体基板全体
を水洗して乾燥させ、後は従来同様にPR工程、
配線パターン作成工程を行う。
In the honing process of the present invention, first, as shown in FIG. 7, abrasive grains 8 of fine metal powder are injected from a relatively moving nozzle 7 onto the surface n of the insulating film 2 formed over the entire surface of the semiconductor substrate 1. The surface n is sequentially roughened by spraying. The abrasive grains 8 may be commercially available products manufactured by a method such as rapid cooling of metal vapor such as Fe or Cu to solidify it into a powder having a particle size of 1 μm or less. By spraying the abrasive grains 8, the surface layer of the insulating film 2 is scraped into irregularities to form a rough surface n'. The roughness of this rough surface n' is variously controlled by the amount of abrasive grains 8, spraying speed, and spraying time. When the surface roughening treatment is completed, the abrasive grains 8 remaining attached to the insulating film 2 are removed. Since mere air blowing is not sufficient for this removal, the entire semiconductor substrate 1 is immersed in the next chemical solution 9 as shown in FIG. 8 to remove the attached abrasive particles, as shown in FIG. Dissolve grain 8. The chemical solution 9 dissolves only the abrasive grains 8. For example, the insulating film 2 is SiO 2 and the abrasive grains 8 are Al.
In this case, a phosphoric acid solution is effective, and in a case where the insulating film 2 is made of Si 3 N 4 and the abrasive grains 8 are made of Cu, a hydrofluoric acid solution is effective. When the abrasive cleaning with the chemical solution 9 is completed, the entire semiconductor substrate is washed with water and dried, and then the PR process is carried out as in the conventional method.
Perform the wiring pattern creation process.

即ち、先ず第9図に示すように絶縁膜2上全面
にレジスト5を塗布してから、レジスト5に選択
露光、現像を行つて第10図に示すように窓孔6
を形成し、その後窓孔6から絶縁膜2をエツチン
グして第11図に示すように絶縁膜2に窓孔3を
形成する。このPR工程において、レジスト5は
絶縁膜2の粗面n′上に形成されるので両者の密着
性は粗面処理をしない従来品よりも強固となり、
従つて第11図のエツチング時にエツチング液が
絶縁膜2とレジスト5の間に侵入する確率が低く
なり、窓孔3の寸法精度がより高精度となる。
That is, first, as shown in FIG. 9, a resist 5 is applied to the entire surface of the insulating film 2, and then the resist 5 is selectively exposed and developed to form window holes 6 as shown in FIG.
After that, the insulating film 2 is etched from the window hole 6 to form a window hole 3 in the insulating film 2 as shown in FIG. In this PR process, the resist 5 is formed on the rough surface n' of the insulating film 2, so the adhesion between the two is stronger than that of conventional products without surface roughening.
Therefore, the probability that the etching solution will enter between the insulating film 2 and the resist 5 during the etching shown in FIG. 11 is reduced, and the dimensional accuracy of the window hole 3 becomes higher.

PR工程が完了すると絶縁膜2上からレジスト
5を除去し、次に第12図に示すように絶縁膜2
上と窓孔3から露出する半導体基板1上の全面に
例えばAl蒸着膜4′を形成する。そしてAl蒸着膜
4′をPR法で選択除去して第13図に示すように
所望の配線金属4を形成する。この配線金属4の
絶縁膜2上の密着性は粗面n′上に形成されるため
従来品より強固となる。特に配線金属4をAl蒸
着で形成すれば蒸着時のAl粒子がその高エネル
ギーでもつて粗面n′に食い入る如く付着してより
強固な密着性が得られる。実際、このように粗面
化した絶縁膜2上に配線金属4を形成すると、信
頼性試験等で配線金属4が剥がれて浮き上がるト
ラブルはほとんど皆無に近くなり、本発明の有効
性が実証された。
When the PR process is completed, the resist 5 is removed from the insulating film 2, and then the insulating film 2 is removed as shown in FIG.
For example, an Al vapor deposited film 4' is formed on the entire surface of the semiconductor substrate 1 exposed from the top and the window hole 3. Then, the Al vapor deposited film 4' is selectively removed by the PR method to form a desired wiring metal 4 as shown in FIG. The adhesion of the wiring metal 4 to the insulating film 2 is stronger than that of conventional products because it is formed on the rough surface n'. In particular, if the wiring metal 4 is formed by Al evaporation, the Al particles during evaporation will stick to the rough surface n' even with their high energy, resulting in stronger adhesion. In fact, when the wiring metal 4 is formed on the insulating film 2 whose surface has been roughened in this way, there is almost no problem of the wiring metal 4 peeling off and floating during reliability tests, etc., proving the effectiveness of the present invention. .

尚、本発明と同目的で蒸気金属微粉体の砥粒8
の代わりに、物の粗面化に通常用いられているア
ルミナなどの粒径が10μm程度の無機質砥粒を用
いることも考えられられる。しかし、この後者砥
粒では粒径が大き過ぎて絶縁膜2が破れる可能性
が大となり、また後の除去作業が大変で且つ完全
な除去が難しくて好ましくない。
Incidentally, for the same purpose as the present invention, vapor metal fine powder abrasive grains 8
Instead, it is also possible to use inorganic abrasive grains with a particle size of about 10 μm, such as alumina, which is commonly used to roughen the surface of objects. However, the latter abrasive grains are undesirable because their grain size is too large, increasing the possibility that the insulating film 2 will be torn, making subsequent removal work difficult, and making complete removal difficult.

ニ 発明の効果 以上のように、本発明によれば配線金属の下地
との密着性が一段と向上するので、配線金属の浮
き上がりによる断線、シヨート等のトラブルが減
少し、半導体製造の歩留まり向上、品質改善が図
れる。
D. Effects of the Invention As described above, according to the present invention, the adhesion of the wiring metal to the underlying layer is further improved, so troubles such as wire breakage and shoots due to lifting of the wiring metal are reduced, and the yield of semiconductor manufacturing is improved and quality is improved. Improvements can be made.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は半導体素子の部分断面斜視図、第2図
乃至第6図は第1図の半導体素子の従来製法を説
明するための各工程での部分拡大断面図、第7図
乃至第13図は第1図の半導体素子の本発明方法
による各製造工程での部分拡大断面図である。 1……半導体基板、2……絶縁膜、4……配線
金属、8……砥粒、n′……粗面。
FIG. 1 is a partial cross-sectional perspective view of a semiconductor device, FIGS. 2 to 6 are partial enlarged cross-sectional views of each process for explaining the conventional manufacturing method of the semiconductor device in FIG. 1, and FIGS. 7 to 13. 2A and 2B are partially enlarged cross-sectional views of the semiconductor device shown in FIG. 1 at various manufacturing steps according to the method of the present invention. 1... Semiconductor substrate, 2... Insulating film, 4... Wiring metal, 8... Abrasive grain, n'... Rough surface.

Claims (1)

【特許請求の範囲】 1 半導体基板上に無機絶縁膜表面をそれとは被
エツチング特性の異なる砥粒によるホーニング加
工で粗面化する工程、前記無機絶縁膜上に付着し
た砥粒を薬液にて溶かし除去する工程と、前記無
機絶縁膜上に配線金属を所定のパターンで選択的
に形成する工程を含むことを特徴とする半導体素
子製造方法。 2 前記砥粒が金属微粉体である特許請求の範囲
第1項記載の半導体素子製造方法。
[Scope of Claims] 1. A step of roughening the surface of an inorganic insulating film on a semiconductor substrate by honing using abrasive grains having different etching characteristics from that of the inorganic insulating film, and dissolving the abrasive grains attached to the inorganic insulating film with a chemical solution. A method for manufacturing a semiconductor device, comprising a step of removing the inorganic insulating film, and a step of selectively forming a wiring metal in a predetermined pattern on the inorganic insulating film. 2. The semiconductor device manufacturing method according to claim 1, wherein the abrasive grains are metal fine powder.
JP3706984A 1984-02-27 1984-02-27 Manufacture of semiconductor element Granted JPS60180144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3706984A JPS60180144A (en) 1984-02-27 1984-02-27 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3706984A JPS60180144A (en) 1984-02-27 1984-02-27 Manufacture of semiconductor element

Publications (2)

Publication Number Publication Date
JPS60180144A JPS60180144A (en) 1985-09-13
JPH0584063B2 true JPH0584063B2 (en) 1993-11-30

Family

ID=12487257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3706984A Granted JPS60180144A (en) 1984-02-27 1984-02-27 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS60180144A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0789551B2 (en) * 1986-02-13 1995-09-27 日本電気株式会社 Semiconductor device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5139836B2 (en) * 1971-12-13 1976-10-29
JPS5187578A (en) * 1975-01-30 1976-07-31 Matsushita Electric Works Ltd KAGAKUMETSUKYOKIBANNO SEIHO

Also Published As

Publication number Publication date
JPS60180144A (en) 1985-09-13

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