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JPS6358368B2 - - Google Patents
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JPS6358368B2 - - Google Patents

Info

Publication number
JPS6358368B2
JPS6358368B2 JP54090992A JP9099279A JPS6358368B2 JP S6358368 B2 JPS6358368 B2 JP S6358368B2 JP 54090992 A JP54090992 A JP 54090992A JP 9099279 A JP9099279 A JP 9099279A JP S6358368 B2 JPS6358368 B2 JP S6358368B2
Authority
JP
Japan
Prior art keywords
sintered body
support
silicon
silicon carbide
silicon dioxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54090992A
Other languages
Japanese (ja)
Other versions
JPS5615047A (en
Inventor
Yasutoshi Kurihara
Komei Yatsuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9099279A priority Critical patent/JPS5615047A/en
Publication of JPS5615047A publication Critical patent/JPS5615047A/en
Publication of JPS6358368B2 publication Critical patent/JPS6358368B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07331Connecting techniques
    • H10W72/07337Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)

Description

【発明の詳細な説明】 本発明は新規な混成集積回路装置に関する。[Detailed description of the invention] The present invention relates to a novel hybrid integrated circuit device.

半導体装置の一例である高出力トランジスタで
は、数アンペア以上のコレクタ電流が流れるが、
この際半導体素子としてのトランジスタペレツト
の内部における発熱を伴なう。この発熱に起因す
る特性の不安定性や寿命の加速的劣化を避けるた
め、トランジスタペレツトが許容制限温度を越え
て昇温するのを防止する方法がとられている。
In a high-output transistor, which is an example of a semiconductor device, a collector current of several amperes or more flows.
At this time, heat is generated inside the transistor pellet as a semiconductor element. In order to avoid instability of characteristics and accelerated deterioration of lifetime due to this heat generation, methods are used to prevent the temperature of the transistor pellet from rising beyond the permissible limit temperature.

温度上昇を防ぐ方法の1つとして、従来、トラ
ンジスタペレツトの支持体としてのステムを放熱
器に取付け、トランジスタペレツトで発生した熱
をステムや放熱器を介して外部へ放出させる方法
がとられてきた。
One method to prevent temperature rise has traditionally been to attach the stem, which serves as a support for the transistor pellet, to a radiator, and to release the heat generated by the transistor pellet to the outside via the stem and the radiator. It's here.

しかしながら、高出力トランジスタの場合は、
上述したように大きなコレクタ電流を流すため、
その電流路を確保することや効率的に熱放散させ
る必要から、コレクタ領域が直接ステムに固着さ
れるようにトランジスタペレツトを載置しなけれ
ばならない。ところで、この種のトランジスタは
通常エミツタまたはベース接地にして使用される
ため、コレクタ端子即ちステムは多くの場合接地
状態におかれる放熱器(またはシヤーシ)などに
直接取付けることができない。
However, for high power transistors,
As mentioned above, in order to flow a large collector current,
In order to secure the current path and to efficiently dissipate heat, the transistor pellet must be mounted so that the collector region is directly fixed to the stem. By the way, since this type of transistor is usually used with the emitter or base grounded, the collector terminal or stem cannot be directly attached to a heat sink (or chassis) etc. which is often grounded.

このため、通常はステムと放熱器との間に例え
ばマイカまたはテレフタル酸ポリエステル(マイ
ラ)などの絶縁板をはさんで電気的に絶縁し、か
つステム−絶縁板間および絶縁板−放熱器間に空
隙を埋めて放熱を助けるためのグリースを介在さ
せ、さらにその上に、ステムと放熱器とを絶縁ワ
ツシヤを介するネジ締めによつて固定していた。
しかしこの場合でも、コレクタ領域がステムに電
気的に接続されている(ステムを接地状態にでき
ない)ため、このままでは電磁波妨害による雑音
の影響を避けることは困難であつた。
For this reason, usually an insulating plate such as mica or polyester terephthalate (Mylar) is sandwiched between the stem and the heatsink to provide electrical insulation, and between the stem and the insulating plate and between the insulating plate and the heatsink. Grease was interposed to fill the gaps and aid heat radiation, and the stem and heat radiator were further fixed on top of this by screwing through insulating washers.
However, even in this case, since the collector region is electrically connected to the stem (the stem cannot be grounded), it is difficult to avoid the effects of noise due to electromagnetic interference.

一方、電気絶縁、効率的な放熱散および電磁波
妨害防止をはかる試みとして、金属支持体上にベ
リリヤ磁器やアルミナ磁器を介して半導体素子を
載置した例がある。しかしながら、ベリリヤ磁器
を用いた場合は、 (1) ベリリヤ自体強い毒性を有しているため、そ
の取扱いに厳重な注意を要し、しかも入手困難
で高価である。
On the other hand, as an attempt to achieve electrical insulation, efficient heat dissipation, and prevention of electromagnetic interference, there are examples in which a semiconductor element is mounted on a metal support via beryllia porcelain or alumina porcelain. However, when using beryllia porcelain, (1) beryllium itself is highly toxic, so strict care must be taken when handling it, and it is difficult to obtain and expensive.

(2) ベリリヤ磁器の熱膨張係数は、7.6×10-6
℃とシリコンのそれ(〜3×10-6/℃)に比べ
て差があるため、半導体素子とベリリヤ磁器間
接合部に熱疲労を生じやすく、両者間の強固な
一体化が困難である。
(2) The thermal expansion coefficient of Beryliya porcelain is 7.6×10 -6 /
Since there is a difference between the temperature and that of silicon (~3×10 -6 /°C), thermal fatigue is likely to occur at the junction between the semiconductor element and the beryllium ceramic, making it difficult to firmly integrate the two.

(3) 接合部の熱疲労を緩和するには、モリブデン
(5.2×10-6/℃)やタングステン(4.3×10-6
℃)などのスペーサを絶縁板に加えて介在させ
る必要があるが、この場合は熱放散上不利にな
るほか、一体化に要する部品点数や処理工数の
面で経済的に不利である。
(3) Molybdenum (5.2×10 -6 /℃) and tungsten (4.3×10 -6 /℃) can be used to alleviate thermal fatigue at the joint.
It is necessary to interpose a spacer such as (°C) in addition to the insulating plate, but in this case, it is not only disadvantageous in terms of heat dissipation, but also economically disadvantageous in terms of the number of parts and processing steps required for integration.

などの問題点が残る。また、モリブデンやタング
ステンは重い金属である(モリブデンの比重
10.27、タングステンの比重19.3)ことから半導
体装置が志向する軽量化の方向に十分沿いきれな
い面がある。一方、アルミナ磁器を用いた場合で
も、毒性の問題を除いては前述した(1)、(2)と同様
の問題を伴なう。
Other problems remain. Also, molybdenum and tungsten are heavy metals (the specific gravity of molybdenum is
10.27, and the specific gravity of tungsten is 19.3), which means that it cannot fully comply with the direction of weight reduction that semiconductor devices are aiming for. On the other hand, even when alumina porcelain is used, problems similar to those described in (1) and (2) above arise, except for the problem of toxicity.

以上、トランジスタを用いた従来のパワー用混
成集積回路装置の欠点を説明したが、トランジス
タに限らず、ダイオードやサイリスタなど他の集
積回路装置においても同様の問題点を残してい
た。
Although the drawbacks of conventional power hybrid integrated circuit devices using transistors have been described above, similar problems remain not only in transistors but also in other integrated circuit devices such as diodes and thyristors.

本発明は前述の欠点を改め、半導体素子と支持
体との間の優れた電気絶縁、効率的な熱放散、電
磁波妨害による雑音防止、半導体素子の強固な接
合および軽量化が可能な混成集積回路装置を提供
することを目的とする。
The present invention corrects the above-mentioned drawbacks and provides a hybrid integrated circuit that provides excellent electrical insulation between the semiconductor element and the support, efficient heat dissipation, noise prevention due to electromagnetic interference, strong bonding of the semiconductor element, and light weight. The purpose is to provide equipment.

本発明は、金属製支持体、該金属製支持体上に
固着された絶縁担体および該担体上に金属層によ
つて載置固定された少なくとも2個の半導体回路
素子を備えた装置において、前記絶縁担体は炭化
ケイ素焼結体からなり、前記回路素子を搭載した
焼結体表面に二酸化ケイ素薄膜が形成されてお
り、前記二酸化ケイ素薄膜は前記支持体と前記素
子との間の絶縁耐圧が2000V以上となる厚さを有
することを特徴とする混成集積回路装置にある。
The present invention provides an apparatus comprising a metal support, an insulating carrier fixed on the metal support, and at least two semiconductor circuit elements placed and fixed on the carrier by a metal layer. The insulating carrier is made of a silicon carbide sintered body, and a silicon dioxide thin film is formed on the surface of the sintered body on which the circuit element is mounted, and the silicon dioxide thin film has a dielectric strength of 2000 V between the support body and the element. A hybrid integrated circuit device is characterized in that it has a thickness equal to or greater than the above.

即ち、本発明は、炭化ケイ素(相対密度98〜
100%)が曲げ強度〜100Kg/mm2(室温)、ビツカ
ース硬度(300g)3700〜4000、熱膨張係数(室
温〜900℃)4×10-6/℃、熱拡散率(室温)
0.229cm2/s、熱伝導率(室温)0.18cal/cm・
s・℃、比重3.17なる物性を示し、これらの性質
のうち、とくに熱膨張係数がシリコンに近接して
いるため、接着部の熱疲労を生じない強固な一体
化が可能となり、熱伝導率がアルミナ磁気とほぼ
同等のため熱放散が効率よくなされ、しかも機械
的に堅牢であり、そして炭化ケイ素自体軽量であ
ることに加えて、モリブデンやタングステンなど
の重い金属をスペーサとして介す必要がないこと
など、半導体素子と支持体間の絶縁板用母体とし
て好ましい性質を兼ね備えていることに着目し、
実地に適用してその有効性を確認した結果なされ
たものである。
That is, the present invention uses silicon carbide (relative density 98~
100%) is bending strength ~100Kg/ mm2 (room temperature), Vickers hardness (300g) 3700~4000, coefficient of thermal expansion (room temperature ~ 900℃) 4 x 10 -6 /℃, thermal diffusivity (room temperature)
0.229cm 2 /s, thermal conductivity (room temperature) 0.18cal/cm・
It exhibits physical properties of s・℃ and specific gravity of 3.17, and among these properties, the coefficient of thermal expansion is particularly close to that of silicon, which allows for strong integration without causing thermal fatigue at the bonded part, and the thermal conductivity is low. Heat dissipation is efficient because it is almost equivalent to alumina magnetism, and it is mechanically robust.In addition to silicon carbide itself being lightweight, there is no need to use heavy metals such as molybdenum or tungsten as spacers. Focusing on the fact that it has desirable properties as a matrix for an insulating plate between a semiconductor element and a support,
This was done after confirming its effectiveness through practical application.

前述の目的に適合した絶縁板を得るためには、
炭化ケイ素粉末成形物を真空中で加圧しながら焼
結させたものが好ましい。そして電気絶縁を担う
二酸化ケイ素薄膜は、炭化ケイ素焼結体を熱酸化
法で形成したものでよいが、必要ならば炭化ケイ
素焼結体上に直接スパツタリング法、CVD
(Chemical Vapor Deposition)法などによつて
形成させてもよい。
In order to obtain an insulating board suitable for the aforementioned purpose,
Preferably, a silicon carbide powder molded product is sintered under pressure in a vacuum. The silicon dioxide thin film responsible for electrical insulation may be formed by thermally oxidizing a silicon carbide sintered body, but if necessary, it may be formed by direct sputtering or CVD on the silicon carbide sintered body.
(Chemical Vapor Deposition) method or the like.

以下に、本発明を実施例により詳細に説明す
る。
The present invention will be explained in detail below using examples.

実施例 1 本実施例における半導体装置は、第1図に示す
ように、半導体素子としてのシリコンダイオード
ペレツト41,41′を4個、炭化ケイ素焼結体
42上に熱酸化によつて厚さ約1.5μmの二酸化ケ
イ素薄膜43を設けた絶縁担体およびその上に設
けたアルミニウム層44を介して銅支持体45上
に一体化し、各々のダイオードペレツトにリード
線46,46′を取付けるとともにアルミニウム
層44にもリード線47を設け、4個のダイオー
ドがそれぞれ整流回路の一部を担うように電気接
続し、そして少くともシリコンダイオードペレツ
ト41,41′が外気から遮断されるようにレジ
ンモールドした混成集積回路装置である。レジン
モールドについては図示せず。シリコンペレツト
と絶縁担体及び絶縁担体と銅支持体との接合はシ
リコンペレツト及び絶縁担体の接合面にいずれも
メタライズ層を形成し、各々はんだによつて接合
した。
Example 1 As shown in FIG. 1, a semiconductor device in this example includes four silicon diode pellets 41, 41' as semiconductor elements, which are formed on a silicon carbide sintered body 42 by thermal oxidation. The diode pellets are integrated on a copper support 45 via an insulating carrier provided with a silicon dioxide thin film 43 of approximately 1.5 μm and an aluminum layer 44 provided thereon, and lead wires 46, 46' are attached to each diode pellet. A lead wire 47 is also provided on the layer 44, and the four diodes are electrically connected so that they each play a part of the rectifier circuit, and a resin mold is formed so that at least the silicon diode pellets 41 and 41' are isolated from the outside air. It is a hybrid integrated circuit device. The resin mold is not shown. The silicon pellets and the insulating carrier and the insulating carrier and the copper support were bonded by forming metallized layers on the bonding surfaces of the silicon pellets and the insulating carrier, and by soldering.

このような構成で得られた本実施例の混成集積
回路装置の銅リード線46−銅支持体45間の絶
縁耐圧は2000V以上が得られ、トランジスタペレ
ツト−銅支持体間の熱抵抗は1℃/W以下が得ら
れた。また電磁波妨害による雑音はトランジスタ
ペレツト−銅支持体間を電気絶縁しない場合より
約30dB小さくなつた。そしてトランジスタペレ
ツトに常温−125℃間の熱変化を1000回与えた後
でも、トランジスタペレツト41,41′−炭化
ケイ素焼結体42間の一体化部には何等の異常も
見出されなかつた。
In the hybrid integrated circuit device of this example obtained with such a configuration, the dielectric strength voltage between the copper lead wire 46 and the copper support 45 is 2000 V or more, and the thermal resistance between the transistor pellet and the copper support is 1. C/W or less was obtained. Furthermore, the noise due to electromagnetic interference was approximately 30 dB lower than when there was no electrical insulation between the transistor pellet and the copper support. Even after the transistor pellets were subjected to thermal changes between room temperature and 125°C 1000 times, no abnormality was found in the integrated portion between the transistor pellets 41, 41' and the silicon carbide sintered body 42. Ta.

このように高い絶縁耐圧が得られたのは高い絶
縁抵抗を有する二酸化ケイ素薄膜43でトランジ
スタペレツト41,41′炭化ケイ素焼結体42
間を絶縁しているためである。熱抵抗が小さいの
は二酸化ケイ素薄膜43を極めて薄く形成すると
ともに熱伝導性のよい炭化ケイ素焼結体42で放
熱を助ける構成になつていることに起因する。ま
た雑音を低減できたのは、銅支持体45がトラン
ジスタペレツト41,41′から電気絶縁されて
いるため銅支持体45を接地することが可能とな
つたからである。
This high dielectric strength voltage was obtained because of the silicon dioxide thin film 43 with high insulation resistance and the transistor pellets 41, 41' silicon carbide sintered body 42.
This is because there is insulation between them. The low thermal resistance is due to the silicon dioxide thin film 43 being formed extremely thin and the silicon carbide sintered body 42 having good thermal conductivity helping heat radiation. Further, the noise can be reduced because the copper support 45 is electrically insulated from the transistor pellets 41, 41', so that the copper support 45 can be grounded.

そして熱疲労の生じにくい堅牢な一体化ができ
たのは、トランジスタペレツトと炭化ケイ素焼結
体の熱膨張係数がほぼ一致しているため、一体化
部の温度変化に伴なう残留応力変化を軽減できた
こと、および炭化ケイ素焼結体そのものの機械的
強度が大きいためモールド用樹脂の熱膨張などに
伴なう応力変化に十分抗し得ることによるもので
ある。
The reason why we were able to create a robust integration that is resistant to thermal fatigue is that the coefficients of thermal expansion of the transistor pellets and the silicon carbide sintered body are almost the same, so residual stress changes due to temperature changes in the integrated part. This is because the silicon carbide sintered body itself has high mechanical strength and can sufficiently withstand changes in stress caused by thermal expansion of the molding resin.

更に、本発明は炭化ケイ素焼結体上に形成させ
た二酸化ケイ素膜上にトランジスタを搭載したの
で、焼結体自身の高い誘電率を軽減できる顕著な
効果が得られ、その結果信号処理スピードを向上
させることができた。
Furthermore, since the present invention has a transistor mounted on a silicon dioxide film formed on a silicon carbide sintered body, a remarkable effect of reducing the high dielectric constant of the sintered body itself can be obtained, and as a result, the signal processing speed can be increased. I was able to improve it.

また、本実施例の場合、同一絶縁担体に4個の
ダイオードペレツトを載置できたため、スペーサ
重量の低減効果が著しく、同等の半導体装置の従
来品に比べ重量を約30%減らすことができた。
In addition, in the case of this example, four diode pellets could be placed on the same insulating carrier, so the spacer weight was significantly reduced, and the weight could be reduced by approximately 30% compared to the conventional equivalent semiconductor device. Ta.

以上のように、炭化ケイ素焼結体に二酸化ケイ
素薄膜を設けた担体は半導体素子を複数個集積し
た回路装置用絶縁担体として極めて有用であるこ
とが実証された。
As described above, it has been demonstrated that a carrier in which a silicon dioxide thin film is provided on a silicon carbide sintered body is extremely useful as an insulating carrier for a circuit device in which a plurality of semiconductor elements are integrated.

実施例 2 本実施例における半導体装置は、第2図に示す
ように、半導体素子としてのシリコンダイオード
ペレツト511,512,513,514を炭化
ケイ素52,52′上に二酸化ケイ素膜53,5
3′、アルミニウム層54,54′を介して一体化
し、これらの一体化物を銅支持体55上に一体化
し、各々のダイオードペレツトにリード線56
1,562,563,564を取付けるとともに
アルミニウム層54,54′にもリード線57,
57′を設け、4個のダイオードがそれぞれ整流
回路の一部を担うように電気接続し、そして少く
ともシリコンダイオードペレツト511,51
2,513,514が外気から遮断されるように
レジンモールドした混成集積回路装置である。レ
ンジモールドについては図示せず。
Embodiment 2 As shown in FIG. 2, a semiconductor device in this embodiment includes silicon diode pellets 511, 512, 513, 514 as semiconductor elements, and silicon dioxide films 53, 5 on silicon carbide 52, 52'.
3', are integrated via aluminum layers 54, 54', and these integrated bodies are integrated on a copper support 55, and a lead wire 56 is attached to each diode pellet.
1,562,563,564 are attached, and lead wires 57, 564 are attached to the aluminum layers 54, 54'.
57', electrically connected so that the four diodes each play a part of the rectifier circuit, and at least silicon diode pellets 511, 51
This is a hybrid integrated circuit device in which parts No. 2,513, and 514 are resin-molded so as to be isolated from the outside air. The range mold is not shown.

このような構成で得られた半導体装置の絶縁
性、放熱性、耐熱疲労性そして雑音防止効果は前
記実施例1と同等であつた。また、本実施例で
は、実施例1と同様に炭化ケイ素焼結体自身の誘
電率を二酸化ケイ素薄膜によつて軽減され、スピ
ード処理が可能であるとともに、同等の半導体装
置の従来品に比べ重量を約20%減らすことができ
た。
The insulation properties, heat dissipation properties, thermal fatigue resistance, and noise prevention effects of the semiconductor device obtained with such a configuration were equivalent to those of Example 1. In addition, in this example, as in Example 1, the dielectric constant of the silicon carbide sintered body itself is reduced by the silicon dioxide thin film, allowing for speedy processing and weight compared to conventional products of equivalent semiconductor devices. was able to be reduced by approximately 20%.

以上のように、炭化ケイ素と二酸化ケイ素から
なる絶縁担体は同一支持体に複数個載置するよう
な場合でも、本発明は支障なく適用できることが
確認された。
As described above, it has been confirmed that the present invention can be applied without problems even when a plurality of insulating carriers made of silicon carbide and silicon dioxide are placed on the same support.

以上に実施例を用いて本発明を説明したが、本
発明はこれのみに限定されるものではなく、例え
ば次のような場合でも本発明の効果ないし利点を
享受できる。
Although the present invention has been described above using examples, the present invention is not limited thereto, and the effects and advantages of the present invention can be enjoyed even in the following cases, for example.

(1) 二酸化ケイ素薄膜を炭化ケイ素焼結体表面の
半導体素子を載置する面に局部的に設けた場
合。
(1) When a silicon dioxide thin film is locally provided on the surface of the silicon carbide sintered body on which the semiconductor element is placed.

(2) 支持体が銅以外の金属例えばアルミニウムな
どの場合。
(2) When the support is made of a metal other than copper, such as aluminum.

(3) 半導体素子の材料が、ゲルマニウム、ヒ化ガ
リウム、リンイヒガリウムのような絶縁担体と
の熱膨張係数差が小さい場合。
(3) When the material of the semiconductor element has a small difference in thermal expansion coefficient from the insulating carrier such as germanium, gallium arsenide, or phosphogallium.

(4) 半導体素子の電極が同素子の両主面にある場
合(半導体素子の発熱が著しい場合)に限られ
ず、一方の主面に全ての電極が設けられている
場合。
(4) Not limited to cases where the electrodes of a semiconductor element are on both main surfaces of the same element (when the semiconductor element generates significant heat), but cases where all electrodes are provided on one main surface.

(5) 絶縁担体に載置される物が半導体素子以外に
他の電子回路素子例えば抵抗体やコンデンサな
どを載置した場合。
(5) When the objects placed on the insulating carrier include other electronic circuit elements such as resistors and capacitors in addition to semiconductor elements.

(6) 半導体素子が、ハンダやアルミニウム以外の
金属、例えば金、銀、銅、ガリウム、スズ、シ
リコン、ゲルマニウム、パラジウム、クロム、
ニツケル、モリブデン、タングステンから選択
された少くとも1つの元素からなる金属を介し
て絶縁担体に載置された場合。
(6) Semiconductor elements may be solder or metals other than aluminum, such as gold, silver, copper, gallium, tin, silicon, germanium, palladium, chromium,
When placed on an insulating carrier via a metal made of at least one element selected from nickel, molybdenum, and tungsten.

以上までに説明したように、本発明によれば次
のような利点ないし効果を奏することができる。
As explained above, according to the present invention, the following advantages and effects can be achieved.

(1) 絶縁担体母材が放熱性のよい炭化ケイ素焼結
体からなり、そして二酸化ケイ素が薄く形成さ
れるため、半導体素子−支持体間の熱抵抗が小
さい。この結果、半導体素子の過熱を防止でき
るため、半導体装置の特性を安定に保つことが
できる。
(1) Since the insulating carrier base material is made of a silicon carbide sintered body with good heat dissipation and silicon dioxide is formed thinly, the thermal resistance between the semiconductor element and the support is low. As a result, overheating of the semiconductor element can be prevented, so that the characteristics of the semiconductor device can be kept stable.

(2) 薄い二酸化ケイ素膜でも大きな絶縁抵抗が得
られるため、放熱性を損なうことなく半導体素
子−支持体間の絶縁耐圧を高めることができ
る。
(2) Since a large insulation resistance can be obtained even with a thin silicon dioxide film, the dielectric strength voltage between the semiconductor element and the support can be increased without impairing heat dissipation performance.

(3) 半導体素子が支持体から電気的に分離されて
おり、同支持体を接地することが可能なため、
半導体装置の特性が電磁波妨害による影響を受
けるのを防止できる。
(3) Since the semiconductor element is electrically isolated from the support and the support can be grounded,
It is possible to prevent the characteristics of a semiconductor device from being affected by electromagnetic interference.

(4) 半導体素子と絶縁担体との熱膨張係数差が小
さいため、両者の固定部に熱的に発生するスト
レスが小さく、また温度変化にともなう同部の
熱疲労を低減できる。この結果、温度変化に対
して安定な強固な一体化が可能となる。
(4) Since the difference in thermal expansion coefficient between the semiconductor element and the insulating carrier is small, the stress generated thermally in the part where they are fixed is small, and thermal fatigue of the part due to temperature changes can be reduced. As a result, strong integration that is stable against temperature changes is possible.

(5) 絶縁担体の機械的強度が優れているため、そ
の上に載置された半導体素子は外部から与えら
れる機械的シヨツクに容易に耐えることができ
る。
(5) Since the insulating carrier has excellent mechanical strength, the semiconductor element mounted thereon can easily withstand mechanical shocks applied from the outside.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図はそれぞれ本発明のパワー用
ハイブリツト型集積回路装置の実施例を示す断面
図である。 41,41′,511〜514……シリコント
ランジスタペレツト、45,55……銅支持体、
43,53,53′……二酸化ケイ素膜、42,
52,52′……炭化ケイ素焼結体、44,54,
54′……積層蒸着膜。
1 and 2 are cross-sectional views showing embodiments of the power hybrid integrated circuit device of the present invention, respectively. 41, 41', 511-514...Silicon transistor pellet, 45,55...Copper support,
43, 53, 53'... silicon dioxide film, 42,
52, 52'...Silicon carbide sintered body, 44, 54,
54'...Laminated vapor deposition film.

Claims (1)

【特許請求の範囲】 1 金属製支持体、該金属製支持体上に固着され
た絶縁担体および該担体上に金属層によつて載置
固定された少なくとも2個の半導体回路素子を備
えた装置において、前記絶縁担体は炭化ケイ素焼
結体からなり、前記回路素子を搭載した該焼結の
表面に二酸化ケイ素薄膜が形成されており、前記
二酸化ケイ素薄膜は前記支持体と前記素子との間
の絶縁耐圧が2000V以上となる厚さを有すること
を特徴とする混成集積回路装置。 2 特許請求の範囲第1項において、半導体回路
素子はダイオード、トランジスタ、サイリスタ、
集積回路素子のうち少なくとも一種であることを
特徴とする混成集積回路装置。
[Claims] 1. A device comprising a metal support, an insulating carrier fixed on the metal support, and at least two semiconductor circuit elements placed and fixed on the carrier by a metal layer. In this, the insulating carrier is made of a silicon carbide sintered body, and a silicon dioxide thin film is formed on the surface of the sintered body on which the circuit element is mounted, and the silicon dioxide thin film is formed between the support body and the element. A hybrid integrated circuit device characterized by having a thickness such that the dielectric strength voltage is 2000V or more. 2 In claim 1, the semiconductor circuit element is a diode, a transistor, a thyristor,
A hybrid integrated circuit device comprising at least one type of integrated circuit element.
JP9099279A 1979-07-19 1979-07-19 Semiconductor device Granted JPS5615047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9099279A JPS5615047A (en) 1979-07-19 1979-07-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9099279A JPS5615047A (en) 1979-07-19 1979-07-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5615047A JPS5615047A (en) 1981-02-13
JPS6358368B2 true JPS6358368B2 (en) 1988-11-15

Family

ID=14014002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9099279A Granted JPS5615047A (en) 1979-07-19 1979-07-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5615047A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3064598D1 (en) * 1979-11-05 1983-09-22 Hitachi Ltd Electrically insulating substrate and a method of making such a substrate
JPS58101442A (en) * 1981-12-11 1983-06-16 Hitachi Ltd Substrate for electric device

Also Published As

Publication number Publication date
JPS5615047A (en) 1981-02-13

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