JPS6214943B2 - - Google Patents
Info
- Publication number
- JPS6214943B2 JPS6214943B2 JP54137667A JP13766779A JPS6214943B2 JP S6214943 B2 JPS6214943 B2 JP S6214943B2 JP 54137667 A JP54137667 A JP 54137667A JP 13766779 A JP13766779 A JP 13766779A JP S6214943 B2 JPS6214943 B2 JP S6214943B2
- Authority
- JP
- Japan
- Prior art keywords
- copper
- polyimide
- electronic device
- layer
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/6875—Shapes or dispositions thereof being on a metallic substrate, e.g. insulated metal substrates [IMS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
Landscapes
- Die Bonding (AREA)
Description
【発明の詳細な説明】
本発明は半導体素子を絶縁物を介して金属支持
体上に載置した電子装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic device in which a semiconductor element is mounted on a metal support via an insulator.
半導体装置の一例である高出力トランジスタで
は、数アンペア以上のコレクタ電流が流れるが、
この際半導体素子としてのトランジスタペレツト
の内部において発熱を伴なう。この発熱に起因す
る特性の不安定性や寿命の加速的劣化を避けるた
め、トランジスタペレツトが許容制限温度を越え
て昇温するのを防止する方法がとられている。温
度上昇を防ぐ方法の1つとして、従来、トランジ
スタペレツトの支持体としてのステムを放熱器に
取付け、トランジスタペレツトで発生した熱をス
テムや放熱器を介して外部へ放出させる方法がと
られてきた。しかしながら、高出力トランジスタ
の場合、上述したように大きなコレクタ電流を流
すため、その電流路を確保することや効率的に熱
放散させる必要から、コレクタ領域が直接ステム
に固着されるようにトランジスタペレツトを載置
している。ところが、この種のトランジスタは通
常エミツタまたはベース接地にして使用されるた
め、コレクタ端子即ちステムは多くの場合接地状
態におかれる放熱器(またはシヤーシ)などに直
接取付けることができない。このため、通常はス
テムと放熱器との間に、例えばマイカまたはテレ
フタル酸ポリエステル(マイラ)などの絶縁板を
はさんで電気的に絶縁し、かつ放熱を助けるため
にステム−絶縁板間および絶縁板−放熱器間に空
隙を埋めるためのグリースを介し、そしてステム
と放熱器とを絶縁ワツシヤを介したネジ締めによ
つて固定していた。しかしこの場合でも、コレク
タ領域がステムに電気的に接続されている(ステ
ムを接地状態にできない)ため、このままでは電
磁波妨害による雑音の影響を避けることが困難で
ある。 In a high-output transistor, which is an example of a semiconductor device, a collector current of several amperes or more flows.
At this time, heat is generated inside the transistor pellet as a semiconductor element. In order to avoid instability of characteristics and accelerated deterioration of lifetime due to this heat generation, methods are used to prevent the temperature of the transistor pellet from rising beyond the allowable limit temperature. One method of preventing temperature rise has traditionally been to attach the stem, which serves as a support for the transistor pellet, to a radiator, and to release the heat generated by the transistor pellet to the outside via the stem and the radiator. It's here. However, in the case of high-output transistors, a large collector current flows as described above, so it is necessary to secure a current path and dissipate heat efficiently, so the transistor pellet is designed so that the collector region is directly attached to the stem. is listed. However, since this type of transistor is usually used with its emitter or base grounded, the collector terminal or stem cannot be directly attached to a heat sink (or chassis) etc. which is often grounded. For this reason, an insulating plate such as mica or polyester terephthalate (Mylar) is usually sandwiched between the stem and the heat sink to electrically insulate the stem and the heat sink. The stem and the radiator were fixed by using grease to fill the gap between the plate and the radiator, and by tightening screws using an insulating washer. However, even in this case, since the collector region is electrically connected to the stem (the stem cannot be grounded), it is difficult to avoid the effects of noise due to electromagnetic interference.
一方、電気絶縁、効率的な熱放散、および電磁
波妨害防止をはかる試みとして金属支持体上にベ
リリヤ磁器やアルミナ磁器を介して半導体素子を
載置した例がある。しかしながら、ベリリヤ磁器
を用いた場合は具体的に次のような問題があつ
た。(1)ベリリヤ自体強い毒性を有していてその取
扱いに厳重な注意を要し、しかも入手困難で高価
である。(2)ベリリヤ磁器の熱膨張係数は7.6×
10-6/℃と支持体やコレクタ電極を兼ねるペレツ
ト載置板として広く用いられる銅(18×10-6/
℃)やアルミニウム(25×10-6/℃)との差が大
きく、そのままではベリリヤ磁器−支持体間ある
いはベリリヤ磁器−載置板間接合部に熱疲労を生
じやすく、両者間の強固な一体化が困難である。
(3)接合部の熱疲労を緩和するには歪緩和のための
緩衝領域を設ける必要があり、このためには例え
ば接合部のソルダ層を厚くしたり、あるいはモリ
ブデン(5.2×10-6/℃)やタングステン(4.3×
10-6/℃)などのスペーサを絶縁板に加えて介す
必要があるが、この場合は一体化に要する部品点
数や処理工数の面で損失が多くなるほか熱放散上
も不利になり。(4)絶縁板としてベリリヤ磁器を用
いた場合に不可欠なスペーサとしてのモリブデン
やタングステンは重い金属である(モリブデンの
比重:10.27、タングステンの比重19.3)ことか
ら、半導体装置の軽量化をはかる際の障害とな
る。一方、アルミナ磁器を用いた場合でも、毒性
の問題を除いては前述したベリリヤ磁器と同様の
問題を伴なう。 On the other hand, in an attempt to achieve electrical insulation, efficient heat dissipation, and prevention of electromagnetic interference, there are examples in which a semiconductor element is mounted on a metal support via beryllia porcelain or alumina porcelain. However, when Beryliya porcelain was used, the following problems specifically occurred. (1) Beryllium itself is highly toxic and requires extreme caution when handling, and is difficult to obtain and expensive. (2) The coefficient of thermal expansion of Beryliya porcelain is 7.6×
10 -6 /℃ and copper ( 18
℃) and aluminum ( 25 It is difficult to
(3) In order to alleviate thermal fatigue at the joint, it is necessary to provide a buffer area for strain relief. For this purpose, for example, the solder layer at the joint may be made thicker, or molybdenum (5.2×10 -6 / °C) and tungsten (4.3×
It is necessary to insert a spacer such as 10 -6 /℃) in addition to the insulating plate, but in this case, there is a large loss in terms of the number of parts and processing steps required for integration, and it is also disadvantageous in terms of heat dissipation. (4) Molybdenum and tungsten, which are essential spacers when using beryllia porcelain as an insulating plate, are heavy metals (specific gravity of molybdenum: 10.27, specific gravity of tungsten: 19.3), so when trying to reduce the weight of semiconductor devices. It becomes an obstacle. On the other hand, even when alumina porcelain is used, the same problems as the above-mentioned Beryliya porcelain arise, except for the problem of toxicity.
以上の背景から種々検討した結果、例えば第1
図に示すように、半導体素子1を銅支持体2上に
載置するにあたり、ポリイミド3および接着剤と
してのフツ素化エチレン4,4′を介して銅支持
体2に一体化した銅載置板5からなる構成が電子
装置として極めて有効であるとの知見を得た。し
かしながら、次の理由からさらに高出力の電子装
置として適用することが困難であつた。 As a result of various studies based on the above background, for example, the first
As shown in the figure, when placing the semiconductor element 1 on the copper support 2, the copper support 2 is integrated with the copper support 2 via the polyimide 3 and fluorinated ethylene 4, 4' as an adhesive. It has been found that the configuration consisting of the plate 5 is extremely effective as an electronic device. However, it has been difficult to apply it to higher output electronic devices for the following reasons.
(1) ポリイミド3自体フレキシブルな性質を有し
ていることおよび接着剤としてのフツ素化エチ
レン4,4′層が薄いことと相まつて接着層、
即ち支持体2−ポリイミド3間あるいはポリイ
ミド3−載置板5間に局部的に空隙を生じ、均
一な接着が困難である。(1) The fact that polyimide 3 itself has flexible properties and the fluorinated ethylene 4,4' layer as an adhesive is thin, combined with the fact that the adhesive layer
That is, gaps are locally formed between the support 2 and the polyimide 3 or between the polyimide 3 and the mounting plate 5, making uniform adhesion difficult.
(2) (1)の結果、接着率(空隙を生じない面積/全
接触面積)が低い。(2) As a result of (1), the adhesion rate (area without voids/total contact area) is low.
(3) (1)、(2)の結果、熱伝導に寄与する有効面積が
少なく、放熱性が阻害される。(3) As a result of (1) and (2), the effective area contributing to heat conduction is small, and heat dissipation is inhibited.
(4) (1)、(2)の結果、接着面積の拡張が困難であ
る。(4) As a result of (1) and (2), it is difficult to expand the adhesive area.
以上にトランジスタを例にして従来の電子装置
の欠点を説明したが、トランジスタに限らず、ダ
イオードやサイリスタなど他の半導体装置、ある
いは少なくとも半導体素子を含む混成集積回路装
置とした場合でも同様の問導点を残していた。 The drawbacks of conventional electronic devices have been explained using transistors as an example, but the same problems apply not only to transistors but also to other semiconductor devices such as diodes and thyristors, or at least to hybrid integrated circuit devices that include semiconductor elements. I left a mark.
本発明の目的は、接着効率を高めることによつ
て放熱性を改善した電子装置を提供するにある。 An object of the present invention is to provide an electronic device with improved heat dissipation by increasing adhesive efficiency.
本発明は、半導体素子を載置する金属載置体と
これを支持する金属支持体とをポリイミドを介し
て一体化する際に銅層と金属ソルダ層とから成る
金属層を介して行うようにしたものである。 The present invention provides a method for integrating a metal mounting body on which a semiconductor element is placed and a metal support body supporting the same through a metal layer consisting of a copper layer and a metal solder layer. This is what I did.
この場合、銅層はポリイミドのフレキシブル性
を抑制して高温下の一体化熱処理時にも平坦性を
保持せしめる役割および金属ソルダとの接着性を
保持するための役割を担うものであり、そして金
属ソルダ層は載置体または支持体との一体化を遂
行するとともにこれらの面の非平坦性に起因する
空隙を埋め合せる役割を担うものである。 In this case, the copper layer plays the role of suppressing the flexibility of the polyimide and maintaining flatness even during high-temperature integration heat treatment, and the role of maintaining adhesion with the metal solder. The layer serves to achieve integration with the carrier or support and to fill voids caused by non-flatness of these surfaces.
第2図は本発明の実施例を示す正面図である。 FIG. 2 is a front view showing an embodiment of the present invention.
第2図に示すように、半導体素子としてのシリ
コントランジスタペレツト11を載置する銅載置
板15を銅支持板12上にポリイミド13を介し
て一体化するにあたり、支持板12とポリイミド
13の間に銅層14と鉛−スズ系ハンダ層14′
を介して一体化し、他方ポリイミド13を載置板
15間にフツ素化エチレン層16を介して一体化
したものである。この際以上の一体化物のトラン
ジスタペレツト11のエミツタおよびベース領域
をそれぞれアルミニウム線17,18で接続し、
そしてコレクタ領域は銅載置板15を介してアル
ミニウム線19に電気接続し、その後通常用いら
れる方法でアルミニウム線17,18,19を銅
リード(図示せず)に接続し、そして銅支持板1
2および銅リードの一部を除く少なくとも前述の
各部が完全に外気からしや断されるように樹脂で
モールド(図示せず)した。 As shown in FIG. 2, when a copper mounting plate 15 on which a silicon transistor pellet 11 as a semiconductor element is placed is integrated onto a copper support plate 12 via a polyimide 13, the support plate 12 and polyimide 13 are separated. In between, there is a copper layer 14 and a lead-tin solder layer 14'.
On the other hand, the polyimide 13 is integrated between the mounting plates 15 via a fluorinated ethylene layer 16. At this time, the emitter and base regions of the above integrated transistor pellet 11 are connected with aluminum wires 17 and 18, respectively.
The collector region is then electrically connected to the aluminum wire 19 via the copper mounting plate 15, and then the aluminum wires 17, 18, 19 are connected to copper leads (not shown) in a conventional manner, and the copper support plate 1
At least each of the above-mentioned parts except part 2 and the copper lead were molded with resin (not shown) so as to be completely isolated from the outside air.
このような構成で得られた電子装置の接着率
は、ポリイミド13−載置板15間では約75%と
第1図構造の従来例の約60%より向上され、支持
板12−ポリイミド13間では約96%大幅に向上
した。後者で大幅な向上が見られたのは、ハンダ
層14′が溶融して空隙を埋める働きを効果的に
行つたためであり、前者で小幅ながら向上したの
は銅層14の存在によりポリイミド13の本質で
あるフレキシブル性が抑制され、空隙の新たな発
生が抑制されたためである。この結果、トランジ
スタペレツト11−支持板12間の熱抵抗は第1
図の従来構造の場合に比べて約50%低い値を示し
た。このように、本実施例によれば接着部の空隙
が軽減されているため放熱性の優れることが確認
された。また、絶縁耐圧は2000V以上が得られ、
−20℃〜+150℃間の熱サイクルを1000回与えた
ときの接着部には何等の異常も見出されなかつ
た。このように高い絶縁耐圧が得られたのは、ポ
リイミドの優れた絶縁性が有効に生かされている
ためであり、熱疲労の生じにくい堅牢な一体化が
可能であるのは、ポリイミドやフツ素化エチレン
が銅支持板や銅載置板とほぼ同等の熱膨張係数を
有するとともにハンダ層が銅と銅の間にはさまれ
た構造になつているため熱ストレスによる変形作
用を受けにくいことに起因する。 The adhesion rate of the electronic device obtained with this configuration is about 75% between the polyimide 13 and the mounting plate 15, which is improved from about 60% in the conventional example of the structure shown in FIG. This was a significant improvement of approximately 96%. The reason for the significant improvement in the latter case was that the solder layer 14' melted and effectively filled the voids, and the reason for the small improvement in the former case was due to the presence of the copper layer 14, which caused the polyimide 13 This is because the flexibility, which is the essence of the material, is suppressed, and the generation of new voids is suppressed. As a result, the thermal resistance between the transistor pellet 11 and the support plate 12 is the first
The value was approximately 50% lower than that of the conventional structure shown in the figure. As described above, it was confirmed that according to this example, the voids in the bonded portion were reduced, so that heat dissipation was excellent. In addition, an insulation voltage of over 2000V can be obtained.
No abnormality was found in the bonded portion when thermal cycles between -20°C and +150°C were applied 1000 times. The reason why such a high dielectric strength voltage was obtained is that the excellent insulating properties of polyimide are effectively utilized.Polyimide and fluorine materials make it possible to form a robust structure that is less likely to cause thermal fatigue. Ethylene has a coefficient of thermal expansion that is almost the same as that of the copper support plate and copper mounting plate, and the solder layer is sandwiched between the copper layers, making it less susceptible to deformation due to thermal stress. to cause.
第3図は本発明の第2の実施例を示す正面図で
ある。 FIG. 3 is a front view showing a second embodiment of the invention.
第3図に示すように、第2図の実施例と同様に
銅載置板15をポリイミド13を介して銅支持板
12上に一体化するにあたり、ポリイミド13−
支持板12間に銅層14と鉛−スズ系ハンダ層1
4′を介するとともに、載置板15−ポリイミド
13間にもハンダ層21′と銅層21を介して一
体化したものである。また、この上に前記第1の
実施と同様にトランジスタペレツトを載置すると
ともに所定の電気配線やモールデイングをして電
子装置を構成する。 As shown in FIG. 3, similar to the embodiment shown in FIG.
A copper layer 14 and a lead-tin solder layer 1 are placed between the support plates 12.
4' and also between the mounting plate 15 and the polyimide 13 via a solder layer 21' and a copper layer 21. Further, as in the first embodiment, a transistor pellet is placed thereon, and predetermined electrical wiring and molding are applied to form an electronic device.
このような構成で得られた電子装置の接着率
は、支持板12−ポリイミド13間では約95%と
前記第1の実施例とほぼ同等であり、ポリイミド
13−載置板15間では約93%と前記実施例1の
場合より大幅に向上された。支持板12側、載置
板15側とも接着率が向上したのは、ポリイミド
13の両側に銅層14,21ではさまれた構造の
ためポリイミドの本質であるフレキシブル性が抑
制され、空隙の新たな発生が抑制されたことと、
ハンダ層14′,21′が溶融して空隙を埋める働
きが効果的になされたためである。その結果、こ
の電子装置のトランジスタペレツト−支持板12
間の熱抵抗は前記実施例1の場合より約30%低い
値を示した。このように、本実施例によれば、放
熱性を一層向上できることが確認された。また、
前記第1の実施例と同様、優れた電気絶縁性や耐
熱疲労性が確認された。 The adhesion rate of the electronic device obtained with such a configuration is about 95% between the support plate 12 and the polyimide 13, which is almost the same as in the first embodiment, and about 93% between the polyimide 13 and the mounting plate 15. %, which was significantly improved compared to the case of Example 1. The reason why the adhesion rate improved on both the support plate 12 side and the mounting plate 15 side is because the structure in which polyimide 13 is sandwiched between copper layers 14 and 21 on both sides suppresses the flexibility, which is the essence of polyimide, and creates new voids. The outbreak was suppressed, and
This is because the solder layers 14' and 21' melted and effectively filled the voids. As a result, the transistor pellet support plate 12 of this electronic device
The thermal resistance between them was approximately 30% lower than that of Example 1. Thus, it was confirmed that according to this example, the heat dissipation performance could be further improved. Also,
As with the first example, excellent electrical insulation and thermal fatigue resistance were confirmed.
第4図は本発明の第3の実施例を示す正面図で
ある。 FIG. 4 is a front view showing a third embodiment of the present invention.
第4図に示すように、銅支持板31上に銅載置
板32,32′と銅電極板33をポリイミド34
を介して一体化するにあたり、銅支持板31−ポ
リイミド34間に銅層35と鉛−スズ系ハンダ層
36を介して一体化し、他方ポリイミド34−銅
載置板32,32′および銅電極板33間にフツ
素化エチレン層37を介して一体化したものであ
る。この際、サイリスタ38、ダイオード39,
40、チツプコンデンサ41、チツプ抵抗42が
載置され、所定の配線およびモールデイングがさ
れた電流制御用電子装置を得ている。 As shown in FIG.
In integrating the copper supporting plate 31 and the polyimide 34, a copper layer 35 and a lead-tin solder layer 36 are interposed between the copper support plate 31 and the polyimide 34, and the other polyimide 34, the copper mounting plates 32, 32', and the copper electrode plate are integrated. 33 and are integrated with a fluorinated ethylene layer 37 interposed therebetween. At this time, the thyristor 38, the diode 39,
40, a chip capacitor 41, and a chip resistor 42 are mounted, and a current control electronic device is obtained with predetermined wiring and molding.
このような構成で得られた電子装置の接着率は
前記第1の実施例の場合とほぼ同等であり従来法
による電子装置より大幅に向上した。この理由は
前記第1の実施例の場合と同様である。また、電
流制御用電子装置に80Wの電力を印加し銅支持板
31の温度を80℃に保つたときのサイリスタ3
8、ダイオード39,40の各温度を測定したと
ころ高々115℃にしかならず、そしてチツプ抵抗
42の抵抗値変化も高々5%にしかならなかつ
た。このように、第4図の実施例によれば、半導
体素子や受動素子などを多数載置した混成集積回
路を構成する電子装置としてもその機能を十分に
果し得ることが確認された。この主な理由は前記
第1の実施例と同様に、接着率の向上にともなう
放熱性の向上による。さらに、電気絶縁性および
耐熱疲労性についても前記第1の実施例とほぼ同
等であることが確認された。 The adhesion rate of the electronic device obtained with this configuration was almost the same as that of the first embodiment, and was significantly improved over the electronic device obtained by the conventional method. The reason for this is the same as in the first embodiment. Also, when 80W of power is applied to the current control electronic device and the temperature of the copper support plate 31 is maintained at 80℃, the thyristor 3
8. When the temperature of each of the diodes 39 and 40 was measured, it was only 115° C. at most, and the change in resistance value of the chip resistor 42 was only 5% at most. As described above, it has been confirmed that the embodiment shown in FIG. 4 can sufficiently function as an electronic device constituting a hybrid integrated circuit in which a large number of semiconductor elements, passive elements, etc. are mounted. The main reason for this is, as in the first embodiment, the improvement in heat dissipation accompanying the improvement in the adhesion rate. Furthermore, it was confirmed that the electrical insulation properties and thermal fatigue resistance were almost the same as those of the first example.
第5図は本発明の第4の実施例を示す正面図で
ある。 FIG. 5 is a front view showing a fourth embodiment of the present invention.
本実施例における電子装置は、銅支持板57上
に前記第3の実施例と同様にして第1銅載置板5
1と銅電極板33を一体化したものの第1銅載置
板51上に、さらにフツ素化エチレン53−ポリ
イミド51−銅55−ハンダ56から構成される
積層体を介して第2銅載置板52を一体化したも
のである。この際、発熱量の比較的少ないダイオ
ード40を第2銅載置板52に載置し、他の回路
素子は前記第3の実施例と同様にして載置して、
前記第3の実施例と同等の電力容量を持つ電流制
御用電子装置を得ている。 In the electronic device of this embodiment, a first copper mounting plate 5 is placed on a copper support plate 57 in the same way as in the third embodiment.
1 and copper electrode plate 33 are integrated, and on the first copper mounting plate 51, a second copper is further placed via a laminate composed of fluorinated ethylene 53, polyimide 51, copper 55, and solder 56. The plate 52 is integrated. At this time, the diode 40, which generates a relatively small amount of heat, is mounted on the second copper mounting plate 52, and the other circuit elements are mounted in the same manner as in the third embodiment.
A current control electronic device having the same power capacity as the third embodiment is obtained.
このような構成電子装置に80Wの電力を印加し
銅支持板57の温度を80℃に保つた場合でもサイ
リスタ38、ダイオード39,40、およびチツ
プ抵抗42の温度は115℃を越えず、熱放散上の
支障は見出されなかつた。また、電気特性および
耐熱疲労性についても、前記第3の実施例同様支
障となる点は見出されなかつた。さらに、本実施
例の場合は、回路素子の実装密度が高められたた
め、前記第3の実施例と同等の電力容量を有する
電子装置でありながら実装面積を約25%小さくす
ることができた。 Even when 80W of power is applied to such an electronic device and the temperature of the copper support plate 57 is maintained at 80°C, the temperature of the thyristor 38, diodes 39, 40, and chip resistor 42 does not exceed 115°C, and heat dissipation is prevented. No problems were found. Furthermore, no problems were found with regard to electrical properties and thermal fatigue resistance, as in the third example. Furthermore, in the case of this example, since the packaging density of the circuit elements was increased, the packaging area could be reduced by approximately 25% even though the electronic device had the same power capacity as the third example.
以上、各実施例を用いて本発明を説明したが、
本発明はこれのみに限定されるものではなく、例
えば次のような場合でも本発明の効果ないし利点
を享受できる。 The present invention has been described above using each example, but
The present invention is not limited to this, and the effects and advantages of the present invention can be enjoyed even in the following cases, for example.
(1) 電子装置を構成する支持体や載置体が表面に
金、ニツケル、銀などで表面被覆した銅または
アルミニウムである場合。(1) When the support or mounting body that constitutes the electronic device is made of copper or aluminum whose surface is coated with gold, nickel, silver, etc.
(2) 電子装置を構成する金属ソルダ層用材料が少
なくとも金−ゲルマニウム、金−シリコンなど
の金系合金ソルダまたは銀−スズなどの銀系合
金ソルダである場合。(2) When the material for the metal solder layer constituting the electronic device is at least a gold-based alloy solder such as gold-germanium or gold-silicon, or a silver-based alloy solder such as silver-tin.
(3) 電子装置を構成する載置体にコンデンサや抵
抗体などの受動素子を載置した場合。(3) When passive elements such as capacitors and resistors are placed on a mounting body that constitutes an electronic device.
以上詳細に説明したように、本発明の実施例に
よれば次のような利点ないし効果を奏することが
できる。 As described above in detail, the embodiments of the present invention can provide the following advantages and effects.
(1) ポリイミドと支持体または載置体間に銅層と
金属ソルダ層を介しているため、金属ソルダが
溶融して空隙を埋める働きをするとともに銅層
の存在によりポリイミドのフレキシブル性が抑
制されて空隙の発生が防止される。(1) Since a copper layer and a metal solder layer are interposed between the polyimide and the support or mounting body, the metal solder melts and fills the voids, and the presence of the copper layer suppresses the flexibility of the polyimide. This prevents the formation of voids.
(2) (1)の結果、接着率が向上する。(2) As a result of (1), the adhesion rate improves.
(3) (1)、(2)の結果放熱性が向上する。(3) As a result of (1) and (2), heat dissipation is improved.
(4) (3)の結果、電子装置の回路素子実装密度を上
げられるため、同装置を小型化できる。(4) As a result of (3), it is possible to increase the mounting density of circuit elements in an electronic device, thereby making the device smaller.
(5) ポリイミドの絶縁性が優れるため、電子装置
の絶縁性がよい。(5) Since polyimide has excellent insulation properties, it provides good insulation for electronic devices.
(6) ポリイミドやフツ素化エチレンが支持板や載
置板の母材となる銅やアルミニウムとほぼ同等
の熱膨張係数を有するとともに、金属ソルダ層
がほぼ同等の熱膨張係数を有する銅層−支持体
または銅層−載置体間にはさまれる構造のた
め、熱ストレスによる疲労の生じにくい電子装
置を実現できる。(6) A copper layer in which polyimide or fluorinated ethylene has a coefficient of thermal expansion almost equal to that of copper or aluminum, which is the base material of the support plate or mounting plate, and a metal solder layer has a coefficient of thermal expansion almost the same as that of copper or aluminum, which is the base material of the support plate or mounting plate. Since the structure is sandwiched between the support body or the copper layer and the mounting body, it is possible to realize an electronic device that is less prone to fatigue due to thermal stress.
なお、本発明を構成するにあたり、ポリイミド
と銅層とは直接一体化されていることが最も望ま
しいが、接着材を介して一体化されていてもよ
い。また、金属ソルダは熱ストレスに対する信頼
性や、コスト、作業温度等の観点から鉛−スズ系
ハンダが望ましいが、例えばインジウム、アンチ
モン、金、銀、アルミニウム、シリコン、ゲルマ
ニウム、鉛、スズ、の中から選択された少なくと
も1種の金属を含む合金ソルダであつても良い。 In constructing the present invention, it is most desirable that the polyimide and the copper layer are directly integrated, but they may be integrated via an adhesive. In addition, lead-tin solder is preferable from the viewpoint of reliability against heat stress, cost, working temperature, etc., but for example, lead-tin solder is preferable. It may be an alloy solder containing at least one metal selected from the following.
以上より明らかなように本発明によれば、放熱
性の良い電子装置を得ることができる。 As is clear from the above, according to the present invention, an electronic device with good heat dissipation performance can be obtained.
第1図は従来の電子装置の正面図、第2図は本
発明の第1の実施例の正面図、第3図は本発明の
第2の実施例の正面図、第4図は本発明の第3の
実施例の正面図、第5図は本発明の第4の実施例
の正面図である。
11……シリコントランジスタペレツト、1
2,31,57……銅支持板、13,34,54
……ポリイミド、14,21,35……銅層、1
4′,21′,36……ハンダ層、15,32,3
2′……銅載置板、16,37,53……フツ素
化エチレン層、33……銅電極板、38……サイ
リスタ、39,40……ダイオード、41……チ
ツプコンデンサ、42……チツプ抵抗、51,5
2……第1、第2載置板。
FIG. 1 is a front view of a conventional electronic device, FIG. 2 is a front view of a first embodiment of the present invention, FIG. 3 is a front view of a second embodiment of the present invention, and FIG. 4 is a front view of the present invention. FIG. 5 is a front view of the third embodiment of the present invention, and FIG. 5 is a front view of the fourth embodiment of the present invention. 11...Silicon transistor pellet, 1
2, 31, 57...Copper support plate, 13, 34, 54
...Polyimide, 14,21,35...Copper layer, 1
4', 21', 36...Solder layer, 15, 32, 3
2'... Copper mounting plate, 16, 37, 53... Fluorinated ethylene layer, 33... Copper electrode plate, 38... Thyristor, 39, 40... Diode, 41... Chip capacitor, 42... Chip resistance, 51,5
2...First and second mounting plates.
Claims (1)
載置体を支持する金属支持体との間にポリイミド
を介して一体化形成してなる電子装置において、
前記金属載置体または前記金属支持体のいずれか
一方と前記ポリイミドとの間に、銅層と金属ソル
ダとから成る金属層を介在させたことを特徴とす
る電子装置。1. In an electronic device formed by integrally forming a metal mounting body on which a semiconductor element or the like is placed and a metal support body supporting the metal mounting body via polyimide,
An electronic device characterized in that a metal layer consisting of a copper layer and a metal solder is interposed between either the metal mounting body or the metal support and the polyimide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13766779A JPS5662343A (en) | 1979-10-26 | 1979-10-26 | Electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13766779A JPS5662343A (en) | 1979-10-26 | 1979-10-26 | Electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5662343A JPS5662343A (en) | 1981-05-28 |
| JPS6214943B2 true JPS6214943B2 (en) | 1987-04-04 |
Family
ID=15203990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13766779A Granted JPS5662343A (en) | 1979-10-26 | 1979-10-26 | Electronic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5662343A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58169912A (en) * | 1982-03-31 | 1983-10-06 | Hitachi Ltd | Semiconductor device |
| JPS5952853A (en) * | 1982-09-20 | 1984-03-27 | Hitachi Ltd | Semiconductor device |
-
1979
- 1979-10-26 JP JP13766779A patent/JPS5662343A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5662343A (en) | 1981-05-28 |
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