JPS6359175B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a pipeline control method for a data processing device that executes a plurality of instructions in parallel.

[Prior art]

In data processing devices such as microcomputers, in order to achieve faster processing speed,
Two methods have been taken: increasing the operating clock and improving the internal control system. Among these methods, the method of increasing the operating clock largely depends on device technology, and as device technology improves, the speed can only be increased by about 10% at most. For this reason, new internal control methods such as pipeline control are adopted to dramatically improve performance.

In the pipeline control method, a series of processing performed by executing one instruction is divided into several basic processes, and the dedicated hardware necessary to perform each of these basic processes one by one is provided. Prepare multiple functional units. By operating these functional units continuously according to the processing order, the overall processing speed is improved.
This is a method often used to improve processing speed.

A conventionally used pipeline control method will be explained. First, referring to the block diagram of FIG. 1, the functions of three functional units of a central processing unit (hereinafter referred to as CPU) in this conventional example will be explained. The bus interface unit 1-1 reads instruction codes from memory, writes and reads data, the operand address calculation unit 1-2 modifies memory addresses when referencing memory, and the execution unit 1-3 performs various functions. Performs transfer and calculation processing.

FIG. 2 is an operational diagram of arithmetic instructions between memories of a CPU composed of the three functional units shown in FIG. This means that when executing one instruction,
It shows how each functional unit is used over time in predetermined time units (hereinafter referred to as stages), and the length of each stage is fixed. That is, each functional unit performs a predetermined operation in the following order.

First stage period of T _A1 : The bus interface section 1-1 reads out the instruction code.

Second stage period of T _A2 : The execution unit 1-3 decodes the instruction.

Third stage period of T _A3 : The operand address calculation unit 1-2 modifies the address when referring to the memory.

Fourth stage period of T _A4 : The bus interface section 1-1 reads data from the memory.

Fifth stage period of T _A5 : The execution unit 1-3 performs arithmetic processing.

Period of the 6th stage of T _A6 : The bus interface unit 1-1 stores the calculation result in the memory.

The CPU described in this conventional example has many other instructions and is capable of various processing, but the order in which functional units are used for one instruction is the same, so all instructions are , each functional unit is used and processing proceeds as shown in the operational diagram of FIG.

Next, a control method will be described when an instruction having an operation diagram consisting of six stages as shown in the operation diagram of FIG. 2 is processed by pipeline control.

When processing instructions in a pipeline manner, a problem arises in the timing of starting execution of the next instruction while one instruction is being executed.

The operation diagrams in FIGS. 3a to 3f show the operating state of each unit at each stage when one instruction is being executed and the next instruction is started. This figure 3 a-f
As shown in the operation diagram, while executing the instruction B, the third
When the next A instruction is started at the timing shown _{in FIG} . and at the T _B5 stage of the execution unit 1-3, and at the timing shown in Figure 3e, the bus interface unit 1-1
At stage T _B6 , the processing in instruction A and the processing in instruction B conflict.

The collision diagram in Figure 4 shows whether or not a collision occurs within the functional unit during the execution of an instruction corresponding to each activation timing of the next instruction shown in Figures 3a to 3f. It is. Each example in the collision diagram indicates the start timing of the next instruction, and 0 in the table indicates that there will be no collision even if the next instruction is started at that timing, and the pipeline operation will be maintained normally. If the next instruction starts at the right timing, the processing of the previous instruction and the next instruction will inevitably conflict within the functional unit, indicating that normal operation of the pipeline cannot continue.

In the collision diagram of FIG. 4 of this conventional example, there is no collision if the next instruction is started at timings t _A1 , t _A4 , and t _A6 during the execution of one instruction, but at t _A2 , t _A3 , and t _A5 . A collision occurs. Based on this collision diagram, the start timing of the next instruction, which is most important in pipeline control, is determined.

Next, the hardware configuration and operation for determining the start timing of the next instruction will be explained using the block diagram of the pipeline control circuit shown in FIG.

Register 5-1-0 to register 5-1-5
holds data on whether a collision occurs during pipeline processing shown in the collision diagram of FIG.
These six registers 5-1-5 to 5-
1-0 constitutes a shift register 5-1.

The shift clock 5-2 becomes active every time the processing at each stage is completed and shifts the data in the shift register 5-1 to the left. Register 5-1-5 which is the final output of shift register 5-1
The output is an instruction start signal 5-3, which controls the start of the next instruction in pipeline control. If it is "0", the next instruction will be activated; if it is "1", it will not be activated.
The initial collision data generation circuit 5-4 is used to correct the data in the shift register 5-1 when the next instruction is started. Assembled gate 5-5
selects the data to be input to the next stage register in the shift register 5-1 under the control of the instruction start signal 5-3.If the instruction start signal 5-3 is "0", the data to be input to the next stage register in the shift register 5-1 is selected. The logical sum of the data in each register in 1 and the corresponding bit of the initial collision data generation circuit 5-4 is input to the next stage register.
If it is "1", the data in each register is simply input to the next register.

The operation diagram in FIG. 6 is based on the register 5-1- in FIG.
The data holding state of the shift register 5-1, which is composed of registers 5 to 5-1-0, is expressed for each stage. In the initial state, the left register 5-1 contains "0", "1", "1", "0", "1" as shown in the collision diagram of FIG.
,
“0” is stored in this order. When the first instruction is executed, in the first stage, the state of the instruction start signal 5-3, which is the final output of the shift register 5-1, is checked. Since the state of this signal is "0", the next instruction is immediately started in the next second stage. At the same time, since a new command is started, it becomes necessary to correct the collision diagram, and the collision data corrected by the initial collision data generation circuit 5-4 is shifted to the left under the control of the assembly gate 5-5. The contents of -1 become the data shown in the second stage of FIG. In the second stage, the state of the command start signal 5-3 is checked again. Since it is "1" this time, the third instruction will not be activated in the next third stage. Also, assembled gate 5-5
Under the control of , the data is simply shifted to the left within the shift register 5-1. Similarly, the state of the command start signal 5-3 is checked during each stage, and the above-described process is repeated.

As explained above, the conventional pipeline control method uses a special control circuit based on a complicated control algorithm.

The processing steps of each functional unit for each stage of all instructions in the CPU are all the same, and all instructions have the same operation diagram, so it is possible to perform operations ranging from simple instructions such as register-to-register transfer to memory-to-memory operations. The first major drawback is that it is difficult to apply to data processing devices with complex instructions.

In addition, since the processing time for each stage is fixed uniformly, the processing time for one stage can be extended,
The second drawback is that it is difficult to increase the amount of processing within one functional unit, and the pipeline lacks flexibility.

In particular, if the memory access time is long in the interface part with the bus, the memory reference will not be completed within the processing time of one stage, so this part may be specially removed from pipeline processing, or The third drawback is that there are various restrictions such as limiting the memory used to high-speed memory.

Furthermore, when this pipeline control method is applied to a microcomputer, a pipeline control circuit is required, which has the fourth disadvantage of not only complicating the circuit but also increasing the chip size.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a pipeline control system most suitable for microcomputers.

[Structure of the invention]

The pipeline control method according to the present invention has a plurality of functional units each performing a plurality of different processes, and the same functional unit performs different processes on the same instruction at different times depending on the processing procedure of the instruction to be executed. In order to avoid conflicts between the data of the instruction being executed and the data of the next instruction to be executed, at what processing step of the instruction being executed should the execution of the next instruction be started? a timing control means that generates a timing signal specifying a timing signal; a plurality of holding means provided corresponding to each of the plurality of functional units and holding the completion status of the processing of the functional unit; a processing start control means that sends a processing start signal to each functional unit in response to maintaining the completion state and controls each functional unit to start the next processing at the same time; The method is characterized by comprising means for starting execution of an instruction in synchronization with the processing start signal.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 7 is a block diagram of a CPU to which an embodiment of the present invention is applied.

CPU is divided according to instruction execution procedure 3
Three functional units that specialize in executing three phased basic processes: a bus interface section 7-1, an operand calculation section 7-2, an execution section 7-3, and the execution start timing of the next instruction after the instruction currently being executed. a timing storage section 7-8 as a timing control means for controlling the basic processing over all instructions, and a first, second, and third storage section as holding means for holding the completion state of the basic processing for each functional unit. Stage end flip-flop (hereinafter referred to as stage end F/
It's called F. ) 7-4, 7-5, 7-6, and an AND gate 7-7 as processing start control means for sending a start signal of the basic processing to the functional unit in accordance with the holding state of the holding means. Preparation, first,
2nd and 3rd stage end F/F7-4,7-
5 and 7-6 maintain the completed state of the basic processing, the bus interface unit 7-1 and the operand calculation unit 7- 2. Execution unit 7
-3 all simultaneously start the next basic process according to the instruction execution procedure, and also start the execution of a predetermined next instruction from the timing signal 7-8' from the timing storage section 7-8. Ru.

Note that although the timing storage section 7-8 is provided within the bus interface section 7-1 in this embodiment,
This may be provided outside the functional unit,
Further, they are provided in a distributed manner within each functional unit as necessary.

This embodiment is applied to the conventional CPU shown in FIG.
1, operand address calculation unit 7-2, execution unit 7
The three functional units No.-3 perform the same processing as each functional unit of the CPU shown in the block diagram of the conventional example in FIG.

The first stage end F/F 7-4 is set when one stage of processing by the bus interface section 7-1 is completed. 2nd stage end F/F7
-5 is set when the operand address calculation unit 7-2 completes one stage of processing. Third
The stage end F/F7-6 is 1 of the execution section 7-3.
It is set when the processing for a stage is completed.

Stage start signal 7-7' is AND gate 7-7
When this signal is inputted, the bus interface section 7-1 , operand address calculation unit 7-2,
Each functional unit of the execution section 7-3 includes a first, second,
3rd stage end F/F7-4,7-5,7-
6 and at the same time start processing for the next one stage. The timing storage section 7-8 stores timing signals set in advance so that the next signal can be started without collision.
The timing signal is sent out at a predetermined timing.

The operation diagram in Figure 8a shows the CPU based on this embodiment.
This is an operational diagram of arithmetic instructions between memories, and the processing operations for each functional unit are the same as those of the conventional example shown in Figure 2.
Identical except for the fifth stage of T _C5 . In the fifth stage of T _C5 , the execution unit 7-3 activates the next instruction in addition to the operation between the data read by the bus interface unit 7-2 and a predetermined register.

FIG. 8b is an operational diagram of a transfer instruction between registers of the CPU based on this embodiment, in which the instruction code is read by the bus interface section 7-1 during the first stage of T _D1 . During the second stage of T _D2 , the execution unit 7-3 decodes the instruction. Period execution part 7-3 of the third stage of T _D3
In addition to transferring data, it also activates the next command.

Next, with reference to the timing diagram of this embodiment shown in FIG. 9, the operation when the two instructions shown in the operation diagrams of FIGS. 8a and 8b are successively processed will be described.

At the timing of t _C1 , instruction C (inter-memory operation instruction) is activated, and at the same time, the operand address calculation unit 7-2 and the execution unit 7-3 also perform one stage of processing during the period of T _C1 . By the end of T _C1 , each functional unit has completed one stage of processing, and each functional unit has completed the first, second, and third stages, respectively.
Set 4, 7-5, 7-6. The logical product of these outputs becomes the stage start signal 7-7' by the AND gate 7-7, and at the same time, the first, second, and third stage end F/Fs 7-4, 7-5, and 7-6 are reset. The bus interface unit 7-1 performs the second stage processing corresponding to the next T _C2 .
Operand address calculation unit 7-2, execution unit 7-3
start all at once.

Continuing the above processing, in synchronization with the activation of the fifth stage of T _C5 , the timing signal 7-8 is read out from the timing storage section 7-8 as determined in advance by instruction C (inter-memory operation instruction). 8' starts execution of the next instruction D (transfer instruction between registers). At the same time, the third command in D command of T _C7
In synchronization with the activation of the th stage, as predetermined by the D instruction (transfer instruction between registers),
Execution of the next instruction E is started according to the timing signal 7-8' read from the timing storage section 7-8.

As explained above, the CPU to which one embodiment of the present invention is applied does not determine the activation timing of the next instruction by drawing a collision diagram, but even if the next instruction is activated for each instruction, Since the timing is predetermined for each instruction at a timing at which no collision occurs, the pipeline control circuit for determining the startup timing shown in Fig. 5, which was conventionally required to schedule pipeline operations, is no longer required. can be significantly simplified.

In addition, the synchronization relationship between each functional unit is not uniformly synchronized during a fixed specific period as in the past, but the processing for one stage is a unit, and the processing for one stage between each functional unit is Once all is completed, move on to the next stage. Therefore, in the design of functional units, there is increased flexibility in the processing content, and especially in the bus interface section, one stage of processing can be completed when a memory reference is completed, regardless of the memory access time. Considerable flexibility occurs in pipeline operation.

Further, since the instruction operation diagrams are not uniformly optimized but are optimized for each instruction, it can be easily applied to general-purpose data processing devices.

〔Effect of the invention〕

As explained in detail above, by adopting the above configuration, the pipeline control method of the present invention has the most suitable operation diagram for each instruction instead of the same operation diagram for all instructions as in the past, and each The synchronization relationship of functional units is based on the completion of one process in one stage, rather than a uniformly fixed period as in the past, and the start timing of an instruction is determined based on each command rather than based on a collision diagram as in the past. Since the timing at which collisions do not occur for all instructions is predefined even if the next instruction is started each time, the increase in hardware amount is kept to a minimum compared to the conventional pipeline control method. This has the effect of providing a high-speed pipeline control system that is flexible in design and has flexibility in design.

In particular, when applied to microcomputers with remarkable performance improvements, the increase in hardware amount is minimal, and compared to sequential processing, a significant improvement in processing speed can be expected, and the practical effect is most noticeable. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a CPU used in an example of a conventional pipeline control method, FIG. 2 is an operational diagram of the CPU instructions shown in FIG. 1, and FIGS.
Figure 2 is an operation diagram when the next instruction is started at each stage in the operation diagram shown in Figure 2, Figure 4 is a CPU collision diagram according to the operation diagram shown in Figure 2, and Figure 5 is the same as the one shown in Figure 2. 6 is an operational diagram showing changes in data in the pipeline control circuit of FIG. 5, and FIG. 7 is a block diagram of the pipeline control circuit of the CPU according to the operation diagram shown in FIG. CPU block diagram,
8a and 8b are operation diagrams of instructions of the CPU shown in FIG. 7, and FIG. 9 is a time chart of the CPU shown in FIG. 7. 1-1... Bus interface section, 1-2...
Operand address calculation section, 1-3...execution section,
5-1...Shift register, 5-1-0, 5-1
-1,5-1-2,5-1-3,5-1-4,5
-1-5...Register, 5-2...Shift clock, 5-3...Instruction start signal, 5-4...Initial collision data generation circuit, 5-5...Gate gate, 7-
1... Bus interface section, 7-2... Operand calculation section, 7-3... Execution section, 7-4, 7-
5, 7-6...1st, 2nd, 3rd stage end flip-flop, 7-7...AND gate, 7
-7'...Instruction start signal, 7-8...Timing signal storage section, 7-8'...Timing signal, T _A1
~T _A6 , T _B1 ~ T _B11 , T _C1 ~ T _C6 , T _D1 ~ T _D3 ... stage, t _A1 ~ t _A6 , T _C1 ~ _{t C8} ... timing.

Claims (1)

[Claims] 1 A plurality of functional units each performing a plurality of different processes, each of which is configured such that the same functional unit performs different processes at different times for the same command, depending on the processing procedure of the command to be executed. and a timing control means for generating a timing signal that specifies at which processing step of the instruction being executed the execution of the next instruction is to be started so as to prevent data of the instruction being executed from colliding with data of the next instruction. and a plurality of holding means provided corresponding to each of the plurality of functional units to hold the processing completion state of the functional unit, and in response to all of these holding means holding the processing completion state. processing start control means for sending a processing start signal to the functional units so that each functional unit starts the next processing at the same time; A pipeline control method comprising: means for starting the pipeline.