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JPS6359181B2 - - Google Patents
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JPS6359181B2 - - Google Patents

Info

Publication number
JPS6359181B2
JPS6359181B2 JP58152802A JP15280283A JPS6359181B2 JP S6359181 B2 JPS6359181 B2 JP S6359181B2 JP 58152802 A JP58152802 A JP 58152802A JP 15280283 A JP15280283 A JP 15280283A JP S6359181 B2 JPS6359181 B2 JP S6359181B2
Authority
JP
Japan
Prior art keywords
interrupt request
request signal
control device
controlled
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58152802A
Other languages
Japanese (ja)
Other versions
JPS6045865A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15280283A priority Critical patent/JPS6045865A/en
Publication of JPS6045865A publication Critical patent/JPS6045865A/en
Publication of JPS6359181B2 publication Critical patent/JPS6359181B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Description

【発明の詳細な説明】 (a) 発明の対象 本発明は情報処理装置に係り、特にハードウエ
ア的に分割された回路又は装置の接続状態を判定
する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Object of the Invention The present invention relates to an information processing device, and particularly to a method for determining the connection state of hardware-divided circuits or devices.

(b) 従来技術 従来の接続装置の判定方式として (i) サービスプロセツサー又は直接キーによつて
情報処理装置内の特定の記録回路にフラグを設
定すると言つた人手によつて接続情報を設定す
る方式 (ii) 制御装置から被制御装置にアクセス要求を出
して所定の時間が経過しても応答信号が帰つて
こない(いわゆるタイムアウト)ことによつて
未接続であることを制御装置が認識する方法 がある。(i)の方式では人手操作による接続情報
(フラグ、ルートFF等)の設定であるため誤操作
に対する保証方法に問題があつた。(ii)の方式では
所定時間待たねばならず特に未接続回路が多くな
る程時間がかかると言つた欠点があつた。
(b) Prior Art Conventional methods for determining connection devices include (i) manually setting connection information by setting a flag in a specific recording circuit within the information processing device using a service processor or a direct key; Method (ii) The control device issues an access request to the controlled device and the control device recognizes that the connection is disconnected when no response signal is returned even after a predetermined period of time has passed (so-called timeout). There is a way. In method (i), connection information (flags, route FF, etc.) is manually set, so there is a problem with the method of guaranteeing against erroneous operations. The method (ii) has the disadvantage that it requires waiting for a predetermined period of time, and it takes longer as the number of unconnected circuits increases.

(c) 本発明の目的 本発明の目的は制御装置と複数の被制御装置と
で構成される情報処理装置において、制御装置に
よつて制御されるために設けられた複数の被制御
装置又は回路からの割込み要求信号インタフエー
スをそのまま変更せずに利用して被制御装置の接
続状態を判別する方式を提供することにある。
(c) Object of the present invention An object of the present invention is to provide an information processing device including a control device and a plurality of controlled devices, in which a plurality of controlled devices or circuits are provided to be controlled by the control device. It is an object of the present invention to provide a method for determining the connection state of a controlled device by using an interrupt request signal interface from a device without changing it.

(d) 本発明の要点 本発明は被制御装置からの割込み要求信号線
を、被制御装置の接続状態の判別に利用するため
に、装置の電源ON又はシステムリセツト等によ
つてONとし該割込み要求信号を制御装置が認識
した後OFFとなるように制御することによつて
従来の割込み要求のためのインタフエースを変更
せずに容易に被制御装置の接続状態を判別できる
ようにしたものである。
(d) Key Points of the Invention The present invention turns on the interrupt request signal line from the controlled device when the device is powered on or resets the system, in order to use it to determine the connection state of the controlled device. By controlling the request signal so that it turns OFF after the control device recognizes it, the connection status of the controlled device can be easily determined without changing the conventional interface for interrupt requests. be.

(e) 発明の実施例 第1図が本発明の一実施例であつて1は制御装
置、2〜4は被制御装置、5〜7は被制御装置か
らの制御装置に対する割込み要求信号線、8〜1
0は被制御装置2〜4の制御装置1に対する接続
状態を示す接続情報レジスタ、11〜13は被制
御装置における通常の割込み要求信号線、14〜
16は論理和回路であつて、上記通常の割込み要
求信号線11〜13と上記接続状態レジスタ8〜
10の出力との論理和出力を上記割込み要求信号
線5〜7に接続する。
(e) Embodiment of the invention FIG. 1 shows an embodiment of the invention, in which 1 is a control device, 2 to 4 are controlled devices, 5 to 7 are interrupt request signal lines from the controlled device to the control device, 8-1
0 is a connection information register indicating the connection state of the controlled devices 2 to 4 to the control device 1, 11 to 13 are normal interrupt request signal lines in the controlled devices, 14 to
16 is an OR circuit which connects the normal interrupt request signal lines 11 to 13 and the connection status registers 8 to 13;
The logical OR output with the output of 10 is connected to the interrupt request signal lines 5-7.

今被制御装置の接続情報レジスタ8〜10が電
源オン又はシステムリセツト信号によつてONと
なると上記論理和回路14〜16を経由して割込
み要求信号線5〜7が付勢され制御装置に対して
夫々の被制御装置が接続されていることを通知す
る。
Now, when the connection information registers 8 to 10 of the controlled device are turned on by the power on or the system reset signal, the interrupt request signal lines 5 to 7 are activated via the OR circuits 14 to 16 and sent to the control device. to notify that each controlled device is connected.

制御装置側でこの割込み要求信号のチエツクを
行い終了したとき直ちに上記接続情報レジスタ8
〜10をリセツトするために例えば特定の命令を
被制御装置に送出する(ルートは図示せず)と被
制御装置側で該命令が受信されて上記接続情報レ
ジスタがリセツトされる。
Immediately after checking this interrupt request signal on the control device side, the connection information register 8 is
.about.10, for example, when a specific command is sent to the controlled device (route not shown), the command is received by the controlled device and the connection information register is reset.

この接続情報レジスタ8〜10はそのセツト条
件が前述の電源ON又はシステムリセツト信号に
よるだけであるので、電源ON又はシステムリセ
ツトが行われない限り再びONになることはない
ので以降の割込み要求信号線8〜10は通常の割
込み要求信号線として使用できる。
Since the connection information registers 8 to 10 are set only by the above-mentioned power ON or system reset signal, they will not be turned ON again unless the power is turned ON or the system is reset. Lines 8 to 10 can be used as normal interrupt request signal lines.

該レジスタ8〜10のリセツト方法について
は、前述のような制御装置からの命令によるだけ
でなく、制御装置1が割込み要求信号線5〜7を
通じて該信号の認識が完了すれば直ちにリセツト
できるようにハードウエアで構成しても良い。
Regarding the method of resetting the registers 8 to 10, the registers 8 to 10 can be reset not only by a command from the control device as described above, but also by the method of resetting them immediately after the control device 1 completes recognition of the signal through the interrupt request signal lines 5 to 7. It may be configured by hardware.

以上の説明から明らかなように、制御装置1は
該割込み要求信号を被制御装置の接続状態を判別
する信号と通常の割込み要求信号とに切分けて識
別制御する必要があるが、その手段そのものは本
発明の主旨とは直接関係ないのでここでは省略す
る。
As is clear from the above explanation, it is necessary for the control device 1 to distinguish and control the interrupt request signal by separating it into a signal for determining the connection state of the controlled device and a normal interrupt request signal. Since these are not directly related to the gist of the present invention, they will be omitted here.

尚割込み要求信号のインタフエースについて本
発明では1:1の割込み要求信号線としている
が、本発明の適用範囲がこれに限定されないこと
は言う迄もない。
Although the present invention uses a 1:1 interrupt request signal line for the interrupt request signal interface, it goes without saying that the scope of application of the present invention is not limited to this.

(f) 発明の効果 本発明によれば、制御装置で特定の割込み処理
を行うだけで被制御装置又は回路の接続状態を判
別できるので情報処理の高速化、高信頼化に効果
がある。
(f) Effects of the Invention According to the present invention, the connection state of a controlled device or circuit can be determined simply by performing specific interrupt processing in the control device, which is effective in speeding up information processing and increasing reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を説明する図であ
る。図において1は制御装置、2〜4は被制御装
置、5〜7は割込み要求信号線、8〜10は接続
情報レジスタを示す。
FIG. 1 is a diagram illustrating an embodiment of the present invention. In the figure, 1 is a control device, 2 to 4 are controlled devices, 5 to 7 are interrupt request signal lines, and 8 to 10 are connection information registers.

Claims (1)

【特許請求の範囲】[Claims] 1 制御装置と該制御装置によつて制御されるた
めに割込み要求信号をインタフエースとしてもつ
複数の被制御装置または回路とを備えた情報処理
装置において、前記割込み要求信号を電源ONま
たはシステムリセツト時にONにし、その割込み
要求信号を制御装置が認識した後にOFFとして
以降通常の割込み要求ができるように前記割込み
要求信号を制御し、被制御装置の接続状態を判別
することを特徴とする情報処理装置。
1. In an information processing device that includes a control device and a plurality of controlled devices or circuits that are controlled by the control device and have an interrupt request signal as an interface, the interrupt request signal is transmitted when the power is turned on or the system is reset. An information processing device that controls the interrupt request signal such that the interrupt request signal is turned ON, and after the control device recognizes the interrupt request signal, the interrupt request signal is turned OFF so that a normal interrupt request can be made thereafter, and determines the connection state of the controlled device. .
JP15280283A 1983-08-22 1983-08-22 Information processor Granted JPS6045865A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15280283A JPS6045865A (en) 1983-08-22 1983-08-22 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15280283A JPS6045865A (en) 1983-08-22 1983-08-22 Information processor

Publications (2)

Publication Number Publication Date
JPS6045865A JPS6045865A (en) 1985-03-12
JPS6359181B2 true JPS6359181B2 (en) 1988-11-18

Family

ID=15548471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15280283A Granted JPS6045865A (en) 1983-08-22 1983-08-22 Information processor

Country Status (1)

Country Link
JP (1) JPS6045865A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56145412A (en) * 1980-04-14 1981-11-12 Hitachi Ltd Interruption signal receiving circuit

Also Published As

Publication number Publication date
JPS6045865A (en) 1985-03-12

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