JPS6360581B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase difference detector of a carrier wave regeneration circuit used for regenerating a carrier wave from an N-phase phase modulated wave.

Conventionally, many inventions have been made regarding carrier wave regeneration circuits for N-phase/phase modulated waves in response to various usage situations and demands.

Typical of these are N multiplication method, inverse modulation method,
These methods include regenerative modulation, analog multiplication (Costas method), etc., but all of them have complex circuit configurations and require analog elements. For example, in the N-multiplication method, an N-multiplier is required in the inverse modulation method, in the re-modulation method, a demodulated signal and a modulator are required, and in the analog multiplication method, an analog adder is required, and these become obstacles to the demand for digitization of circuits.
In addition, in order to widen the frequency pull range in a normal phase-locked circuit, the phase difference detector is given a discriminator characteristic that is sensitive to frequency differences, and N-phase/phase error detectors are also used. Therefore, there is a demand for similar characteristics.

It has been difficult in the prior art to satisfy these two requirements with a digital circuit configuration. Here, when the intermediate frequency IF is about several MHz or less, the IF circuit can be constructed using a digital IC. Therefore, by effectively using digital ICs, a more flexible circuit configuration can be achieved compared to the above-mentioned system.

The purpose of the present invention is to configure an N-phase/phase difference detector necessary for a carrier wave regeneration circuit using only a small amount of digital elements, and also to use this configuration to expand the frequency pull range of the circuit and also to detect frequency differences. The aim is to make it easy to work as a sensitive frequency/phase difference detector.

According to the present invention, a second output having a phase different by π/2 from the first output of a carrier wave regeneration oscillator having a frequency N times that of a carrier wave is sampled at a specific phase of an input signal, and the sample value is determined in magnitude. A first sample holding circuit converts the output into a binary value and holds the output, and samples the first output at a specific phase of the input signal only when the output is one of the values, and when the other value is the first sample holding circuit. N phase/phase comprising a second sample holding circuit that continues to hold the output, and obtaining a phase error output sensitive to the frequency difference between the input signal and the N-divided signal of the carrier wave regeneration oscillator from the output of the second sample holding circuit. An error detector is obtained.

According to the present invention, a frequency difference and phase difference detector for any N phases as well as the commonly used two-phase and four-phase detectors can be configured using several ICs.

FIG. 1 a, b, c, and d show four-phase phase modulated waves converted into square waves, in which the phases are sequentially shifted by π/2. e is a sine wave having a frequency four times that of the waveforms a to d. In the figure, the zero intersection of e and a
~d The rising edge of the waveform is accurate. Here e
If it is sampled at the rising edge of a to d, the sample value will be zero regardless of any of a to d, and even if e deviates from the diagram by θorad, the sample value will be any of a to d. Regardless of Sinθo
becomes. As a result, the phase difference detection characteristics for the phase difference θe between the square wave input signals a to d and the waveform of e when frequency-divided by N are as shown in Fig. 2g, and 4
It can be seen that the phase/phase difference detection characteristics are achieved. The shape of characteristic g is essentially the same as the waveform of e.
Therefore, when e in FIG. 1 is made into a square wave as e', the phase difference detection characteristic also becomes a square wave characteristic as shown in h in FIG. 2.

FIG. 3 is a circuit diagram showing an example of an N-phase phase error detector using an IC. First, a four-phase modulated wave applied from the input terminal 100 is converted into a 0.5V square wave by the comparator 1 and outputted to the output terminal 101.
This corresponds to any one of a to d in FIG. This square wave is the CP of data latch circuit 2.
Added as read input to the terminal. On the other hand, a square-wave quadrupled carrier frequency output from the oscillator 3 is applied to the input terminal D of the data latch circuit 2. This signal corresponds to FIG. 1e'. The value of this input terminal D is identified as high potential or low potential at the time of the rise of the previous read input signal, reaches the output terminal, and is held until the next rise of the read input signal. Therefore, as is clear from the above explanation, the output from the output terminal of the data latch circuit 2 has a phase difference detection characteristic as shown in FIG. 2h.

If an analog sample and hold circuit is used in place of data latch 2 in Figure 3,
Moreover, when the output waveform of the oscillator 3 is a sine wave, the phase difference detection characteristic will be as shown in FIG. 2g from the above explanation.

Based on the above explanation, next we will look at Figures 4 and 5.
Embodiments of the present invention will be described with reference to the drawings.
FIG. 4 is a circuit diagram showing an embodiment of the present invention, and FIG. 5 is a waveform diagram explaining its operation. It is assumed that the output of the carrier wave regeneration oscillator 3 is a square wave as shown in FIG. 1(f). This signal becomes the waveform shown in FIG. 1 e' by the π/2 phase shifter 5. Since the data latch circuit shown in FIG. If we remove the gate 6, the outputs to the terminals 101 and 102 will be as shown in Figure 5
It shows the phase difference detection characteristics as follows. Now consider the function of gate 6. Here, the data latch 2 and the gate 6 forming the second sample holding circuit are logical products, and one input thereof is connected to the output of the data latch 4. For this reason, data
The read input of latch 2 can rise only when the output of data latch 4 (first sample and hold circuit) is at a high level. At other times, the output of data latch 2 will maintain its previous value. Therefore, the output of the output terminal 101 has a phase difference detection characteristic having a history characteristic as shown in FIG. 5k. This characteristic is equal to the ordinary phase difference detection characteristic shown in Figure 2h in the range θe = Mπ/2±π/4 (M is an integer of significance), so when this circuit is used in a phase-locked loop, Since the stable phase difference point is θe=M·π/2, in a steady state there is almost no difference from the case using FIG. 2h.

Now, considering the above-mentioned case when the phase-locked loop is out of synchronization, there is a history characteristic, so the phase difference between the input carrier wave and the regenerated carrier is due to the frequency difference between the input signal and the signal obtained by dividing the frequency of the oscillator output for carrier wave regeneration by 4. The waveform of the output terminal 101 is different when θe increases positively and when it increases negatively. First, when θe increases positively, the output becomes as shown in Figure 5l,
When θe increases negatively, the output becomes as shown in FIG. 5m. For waveforms l and m, the DC component has a positive value in the former and a negative value in the latter. This means that the output of the output terminal 101 serves as a binary detector for frequency differences.

If the theter latch circuit 2 in FIG. 4 is replaced with an analog sample-and-hold circuit, it will have the history characteristic shown in FIG. 2g.

As described above, according to the present invention, the N-phase frequency
A phase difference detector can be easily constructed using several digital ICs.

[Brief explanation of the drawing]

Figure 1 is a diagram for explaining the principle of N-phase phase error detection, Figure 2 is a diagram showing four-phase phase error detection characteristics, and Figure 3 is an example of an N-phase phase error detector using an IC. FIG. 4 is a block diagram showing one embodiment of the present invention, and FIG. 5 is a waveform diagram for explaining the operation of the circuit shown in FIG. 4. In the figure, 1 is a comparator, 2 is a sample circuit, 2' is a second sample holding circuit, 4 is a first sample holding circuit, 3 is an oscillator for carrier wave regeneration, and 3' is a carrier wave having a first output and a second output. Reproduction oscillators are shown.

Claims (1)

[Claims] 1. A second output having a phase different by π/2 from the first output of a carrier wave regeneration oscillator having a frequency N times that of the carrier wave is sampled at a specific phase of the input signal, and the sample value is A first sample holding circuit converts the output into a binary value depending on its magnitude and holds the output, and the first sample holding circuit samples the first output at a specific phase of the input signal only when the output is one value, and selects the other value. a second sample holding circuit that continues to hold the output when Characteristic N-phase/phase error detector.