JPS6362013B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a microcomputer, and more particularly to a microcomputer equipped with a bus release function and an interrupt control function.

[Conventional technology]

In recent years, with advances in integrated circuit technology, microcomputers (hereinafter referred to as MCUs) have appeared that are equipped with functions such as storage, interrupt control, bus release control, timer/counter, and serial transmission/reception on the same silicon substrate. However, it has come to be used for various purposes such as various control equipment. Such equipment includes
In addition to the MCU, peripheral devices such as a floppy disk controller and a display controller are added.
A DMA controller is used to transfer data between these peripheral devices and the MCU's data memory, and the MCU
DMA to transfer data at high speed without going through
transfer is known. In this case, the DMA controller receives a DMA request signal from the peripheral device and
Outputs a bus release request signal to the MCU. MCU
In response to this, it stops at an appropriate timing during processing, releases the bus, and outputs a bus use permission signal. On the other hand, the DMA controller
Check the MCU's bus permission signal and start DMA transfer. In addition, the MCU mentioned above usually has an interrupt control function, and outputs an interrupt request signal to the CPU at regular intervals to cause the CPU to execute a predetermined process. So-called interrupt processing is known. These interrupts include maskable interrupts that can be masked by instructions from the CPU, and non-maskable interrupts that cannot be masked. The latter non-maskable interrupt is normally used as a top-priority interrupt in an emergency such as an abnormality in an external device or a runaway program.

In conventional MCUs, even during the above-mentioned non-maskable interrupt processing, the bus release request signal causes the processing to stop at an appropriate timing. Alternatively, even if a non-maskable interrupt request is made while the bus is being released, the interrupt process will not be executed as long as the bus release request signal continues. Therefore, there is a drawback that the highest priority interrupt processing in an emergency is interrupted or forced to wait.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks, to suppress the bus release function during the highest priority interrupt processing, and to execute the highest priority interrupt processing without having to wait even when the bus release is permitted. The object of the present invention is to provide a microcomputer that is possible, avoids bus contention, and has increased versatility.

[Structure of the invention]

A microcomputer according to a first aspect of the present invention includes an edge detection circuit that inputs an interrupt request signal and outputs a one-shot pulse, and a first edge detection circuit that is set by inputting the one-shot pulse and reset by an interrupt return command. an interrupt control circuit having a flip-flop and an interrupt holding circuit for temporarily holding the interrupt request signal; a delay means for delaying the output of the first flip-flop; and a suppression for suppressing the bus release request signal by the delay means. a second flip-flop which is set or reset by a bus release request signal sent to the CPU at a predetermined timing via the suppressing means; and the output of the second flip-flop and the first flip-flop. and a bus release control circuit having means for suppressing a bus release permission signal.

A microcomputer according to a second aspect of the present invention includes an edge detection circuit that inputs an interrupt request signal and outputs a one-shot pulse, and a first edge detection circuit that is set by inputting the one-shot pulse and reset by an interrupt return command. an interrupt control circuit having a flip-flop and an interrupt holding circuit for temporarily holding the interrupt request signal; a delay means for delaying the output of the first flip-flop; and a suppression for suppressing the bus release request signal by the delay means. and a second flip-flop which is set or reset by a bus release request signal sent to the CPU at a predetermined timing via the suppressing means, and the output of the second flip-flop and the first flip-flop. The bus release control circuit includes means for suppressing a bus release permission signal and a selection circuit for selecting a delay time of the delay means.

[Explanation of Examples]

FIG. 1 is a block diagram of an embodiment of the first invention.

In this embodiment, an edge detection circuit 2 inputs an interrupt request signal NMI and outputs a one-shot pulse.
1 and the first flip-flop 23 which is reset by the interrupt return instruction RETI which is set by the input of this one-shot pulse and the interrupt request signal.
The interrupt control circuit 13 has an interrupt hold circuit 22 that temporarily holds NMI, and a D-type flip-flop 29 as a delay means for delaying the output of the first RS type flip-flop 23. A gate circuit 27 serves as a suppressing means for suppressing the bus release request signal HOLD, and the bus release request signal HOLD is sent to the CPU 12 at a predetermined timing via the gate circuit 27.
an RS-type second flip-flop 24 that is set or reset by an AND gate 26 as a means for suppressing the bus open permission signal HOLDA by the output of the second flip-flop 24 and the output of the first flip-flop 23; The bus release control circuit 14 has a bus release control circuit 14.

Next, the operation of this embodiment will be explained using the operation timing diagram of FIG. 2.

When the interrupt request signal NMI is input, the edge detection circuit 21 outputs a one-shot pulse and sets a flip-flop (hereinafter referred to as F/F) 23. As a result, the AND gate 26 is prohibited. The F/F 29 receives the output of the F/F 23, and the AND gate 27 is disabled after a delay, so the AND gate 25 is also disabled. Therefore, even if the bus release request signal HOLD becomes high level (hereinafter referred to as "1"), the bus release permission signal HOLDA remains at low level (hereinafter referred to as "0"), and the bus is not connected to another bus. Do not open to controller. Further, the timing control circuit 31 is not affected at all. On the other hand, execution of the interrupt process is suspended by the interrupt suspension circuit 22 until one instruction being executed by the CPU 12 is completed.

When the instruction being executed ends, interrupt processing is started and the instruction is executed according to a predetermined processing procedure. At the end of interrupt processing, interrupt return instruction RETI
The process returns to the process before the interrupt process. At this point, the F/F23 uses the interrupt return instruction RETI.
It is reset and the AND gate 26 becomes valid.
After a delay, the AND gates 27 and 25 also become valid, and the bus release request signal HOLD is output to the timing control circuit 3.
1, the F/F 24 is set at a timing determined by the CPU 12, and the bus release permission signal HOLDA becomes "1". As a result, the controller outputting the bus release request signal HOLD gains control of the bus, and DMA transfer and the like are executed. Therefore, it is possible to suppress bus release requests during the highest priority non-maskable interrupt processing.

FIG. 3 is an operation timing diagram when an interrupt request signal is input while the bus is open in this embodiment.

When the interrupt request signal NMI is input, the edge detection circuit 21 outputs a one shot pulse and the F/
F23 is set. As a result, the AND gate 26 is immediately inhibited, and the bus release permission signal HOLDA is
becomes “0”. At this point, and gate 2
7 is valid, so the CPU 12 is in the bus open state. On the other hand, the DMA controller, etc. that outputs the bus release request signal HOLD cannot release the bus immediately even if the bus release permission signal HOLDA becomes "0", and releases the bus after one cycle of transfer is completed. . The microcomputer (MPU) 11 is
Since the interrupt processing is started with a delay of the F/F 29 delay time, bus contention can be avoided.
Further, after executing the interrupt processing, the MCU 11 returns by an interrupt return instruction RETI. At this point F/F23
is reset, the bus release permission signal becomes "1" again, and the DMA controller etc. obtains the right to use the bus, similar to the explanation in FIG.

FIG. 4 is a block diagram of a bus release control circuit portion according to an embodiment of the second invention.

Since the second invention is the same as the embodiment shown in FIG. 1 except for the bus release control circuit, only the bus release control circuit 14' will be described.

In the second invention, a selection circuit 51 and a multi-bit D-type flip-flop 52 are used as means for selecting the delay time of the D-type flip-flop 24 as means for delaying the output of the first flip-flop 23 of the interrupt control circuit 13. Transistor 53~
A switch circuit consisting of 55 circuits is added. The selection circuit 51 makes it possible to select the delay time of the output of the first flip-flop 23 in accordance with the response time of the DMA controller or the like. That is, the selection circuit 51 selects one of the transistors 53, 54, and 55 as a switch circuit.

〔Effect of the invention〕

As explained in detail above, according to the invention, it is possible to suppress the bus release function during top-priority interrupt processing, making it possible to perform high-speed interrupt processing. Also, the highest priority interrupt processing can be executed without having to wait. Furthermore, since the delay time can be selected depending on the response time of the controller, etc., bus contention can be avoided and a highly versatile microcomputer can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the first invention, FIGS. 2 and 3 are operation timing diagrams of the embodiment shown in FIG. 1, and FIG. 4 is an embodiment of the second invention. FIG. 3 is a block diagram of a bus release control circuit portion of the device. 11...Microcomputer, 12...CPU,
13... Interrupt control circuit, 14, 14'... Bus release control circuit, 21... Edge detection circuit, 22... Interrupt hold circuit, 23... R-S type first flip-flop,
24...R-S type second flip-flop, 25,
26, 27...AND gate, 28...Inverter,
29, 30...D-type flip-flop, 31...timing control circuit, 51...selection circuit, 52...D-type flip-flop, 53, 54, 55...transistor, HOLD...bus release request signal, HOLDA...bus release permission signal, NMI...distribution Interrupt request signal, RETI...Interrupt return instruction.

Claims (1)

[Scope of Claims] 1. An edge detection circuit that inputs an interrupt request signal and outputs a one-shot pulse, a first flip-flop that is set by input of the one-shot pulse and reset by an interrupt return command, and the interrupt an interrupt control circuit having an interrupt holding circuit for temporarily holding a request signal; a delay means for delaying the output of the first flip-flop; a suppressing means for suppressing the bus release request signal by the delay means; and the suppressing means. A second flip-flop is set or reset by a bus release request signal sent at a predetermined timing from the CPU via the CPU, and the bus release permission signal is generated by the output of the second flip-flop and the output of the first flip-flop. A microcomputer characterized in that it includes a bus release control circuit having means for suppressing the opening of the bus. 2. An edge detection circuit that inputs an interrupt request signal and outputs a one-shot pulse, a first flip-flop that is set by the input of the one-shot pulse and reset by an interrupt return command, and temporarily suspends the interrupt request signal. an interrupt control circuit having an interrupt circuit; a delay means for delaying the output of the first flip-flop; and a suppressing means for suppressing the bus release request signal by the delay means; a second flip-flop which is set or reset by a bus release request signal sent at the same timing; means for suppressing the bus release permission signal by the output of the second flip-flop and the output of the first flip-flop; and the delay means. A microcomputer comprising: a selection circuit for selecting a delay time; and a bus release control circuit.