JPS638503B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a microcomputer, and more particularly to a microcomputer equipped with a bus release function and an interrupt control function.

[Prior art]

In recent years, with the advancement of integrated circuit technology, microcomputers have appeared that are equipped with various functions on the same silicon substrate, such as storage devices, interrupt control, bus release control, timer counter serial transmission and reception functions, and various control devices. It has come to be used for a variety of purposes. In order to improve the processing capacity of such control equipment, so-called multiprocessor systems are known that use a plurality of microcomputers. In this multiprocessor system, a configuration in which some storage devices and peripheral devices are shared between microcomputers is common. In this case, since a plurality of microcomputers access shared storage devices and peripheral devices via a common bus, competition occurs among the microcomputers regarding the use of these devices. Therefore, when using the bus, it outputs a bus release request signal to other microcomputers, confirms that it has obtained the right to use the bus, and then starts using the bus. On the other hand, the microcomputer that receives the bus release request signal stops at an appropriate timing during processing, releases the bus, and outputs a bus use permission signal to other microcomputers.

In addition, the microcomputer mentioned above is
Usually, it is equipped with an interrupt control circuit, and
Outputs an interrupt request signal to the CPU (central processing unit),
2. Description of the Related Art So-called interrupt processing is known in which a predetermined process is executed or a certain process is executed in response to an interrupt request signal from the outside. These interrupts include maskable interrupts that can be masked by instructions from the CPU, and non-maskable interrupts that cannot be masked. The latter non-maskable interrupt is normally used as a top priority interrupt in case of an emergency such as an abnormality in an external device or a runaway program.

In conventional microcomputers, even when the above-mentioned non-maskable interrupt processing is being executed,
Since the bus release request signal causes the process to stop at an appropriate timing during the process, there is a drawback that the highest priority interrupt process in an emergency is interrupted, making it impossible to take sufficient measures in an emergency.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly versatile microcomputer that can eliminate the drawbacks of the prior art and suppress the bus release function during top-priority processing.

[Structure of the invention]

The microcomputer of the present invention includes an interrupt control circuit and a bus release control circuit whose function is suppressed by a release control signal from the interrupt control circuit.

[Explanation of Examples]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of the present invention.

Reference numeral 1 designates a microcomputer according to the present invention, which includes an interrupt control circuit 2 and a bus release control circuit 3 whose function is suppressed by a release control signal 5 from the interrupt control circuit 2. Furthermore, 4 is
6 is an interrupt request signal, 7 is a bus release request signal, and 8 is a bus release permission signal.

FIG. 2 is a block diagram showing essential parts of an embodiment of the present invention.

21 is an edge detection circuit for the interrupt request signal 6; 22
is an interrupt holding circuit that temporarily holds the interrupt request signal 6;
23 and 28 are set-reset type flip-flops (hereinafter referred to as RS-F/F), and 24 is a D-F/F/F/F/F.
F, 25 and 26 are AND gates, 27 is an inverter, and 29 is a timing control circuit.

Next, the operation of this embodiment will be explained using the time chart shown in FIG.

When the interrupt request signal 6 shown in FIG. 3 is input to the interrupt control circuit 2, the edge detection circuit 21 outputs a one-shot pulse signal 10, and the RS-
Set F/F23. As a result, the open control signal 5 becomes high level, the AND gate 25 is prohibited, and even if the bus release request signal 7 becomes high level, the output of the AND gate 26 is low level, and therefore, the RS-F/F 28 is not set. So,
The bus release permission signal 8 remains at a low level and the bus is not released.

On the other hand, execution of the interrupt process is suspended by the interrupt suspension circuit 22 until one instruction being executed by the CPU 4 is completed. When the instruction being executed ends, interrupt processing is started, and after execution of predetermined processing, an interrupt return command signal 9 returns to the processing prior to the interrupt processing. At this point, RS-F/F23
is reset by the interrupt return command signal 9, and the interrupt control signal 5 becomes low level, so the AND gate 25 is enabled and the timing signal 11 outputted via the timing circuit 29 at the predetermined timing of the CPU 4 is activated. , and gate 26
Since the output of the bus becomes high level and the RS-F/F 28 is set, the bus release permission signal 8 becomes high level.

Therefore, according to this embodiment, it is possible to suppress bus release requests during processing of the highest priority non-maskable interrupt, so it is possible to prioritize interrupt processing and speed up processing. can.

FIG. 4 is a block diagram showing the main parts of another embodiment of the present invention.

In this embodiment, the open control signal 5 output from the RS-F/F 23 of the interrupt control circuit 2 in the embodiment shown in FIG.
Command signal 12, 1 from CPU 4 (see Figure 1)
RS-F/F31 that can be reset with 3 steps
The logical AND with the output of is taken as the open control signal 5',
The signal is output to the bus release control circuit 3.

Therefore, according to this embodiment, RS-F/F23
It becomes possible to enable or disable the output of the bus release control signal 5, that is, the release control signal 5, and it is possible to switch whether or not to permit the bus release function during interrupt processing.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, by adopting the above-described configuration, it is possible to suppress the function of the bus open circuit during processing of the highest priority interrupt, which is useful for dealing with emergencies, etc. Very effective. It is also possible to give priority to the bus release function over interrupt processing, making it possible to provide a highly versatile microcomputer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a block diagram showing essential parts of an embodiment of the present invention, and FIG. 3 is for explaining the operation of the embodiment of FIG. 2. FIG. 4 is a block diagram showing the main parts of another embodiment of the present invention. 1... Microcomputer, 2... Interrupt control circuit, 3... Bus release control circuit, 4... CPU,
5, 5', 6-13... Signal, 21... Edge detection circuit, 22... Interrupt pending circuit, 23, 24, 2
8, 31...flip flop, 25, 26, 3
0...AND gate, 27...Inverter, 29
...Timing control circuit.

Claims (1)

[Claims] 1. A microcomputer comprising an interrupt control circuit and a bus release control circuit whose function is suppressed by a release control signal from the interrupt control circuit.