JPS6362149B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sine wave detection circuit, and particularly to a sine wave detection circuit in which an input signal is a data signal or a sine wave other than a data signal (for example, as an echo suppressor cancellation signal) in a data communication modulation/demodulation device. This invention relates to a sine wave detection circuit used for determining whether a signal such as a 2100 [Hz] sine wave is used.

In demodulators used for data communications, etc.,
Everything other than the data signal is the same as noise, and it is necessary to determine whether the received input signal is a data signal or other noise. In particular, in data terminals that use regular telephone lines, the sine wave signals used to activate and release the echo suppressor are also transmitted and received via the same line.
It is necessary to distinguish these from data signals. When the noise level is sufficiently lower than the data signal level, it can be identified by the received input level. In addition, even when the noise level is high, if the frequency spectrum is random, the demodulator's eyes will not open, so it can be distinguished from data signals by monitoring the degree of eye opening. .

However, when a single frequency noise such as a sine wave is demodulated as a received input, the sine wave of a specific frequency opens the demodulator's eyes and becomes indistinguishable from data. For example, for a modem with a transmission rate of 4800 bits/second (according to CCITT Notice V27)
It uses an 8-phase phase modulation method with a carrier frequency of 1800 [Hz] and a modulation rate of 1600 [Hz], so
Frequency (600,
When a sine wave of 800,...3000 [Hz]) is input to the demodulator, the demodulator's eyes may open, making it impossible to distinguish it from the input of a data signal.

Therefore, in conventional demodulators, a specific frequency (for example, an echo suppressor release signal of 2100 [Hz]) is used.
Considering only the sine wave of , the specific frequency is removed by a rejector or extracted by a narrow band pass waver for discrimination. Therefore, when using two or more sine wave signals, there is a drawback that filters for each frequency are required. Another drawback is that it is not possible to remove or identify single frequency noise other than a specific frequency.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sine wave detection circuit which eliminates the above-mentioned drawbacks and can distinguish a single frequency signal from a data signal regardless of its frequency.

The sine wave detection circuit of the present invention has a first delay means which delays an input signal by a predetermined time, and a second delay means which delays an output signal by the predetermined time.
a first complex multiplier for complex-multiplying the conjugate signal of the input signal and the output signal from the first delay means; and a conjugate signal of the output signal from the first delay means and the second complex multiplication means for complex multiplication by the output signal from the second delay means;
subtracting means for outputting the difference between the output signal from the first complex multiplication means and the output signal from the second complex multiplication means; and squaring means for outputting the square of the absolute value of the output signal of the subtraction means; a 4th power means for outputting the fourth power of the absolute value of the input signal; a multiplication means for multiplying the output signal from the 4th power means by a predetermined constant; and an output signal from the multiplication means and the squaring means. level comparing means for comparing the amplitude with the output signal of the output signal and outputting a binary signal in response to the comparison result; detecting the binary signal from the level comparing means at a constant cycle; An up-down counter that counts up or down in response to a state, and when the content of the up-down counter exceeds a predetermined upper limit value, the up-down counter is initialized and a first pulse is output to increase the up-down counter. a comparison means for initializing the up-down counter and outputting a second pulse when the content of the down counter exceeds a predetermined lower limit value; and a comparison means for discriminating between the first pulse and the second pulse. and a discriminator that outputs a binary signal in response to the result.

Next, the present invention will be explained in detail with reference to the drawings.

The figure is a block diagram showing one embodiment of the present invention.

Delay circuits 1 and 2 are connected in series,
The input signal a to the delay circuit 1 is given to the conjugate circuit 3, and the output signal d of the conjugate circuit 3 and the delay circuit 1
The output signal b is applied to the complex multiplier 5. Furthermore, the input signal b to the delay circuit 2 is input to the conjugate circuit 4.
The output signal e of the conjugate circuit 4 and the output signal c of the delay circuit 2 are applied to a complex multiplier 6. The output signals f and g from the complex multipliers 5 and 6 are applied to a subtracter 7;
The output signal h is output by the squaring circuit 8 as an absolute value square value signal i.

The input signal a is also applied to a 4th power circuit 9, and the output signal j of the 4th power circuit 9 is multiplied by a constant α by a multiplier 10 to become an output signal k.

The level comparison circuit 11 outputs the output signal i of the squaring circuit 8.
and the output signal k of the multiplier 10, and depending on the magnitude relationship between the amplitudes of the output signals k and i, when (amplitude of signal k)>(amplitude of signal i), it is set to "1", and (signal k When (amplitude of signal i)<(amplitude of signal i), "0" is output as output signal l.

The output l signal of the level comparison circuit 11 is applied to an up-down counter 12. When the signal l is "1", the up-down counter 12 increments by a fixed amount at a fixed cycle, and when the signal l is "0", it subtracts by a fixed amount at a fixed cycle. The counter output m of the up-down counter 12 is input to comparators 13 and 14. The coparator 13 compares the counter output m with a predetermined upper limit value _MMAX , and when m> _MMAX , outputs "1" as a counter clear pulse o and outputs "1" as a set pulse r. do. Further, the comparator 14 compares the counter output m with a predetermined lower limit value M _MIN and determines that m<
When M _MIN is reached, "1" is output as the counter clear pulse n and the reset pulse q is output.
outputs "1" as The counter clear pulses o and n are logically summed by an OR circuit 15, and when the output signal p of the OR circuit 15 becomes "1", the up-down counter 12 is initialized. The flip-flop 16 is set and reset by the set pulse r and the reset pulse q, respectively, and "1" and "0" are obtained at the terminal B as outputs of the flip-flop.

The input signal a given from the input terminal A is a complex baseband signal obtained by demodulating the reception input of the data communication modulation/demodulation device (it may be a digital signal or an analog signal), and the delay circuits 1 and 2, the complex Multipliers 5 and 6, subtracter 7, etc. are all circuits that process complex numbers (or complex quantities). Further, the delay times of delay circuits 1 and 2 are both τ and are equal. Conjugate circuits 3 and 4 are circuits that take the complex conjugate of input signals a and b, respectively.

A subtracter 7 separately subtracts the real and imaginary parts of the output signals f and g of the complex multipliers 5 and 6, respectively. The squaring circuit 8 is, for example, a subtracter 7
This circuit outputs the square value of the absolute value of the input signal h by adding the square value of the real part and the square value of the imaginary part of the output signal h. Also, the quadratic circuit 9
is a circuit that combines a squaring circuit and a multiplier that squares this output, that is, a circuit that outputs the fourth power of the absolute value of the input signal a, and the multiplier 10 outputs the fourth power of the absolute value of the input signal a.
This is a circuit that multiplies by a fixed constant α.

Next, the operation of this embodiment will be explained. Input signal a is a function of time t, and if this is S(t), one input signal d of multiplier 5 is S ^* (t)
(Here, "*" represents a complex conjugate). On the other hand, the output signal b of the delay circuit 1 becomes (S(t-τ). Therefore, the output f of the multiplier 5 becomes f=S ^* (t)・S(t-τ). Similarly Then, the output g of the multiplier 6 is g=S ^* (t-τ)・S(t-2τ), so the output h of the subtractor 7 is h=S ^* (t)・S(t- τ) −S ^* (t−τ)・S(t−2τ) The output h becomes 0 when the input signal a is a sine wave, and also when some white noise is mixed into the sine wave. The value is close to 0 even when
When the input signal is a data signal whose phase changes randomly, the value of the output h will vary greatly over time.

Further, the output j of the 4th power circuit 9 is as follows: j=|S(t)| ⁴ (“||” represents an absolute value). This output j has a constant value when the input signal a is a sine wave, but has a value that fluctuates greatly over time when it is a data signal.

That is, when the input signal a is a sine wave, if S(t)=Ae ^jwt , the output h of the subtracter 7 becomes h=0. Therefore, the output i of the squaring circuit 8 is i=0. Further, the output j of the 4th power circuit 9 is j=A ⁴ . Therefore, if the multiplier α of the multiplier 10 is selected as a positive number, k=αA ⁴ >0, and the output l of the level comparison circuit 11 is always
It becomes “1”.

However, when the input signal a is a data signal whose phase changes randomly, the level comparison circuit 1
Since both the input signals i and k to the level comparison circuit 1 fluctuate largely and randomly over time t, the level comparison circuit 1
The output l of 1 is a value that randomly takes "1" and "0". Therefore, the output l of the level comparison circuit 11
By appropriately filtering, it is possible to distinguish between a sine wave and a data signal.

Up-down counter 12 and comparator 1
3 and 14, a flip-flop 16, and an OR circuit 15 constitute a random walk filter.
By appropriately selecting M _MAX and the lower limit M _MIN , when the input l to the up-down counter 12 is a continuous "1" or the ratio of "1" to "0" is very large, the flip-flop 16
The output S of is always "1", indicating that the input signal a is a sine wave. On the other hand, when the input l is "1" and "0" at random, the output S is always "0". , operates to indicate that the input signal a is not a sine wave. The output i of the squaring circuit 8 does not become 0 when the input signal a is a sine wave containing white noise, etc., and takes a magnitude corresponding to the power of the white noise, etc., but the multiplier α of the multiplier 10 is adjusted appropriately. By selecting a large value, when components such as white noise are sufficiently small compared to the sine wave component of input signal a, the relationship between (amplitude of signal k) > (amplitude of signal i) between inputs k and i of the level comparison circuit 11 is established. Similarly, sine wave detection can be performed.

Furthermore, the above-mentioned operation only requires that the input signal a be a sine wave, and is independent of its frequency. Therefore, even if the line uses a plurality of sine waves, it is sufficient to include only one sine wave detection circuit, and as in the past, a band filter or the like corresponding to each of the sine wave signal frequencies is provided. There's no need.

Furthermore, the above operation is basically independent of the absolute level of input signal a;
There is no requirement that AGC be involved. Further, the above-mentioned configuration can be performed entirely by digital processing, so it can be easily configured using an LSI or a microprocessor.

As described above, the present invention enables discrimination between data signals and sine wave signals using a simple circuit configuration without requiring a band waver or the like corresponding to the number of sine wave signals as in the past. Since it does not depend on the absolute level of the input signal, it has the effect of operating stably even when the input signal rises and when the input signal has a level hit.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. 1...Delay circuit, 2...Delay circuit, 3...conjugate circuit,
4... Conjugate circuit, 5... Complex multiplier, 6... Complex multiplier, 7... Subtractor, 8... Square circuit, 9... Quadrature circuit,
10... Multiplier, 11... Level comparison circuit, 12... Up/down counter, 13... Comparator, 14
...Comparator, 15...OR circuit, 16...Flip-flop.

Claims (1)

[Claims] 1. A first delay means for delaying the input signal by a predetermined time; a second delay means for delaying the output signal from the first delay means by a time equal to the predetermined time; and a second delay means for delaying the input signal by a time equal to the predetermined time. and a conjugate signal of the output signal from the first delay means and an output from the second delay means. a second complex multiplication means for complex multiplying a signal, a subtraction means for outputting a difference between an output signal from the first complex multiplication means and an output signal from the second complex multiplication means, and the subtraction means a squaring means for outputting the square of the absolute value of the output signal from the input signal; and a squaring means for outputting the fourth power of the absolute value of the input signal;
a multiplication means for multiplying the output signal from the quadrupling means by a predetermined constant; comparing the amplitudes of the output signal from the multiplication means and the output signal from the squaring means; a level comparison means for outputting a value signal; an up-down counter for detecting a binary signal from the level comparison means at a constant cycle and counting up or down in response to the state of the binary signal at this time; When the content of the up-down counter exceeds a predetermined upper limit value, the up-down counter is initialized and a first pulse is output, and when the content of the up-down counter exceeds a predetermined lower limit value, the up-down counter is initialized and a first pulse is output. a comparison means for initializing a counter and outputting a second pulse;
1. A sine wave detection circuit comprising a discriminating means for discriminating between a pulse and a second pulse and outputting a binary signal in response to the discrimination result.