JPS6362779B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interprocessor communication system in an information processing system or the like in which a plurality of processors are connected to a serial bus such as a linear bus or a ring bus.

Conventionally, inter-processor communication in information processing systems, etc. in which multiple processors are connected to a serial bus involves first transferring data between a sending/receiving buffer managed by a communication control program, and then transferring data from the same buffer to the user program area in response to an interrupt, etc. A method of transferring this data is common. Figure 1 shows
This figure shows an example of this conventional inter-processor communication system, in which 10 and 11 are processors, 12 is a task, 13 is a communication buffer, 14 is an inter-processor connection device, 15 is a serial bus (ring bus),
16 is a communication window.

To explain the operation of FIG. 1, the transmission data from each task 12 is temporarily stored in the communication buffer 13 managed by the communication control program. When the inter-processor connection device 14 is empty, the communication buffer 13
If there is data to be transmitted, the processor takes out one piece of data to be transmitted from the buffer and makes a communication request to the inter-processor connection device 14 through the communication window 16. The transmitted data is stored in the communication buffer 13 of the communication destination processor via the serial bus 15. The communication destination processor starts the corresponding task based on the communication destination task number in the data. The task 12 reads the transmission data stored in the communication buffer 13 into its own data work area.

The disadvantage of the method shown in FIG. 1 is that the communication processing overhead due to transmission/reception buffer management, interrupt processing, data transfer, etc. increases, especially as the traffic becomes higher and the longer the data is transferred.

On the other hand, in channel-coupled one-to-one processor-to-processor communication, the logical communication bus (logical bus) between the communication source and communication destination tasks is directly connected.
By associating tasks with one of a plurality of subchannels provided in the interprocessor connection device and performing direct communication between tasks via the subchannel, the above disadvantages can be eliminated, and the processor can be connected while the channel is in an idle state. A method is known in which high-speed communication is possible by performing multiplex communication corresponding to each subchannel using a communication waiting function that allows an interconnection device to wait for communication from the other party corresponding to each subchannel. FIG. 2 is a diagram explaining this system, in which 17 is a subchannel, 18 is an interprocessor connection device, and 19 is a subchannel of the interprocessor connection device, and the other features are the same as in FIG.

To explain the operation of FIG. 2, a communication request from each task 12 is made by a communication waiting command (dedicated command), and the task 17 puts the channel of the communication source processor into an idle state in the subchannel 19 of the interprocessor connection device 18 corresponding to each subchannel. We met at the hotel. After that, when synchronization is achieved by issuing a communication waiting command to the subchannel from the communication destination processor, the waiting command is read, read, and
Starts data transfer by chaining with the WRITE command. According to this method, it is possible to eliminate asynchronous interrupts to the communication destination at startup.

By the way, the channel-coupled 1 shown in FIG.
If the communication method between a pair of processors is directly applied to an n-to-n communication system in which n processors communicate with each other, n(n-1)/2 inter-processor connection devices will be required, resulting in high costs. It has drawbacks such as lack of expandability and flexibility.

In order to eliminate these drawbacks, the present invention has proposed a multiplex communication function using multiple subchannels in one-to-one processor communication using a serial bus.
In addition to being expanded and applied to n-to-n communication, this expansion suppresses the increase in software creation burden and communication processing overhead, and realizes n-to-n communication with the same communication procedures and communication efficiency as one-to-one communication. This paper proposes a hardware support mechanism for this purpose. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 shows an embodiment of the n-to-n processor communication system according to the present invention. In FIG. 3, each task 12 in the processors 10, 11 is in one-to-one correspondence with the subchannels 17, 21 of the processor and interprocessor connection device 20 by a communication control program. Inter-processor connection device 20
For each subchannel, set the communication destination processor address, the communication destination interprocessor connection device subchannel address, and the subchannel usage status.
It has a memorizing function. A plurality of processors are connected to a serial bus 15 via an interprocessor connection device 20.
are connected to and can communicate with each other.

Now, when applying a multiplex communication method that allows direct transfer between tasks using multiple subchannels to an n-to-n communication system via a serial bus, the communication source task corresponds to one subchannel in the own processor-to-processor connection device. , the communication destination task is associated with one subchannel in the communication destination interprocessor connection device, and a correspondence relationship is established between the communication source interprocessor connection device subchannel selected above and the communication destination interprocessor connection device subchannel. , it is necessary to communicate. In addition, for communication, the subchannel address of the inter-processor connection device (hereinafter referred to as
It is necessary to specify the communication destination processor address (hereinafter referred to as DA), the communication destination inter-processor connection device subchannel address (hereinafter referred to as SBA(D)) as communication address information.

On the other hand, in a one-to-one communication system, the correspondence between tasks and subchannels is the same as in the n-to-n communication system, but there is no need to specify DA and SBA (D), and naturally SBA (S) and SBA (D) It is also unnecessary to make a correspondence with

Furthermore, the current channel specifications require device address word (DAW) as communication address information.
In many cases, only one can be specified in the IOD address area, and when targeting the serial bus connection of these existing processors, if SBA (S) is specified in the above DAW, DA and SBA (D) are I/O It is necessary to specify it using command data, or to issue multiple commands in succession and specify the IOD address area information of the DAW as a whole.

From the above, the main problems in n-to-n communication systems are SBA (S) at the time of communication startup,
The communication overhead required for DA and SBA(D) specification, and the incompatibility with conventional one-to-one communication interfaces regarding communication address specification, and the fact that SBA(S) and
Managing correspondence with SBA(D) through software control requires a large burden on software creation.

Therefore, in the present invention, communication is performed in the following two steps, and a function is supported to automatically establish a correspondence relationship between SBA(S) and SBA(D) on the interprocessor connection device on the receiving side. This paper proposes a method that can solve the above problems.

[First stage operation] The correspondence between SBA(S) and DA+SBA(D) is stored in the management table (hereafter CTBL) in the interprocessor connection device.
). This CTBL storage method can be roughly divided into the following two types.

(A) When the correspondence between SBA (S) and DA + SBA (D) is established by software control; CTBL setting dedicated command (referred to as CMDA)
The corresponding relationship is stored in CTBL. Figure 4 shows how to implement CTBL settings. In FIG. 4, 10 and 11 are processors A and B, respectively, 12 is a task, 20 is an inter-processor connection device, and 30 is an inter-processor connection device 20.
CTBL, DSB are device status bytes, CE/DE
indicates channel termination/device termination, during CTBL
STATUS represents the state of CTBL.

Assuming that subchannel a of processor A and subchannel b of processor B are associated with a communication source task and a communication destination task, respectively, when processor A issues a command (CMDA) to subchannel a, DA (=
B) and SBA(D) (=b) are sent and stored in CTBL.

On the other hand, on the processor B side, subchannel b
When issuing a command (CMDA) to CMDA
As data, the inter-processor connection device is DA.
(=A) and SBA(D) (=a) are sent and stored in CTBL.

In addition, as another implementation example of the above CTBL settings,
CTBL of the communication destination inter-processor connection device by communication frame from either processor side.
There is also a way to set .

(B) When the correspondence between SBA(S) and DA+SBA(D) is not established; Communication path establishment instruction command (referred to as CMDB)
is issued, the inter-processor connection device on the receiving side is activated through communication, automatically selects an unused subchannel, and the SBA(S) obtained by the selection is
The correspondence relationship between DA + SBA (D) is set in the CTBL of the receiving side inter-processor connection device, and the correspondence relationship is notified to the communication source inter-processor connection device by the response frame of the command, and the communication source inter-processor connection device is notified of the correspondence relationship.
Also set in CTBL.

Figure 5 shows the format of the communication frame used in this inter-processor communication, where F is the flag sequence (01111110), DA is the communication destination processor address, SA is the communication destination processor address, and C
is the bus control command, SBA is the interprocessor connection device subchannel address (D is the communication destination, S
is the communication source), and FCS is the frame check sequence. The command or command response is specified in the data section.

FIG. 6 is a diagram illustrating the communication path establishment operation in this case. In FIG. 6, 40 is a communication frame, 50 is a subchannel address (special address designation) of a connecting device between processors on the receiving side when a communication path establishment instruction is issued, and 60 is a communication link between software higher than the communication control program. The control information 70 such as logical paths necessary for
Response to CMDB, 80 is an attention interrupt that notifies the occurrence of an asynchronous interrupt, 90 is the destination processor address specified in the received frame +
This command (referred to as SENSE command) reads the interprocessor connection device subchannel address and the contents of the frame data section. Other details are the same as in Figure 4.

As another example, when issuing CMDB, do not specify # in the data of this command, and on the receiving side, if it is a CMDB command, SBA(D) (=#)
It is also conceivable to regard this as an instruction to establish a communication path regardless of the situation, and to perform the same operations as in the implementation example shown in FIG. 6 thereafter.

[Second stage operation] According to the communication request from each task, the DAW's communication address information is sent as communication address information in the same way as in the case of one-to-one communication.
In the IOD address area, the communication control program specifies the SBA(S) assigned to the task and starts communication. When the inter-processor connection device accepts the communication start, in the first step SBA (S) and DA + SBA (D) are connected.
The CTBL for which the correspondence relationship is set is indexed, and the corresponding
The DA corresponding to SBA(S) and SBA(D) are set in a communication frame as communication destination address information, and the frame is stored in the transmission buffer. Thereafter, communication frames are transmitted and received in accordance with the inter-processor communication control procedure at the data link level via the serial bus.

FIG. 7 is a block diagram of an embodiment of an inter-processor connection device to which the present invention is applied. Hereinafter, the communication operation will be explained in more detail using FIG. 7, dividing it into transmission and reception.

Communication operation during transmission PAR 204 is a processor address register that holds the unique address of the corresponding processor, and the corresponding address value is always set. CMD2
05, DAR206 is the command from the host device and the processor address (DA) of the communication destination, respectively.
and a register that holds the interprocessor connection device subchannel address (SBA(D)).

I/O interface control unit (IOIC) 203
Under the control of the controller, a command from the host device and a startup subchannel address are set in the CMD 205 and SBA 210, respectively, via the input bus (INBUS) 201, and the communication control unit (CC) 211 is activated. CC
211 checks the contents of CMD205,
In the case of a CTBL setting command or a communication bus establishment instruction command, CTBL and DAR 206 in the subchannel (SBCH) 208 of DA and SBA (D), respectively.
Request the IOIC203 to configure the settings. IOIC203
In accordance with this request, among the data of the command,
The parts determined in advance for the above address specification are respectively set to CTBL in SBCH208 and DAR206.
Set to .

If the command is not a CTBL setting command or a communication path establishment instruction command, the SBCH 208 is indexed using the address indicated by the SBA 210, and the index result is sent to the subchannel access output register (SBOR) 209.
Output to. CC211 examines the contents of SBOR209 and selects the subchannel (=SBA) shown in SBA210.
If the DA and SBA(D) corresponding to (S)) are set normally, the corresponding address of the communication destination is set in the DAR 206 from the SBOR 209. SBOR20
If the output result of step 9 is other than the above, the state is
Set in DSB 213 and report that to IOIC 203.

The state of the subchannel indicated by SBA 210 after the SBCH 208 index is written to the SBCH 208 via the subchannel input register (SBIR) 207.

CC211 will send PAR204, CMD205, and DAR20 if these communication startups are performed normally.
6. Start up the SBA 210 and IOIC 203, send the data necessary to create a transmission frame to the transmission buffer (SBUF) 217, and create the frame.
Connect to send queue.

Thereafter, it is sent to the serial bus 223 under the control of the transfer control unit (TRC) 219.

Communication operation during reception The frame received from the serial bus 222 is
Receive buffer (RBUF) under control of TRC219
218, especially the first byte of the data part (commands, response information, etc. are stored) and the frame's
Information in the SBA(D) area is set in the data register (DR) 214 and subchannel address register (SAR) 216, respectively, and the CC 211 is activated.
CC211 checks the contents of DR214, and in the case of a communication path establishment instruction command, checks the contents of SAR216, and checks whether the contents are the same as the contents set in advance in the special subchannel address register (SSAR) 215. , if they are the same, the subchannel automatic selection mechanism (SAS mechanism)
212 is used to select an available free subchannel for the communication, and the result is set in the SBA 210.

After that, the SA of the frame from RBUF218,
SBA(S), SBA2 of CTBL in SBCH208
In the subchannel address area shown in 10, respectively.
Write as DA, SBA(D), and after confirming normal writing with SBOR 209, write communication path establishment to SBCH 208 via SBIR 207. It also creates a frame to respond to the communication source to establish a communication path.
Store in SBUF217.

If the contents of SAR and SSAR are not the same, and
If the content of DR214 is not a communication path establishment instruction command, the content of SAR216 is sent directly to SBA.
210, checks the status of the subchannel area indicated by the contents of SBA2 of SBCH 208, creates a predetermined response frame according to the type of command, and stores it in SBUF 217. Also, the state of the subchannel is reset via the SBIR 207.
If it is necessary to have an interface with the host device due to the contents of DR214, etc., please indicate this in IOIC2.
Report on 03.

The above subchannel automatic selection mechanism (SAS mechanism)
The operation flow of 212 is shown in FIG.

Although the above description has described the positioning of the interprocessor connection device as a device under a channel, it is also possible to implement this device in a form that includes a channel function.

As explained above, according to the present invention, in channel-coupled one-to-one processor communication,
CTBL and
n-to-n via serial bus using SAS mechanism
By applying it to communication, there is an advantage that highly efficient n-to-n processor communication can be realized with a communication procedure that is almost equivalent to the one-to-one communication described above, with less burden on software creation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional communication system between n to n processors via a serial bus, FIG. FIG. 4 is a block diagram of an embodiment of a communication system between n to n processors via a Figure 5 is a diagram showing the communication frame format sent and received between processors on a serial bus, Figure 6 is a diagram explaining a communication path establishment method using the SAS mechanism, and Figure 7 is a diagram showing the connection between processors to which the present invention is applied. A configuration diagram of an embodiment of the device,
Figure 8 shows the interprocessor connection device in Figure 7.
It is an operation flow diagram of the SAS mechanism. 10, 11...Processor, 12...Task,
13... Communication buffer, 14, 18, 20...
Inter-processor connection device, 15...serial bus,
16...Communication window, 17...Subchannel, 1
9, 21...Subchannel of interprocessor connection device.

Claims (1)

[Claims] 1. In an information processing system in which multiple processors are interconnected via a serial bus and each processor can communicate with other processors on an equal basis, an inter-processor connection device is provided between a channel that controls the input/output operations of the processors and the serial bus. established,
This connection device is provided with a plurality of subchannels that have a one-to-one correspondence with a subchannel that is a unit of channel multiplexing operation, and also includes a communication destination processor address and a communication destination processor address for communication using the subchannel for each subchannel. Means for storing instruction information from a channel such as subchannel address, input/output command, data length, and the subchannel status, and a means for storing the subchannel address of the interprocessor interconnection device started from the channel, means for reading the address and subchannel address of the interprocessor connection device of the communication destination from the storage unit; means for assembling a frame for interprocessor communication based on the instruction information; means for sending the frame to the serial bus; and means for sending the frame from the serial bus. When receiving the frame, the frame content is checked, and if the content is an instruction to select a subchannel on the receiving side for establishing a communication path, the usage status of each subchannel in the storage unit is checked, and an empty subchannel is selected. Select
The processor address of the communication partner and the subchannel address of the interprocessor connection device corresponding to the selected subchannel are written in the storage section, the subchannel is placed in the communication path establishment state, and a response frame for establishing the communication path is assembled, and the communication between the channel and the processor is performed. Means for activating an interface control unit with a connecting device, when the sender of the receiving side subchannel selection instruction receives a response frame to the instruction, storing the communication source inter-processor connecting device subchannel address established on the receiving side in the storage unit. In the case of a frame other than the receiving side subchannel selection instruction or its response frame, the interface control unit between the channel and the processor connection device is activated corresponding to the subchannel specified in the received frame, and the frame instruction is a pair of processor-to-processor connection devices between a sending side and a receiving side, comprising means for processing according to the contents, assembling the processing result as a response frame to the frame, and updating the state of the subchannel area of the storage section; An inter-processor communication method characterized by multiplexing data transmission and reception by providing communication paths corresponding to subchannels.