JPH0823854B2 - Control device - Google Patents

Description

DETAILED DESCRIPTION [Table of Contents] Outline Industrial field of application Conventional technology Problems to be solved by the invention Means for solving problems Problems Working examples Effects of the invention [Summary] Multiple items classified by function It is composed of functional units of
A device having a shared memory accessed from the functional unit, the control device for controlling access from each functional unit to prevent the port of the shared memory from being continuously occupied by the functional unit in which the failure has occurred. The adapter detects the port to which the functional unit in which the failure has occurred is connected, and sends a command to the port to release the connection with the functional unit in which the error has occurred, and prevents the processing capacity of the device from decreasing. For this purpose, by combining the command analysis means for analyzing the command sent by the service adapter for each functional unit and the source address determined for each functional unit held based on the instruction of the command analysis means, And an address sending means for sending the address of the above-mentioned port to solve the command sent by the service adapter notified of the failure occurrence from the functional unit. In response to the instruction of the instruction analysis means, the service adapter, based on the address transmitted by the address transmission means, releases the coupling to the port to which the faulty functional unit is coupled instead of the faulty functional unit. It is configured to send commands.

[Industrial applications]

The present invention relates to an apparatus having a shared memory which is configured by a plurality of functional units classified by function and which is accessed from the functional unit. In particular, a port of the shared memory that controls access from each functional unit has a failure. The present invention relates to a control device for preventing the functional unit from being continuously occupied.

Higher performance of central processing unit in information processing system,
Since the speedup is remarkable, and of course the number of data processing is large, many files are needed to store the data, and it is essential that this file can be used by multiple central processing units. I came.

By the way, for example, a disk device used as an external storage device of an information processing system is indispensable as a system resident file and a virtual storage page file, and is also used as a large number of data files for storing enormous information. To be done.

By the way, it is becoming difficult for a disk controller for fulfilling such a demand to control and manage the disk device with a large number of channel paths by one processor. Therefore, what was considered was a functional unit corresponding to a channel, a functional unit corresponding to a disk device, a shared memory accessed by these functional units, a functional unit for managing all functional units, and each functional unit. There is a disk control device that is configured by functional units that perform unit failure analysis and that connects each functional unit with a common bus.

In a disk controller configured with such functional units, there is contention for access to the memory shared by each functional unit, so multiple ports that control this access are provided in the shared memory, and access is performed in accordance with the order of access. By allocating this port, the contention is efficiently avoided, but it is necessary to prevent the allocated port from being occupied by the occurrence of a failure in each functional unit.

[Conventional technology]

 FIG. 3 is a block diagram illustrating a conventional technique.

FIG. 3 shows an example of a disk control device composed of functional units. Reference numeral 1 denotes a shared memory, which is connected to the common bus 12 via the ports 2, 3, and 4, and is accessed by another functional unit connected to the common bus 12 to transfer data.

2 to 4 are ports, 5 is an automatic allocation control circuit,
As shown in the figure, the ports 2, 3 and 4 have the same configuration.

Therefore, the operation of the port 2 will be mainly described.
A command sent by another functional unit from the common bus 12, an address of the functional unit indicating the destination of the command, and an address for the common memory 1 indicating the destination are input.

For example, a command for instructing writing or reading of data is input to the decoder 15, an address indicating a destination is input to the comparison circuit 13, and the address is compared with the port address held by the port address 14. If they match, the decoder 15 is effective. Is transmitted.

When the decoded contents become valid, the decoder 15 outputs "1".
To the AND circuit 16. Since the flip-flop 18 is not set at the initial stage, "1" is sent to the AND circuit 16, and the AND circuit 16 sends "1" to the AND circuit 17. Therefore, the AND circuit 17 sends "1" sent from the decoder 15 to the flip-flop 18, and the flip-flop 18 is set to send "1" to the AND circuits 26 and 27 of the automatic allocation control circuit 5, “0” is sent to the circuit 16.

Therefore, the AND circuit 17 again sets “0” to the flip-flop 18
However, the flip-flop 18 sends "1" to the AND circuits 26 and 27 until it is reset.

The address register 20 is enabled by the AND circuit 16 sending "1", stores the address of the functional unit that accessed the port 2, and sends it to the comparison circuit 21. The comparator circuit 21 sends the address of the functional unit to the common bus 12 every time the functional unit requests data transfer.
When the address of the functional unit input from 12 matches the address stored in the address register 20, "1" is ANDed.
To the circuit 22.

Therefore, the AND circuit 22 sends "1" sent from the decoder 15 to the data buffer 23 and the address register 25, enables the data buffer 23 and the address register 25,
As will be described later, the address of the shared memory 1 input to the address register 25 is sent out via the command buffer 24,
Shared memory 1 and common bus 12 via data buffer 23
Data transfer between the two.

When the functional unit that has accessed the port 2 and transferred the data to the shared memory 1 sends a command to release the connection with the port 2 after the data transfer is completed, the decoder 15 decodes this command.

The comparison circuit 21 compares the address with the address of the address register 20 and, since the addresses match, the decoder 15 validates the decoded command, so that the decoder 15 sends "0".
Therefore, the NOT circuit 19 sends "1" to the flip-flop 18 and resets the flip-flop 18, so that the flip-flop 18 sends "1" to the AND circuit 16 again.

Also, the address register 20 is reset and erases the stored address of the functional unit when the decoder 15 outputs "0".

The decoders 15 of the ports 3 and 4 other than the port 2 also send "1" to the AND circuits 16 of the ports 3 and 4 when the decoded contents become valid, and the flip-flops 18 of the ports 3 and 4 respectively.
Each send "1", the AND circuit 16 of port 3
Sends "1" to the AND circuit 26 of the automatic allocation control circuit 5, but since the flip-flop 18 of the port 2 has not yet sent "1" to the AND circuit 26 of the automatic allocation control circuit 5 at this time, AND The circuit 26 does not send "1" to the AND circuit 17 of port 3.

Therefore, the address register 20 of the port 3 is not enabled, and since the AND circuit 27 of the automatic allocation control circuit 5 is still sending “0”, the address register 20 of the port 4 is not enabled either. , The address of the functional unit that has accessed the port is stored only in the address register 20 of the port 2.

When the port 2 is occupied and there is a functional unit that accesses the port subsequently, even if the decoder 15 of the port 2 decodes and outputs "1", the AND circuit 16 of the port 2
Since the flip-flop 18 of the port 2 is sending "0", the AND circuit 16 of the port 2 is still sending "0".

Therefore, the address register 20 of the port 2 does not store the address of the new functional unit.

However, in the AND circuit 26 of the automatic allocation control circuit 5, since the flip-flop 18 of port 2 is sending "1", the decoder 15 of port 3 is sending "1" and the AND circuit 16 of port 3 is When "1" is sent, "1" is sent to the AND circuit 17 of port 3.
To the address register 20. Therefore, the address register 20 of the port 3 is enabled to store the address of the new functional unit.

At the same time, the flip-flop 18 of the port 3 sends “1” to the AND circuit 27 of the automatic allocation control circuit 5. Therefore, when the decoder 15 of the port 4 sends "1", the flip-flop 18 of the port 4 sends "1" to the AND circuit 27 in the same manner as described above.

At this time, the flip-flop 18 of the port 2 also sends "1" to the AND circuit 27, so the AND circuit 27 sends "1". Therefore, the address register 20 of the port 4 is enabled and stores the address of the functional unit that next accessed the port.

Then, the flip-flop 18 of the port 4 sends "1" to the common bus 12 and outputs a busy signal indicating that all of the ports 2 to 4 are in use.

The address of the shared memory 1 indicating the destination is stored in the command buffer 24. When the AND circuit 22 sends "1" as described above, the address register 25 is enabled and the address of the shared memory 1 is sent. Therefore, the data sent by the functional unit following the address indicating the destination is transferred to the shared memory 1 via the data buffer 23 enabled by "1" sent by the AND circuit 22 as described above, and written in the shared memory 1. Get caught. When reading data from the shared memory 1, the data read out to the data buffer 23 at the address transmitted by the address register 25 is
It is sent to the common bus 12.

In this way, the ports 2, 3 and 4 control access to the shared memory 1 from other functional units according to the priority order defined by the automatic allocation control circuit 5.

Channel adapters 7 and 8 are configured as shown in FIG. 5, and the processor 30 operates by reading a program from the control memory 31, and transmits a start I / O command from a channel which is a host device via the interface circuit 28. The common bus control circuit 29 performs the reception and data transfer between the channels.
To send an address (all the port addresses are the same address) to the ports 2 to 4 via the common bus 12 to perform data transfer with the shared memory 1.

When a failure occurs inside the channel adapters 7 and 8, a detection circuit (not shown) notifies the service adapter 11 of the failure via a dedicated signal line.

The device adapters 9 and 10 are constructed as shown in FIG. 5, and the processor 30 reads out a program from the control memory 31 to operate and sends a command to the disk device via the interface circuit 28 to communicate with the disk device. Data transfer between the two, and controls the common bus control circuit 29 to
An address (all the port addresses are the same address) is sent to ports 2 to 4 via 12 and data transfer with the shared memory 1 is performed.

When a failure occurs inside the device adapters 9 and 10, the detection circuit (not shown) notifies the service adapter 11 of the failure through a dedicated signal line.

Reference numeral 6 denotes a resource manager, which is configured as shown in FIG. 6, and the processor 33 reads a program from the control memory 32 to operate and controls the common bus control circuit 34 to control the common bus 12
Receive all start I / O commands from the channels sent by the channel adapters 7 and 8 via the
This start I / O command is centrally managed.

And channel adapter 7,8 for each start I / O instruction
And instruct processing to the device adapters 9 and 10. Further, the control information for each received all start I / O commands, the control information for each channel path, and the control information for each disk device are centrally stored, and other functional units are passed through the RAM access control circuit 36. It is possible to access the RAM 35 and read the above control information.

A service adapter 11 is constructed as shown in FIG. 7, and the processor 38 operates by reading a program from the control memory 37, and a dedicated signal from the channel adapters 7 and 8 and the device adapters 9 and 10 via the peripheral device control circuit 40. A failure occurrence notified by a line is detected, and a command for switching, for example, a function unit is sent to the common bus 12 via the common bus control circuit 39.

With the disk controller configured in this way, for example,
When the channel adapter 7 is selected from the channels of the higher-level device and receives the start I / O command, it is coupled via the common bus 12 with, for example, the device adapter 9 connecting the designated disk device according to the instruction of the resource manager 6. Then, the data is transferred to and from the disk device. In this case, since the channel adapter 7 and the device adapter 9 temporarily store the data to be transferred to the shared memory 1, the address of the shared memory 1 including the address of the port is sent out and assigned according to the priority order determined by the automatic assignment control circuit 5. The shared memory 1 is accessed via one of the ports 2-4.

[Problems to be solved by the invention]

As described above, conventionally, the channel adapters 7 and 8 and the device adapters 9 and 10 occupy one of the ports 2 to 4 and access the shared memory 1 in the priority order determined by the automatic allocation control circuit 5. For example, if the channel adapter 7 occupying the port 2 becomes an obstacle and does not send the command to release the connection with the port 2, the address of the channel adapter 7 stored in the address register 20 of the port 2 is not erased. .

Therefore, the port 2 does not receive access from other functional units, the usage efficiency of the port 2 is reduced, and the number of ports that can be used by other functional units is also reduced, so that the processing capability of the disk control device is reduced. There's a problem.

The present invention provides a command for the service adapter 11 to detect a port to which a functional unit in which a failure has occurred is coupled based on a notification that a fault has occurred, and to release the combination with the functional unit in which the fault has occurred in the port. The purpose is to improve the port usage efficiency and prevent the disk controller from degrading the processing capacity.

[Means for solving problems]

 FIG. 1 is a block diagram of the principle of the present invention.

The service adapter 11 is connected to the functional unit 41 via the dedicated signal line.
Alternatively, when a failure occurrence notification is received from 42, a command is sent to the instruction analysis means 44 of the functional unit 41 or 42 that has notified the failure occurrence via the information extraction signal line, and the address sending means 43 causes the failure occurrence function. The unit address and the destination address (port address common to each port) sent to the shared memory 1 are sent to the common bus 12.

When the service adapter 11 receives the address of the functional unit in which the failure has occurred and the destination address from the common bus 12, the normal address of the functional unit and the address of the functional unit indicating the source are transmitted in the same manner as the command frame sent when the data transfer ends. , The destination adren and the data for instructing the uncoupling at the end of the data transfer are sent to the common bus 12.

Port 2 or 3 that received this command frame
As described with reference to FIG. 4, since the address of the functional unit stored in the address register 20 is erased, the connection with the functional unit in which the failure has occurred can be released.

[Action]

With the above-described configuration, the command analysis unit 44 analyzes the command transmitted by the service adapter 11 and instructs the address transmission unit 43 to transmit the source address and the destination address. It becomes possible to send the decoupling associated with the end of the data transfer to the port 2 or 3 instead of the functional unit that has occurred, release the port 2 or 3 occupied by the functional unit in which the failure has occurred, and process the disk controller. It is possible to prevent a decrease in efficiency.

〔Example〕

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

FIG. 2 is provided in the common bus control circuit 29 shown in FIG. 5, and additionally has a decoder 45 and a signal line 51.

The source address register 48 stores the address assigned to the functional unit itself, and when the destination address sent from each of the other functional units input from the common bus 12 is stored in the destination address register 50, this destination The comparison circuit 49 compares the address with its own address, and if they match, it recognizes that it is the other party to which data should be transferred, and enables the data buffer 46 to transfer the data.

Further, the address of the functional unit of the other party to which the data is to be transferred is stored in the destination address register 47 and sent to the common bus 12.

As described with reference to FIG. 1, the service adapter 11 sends a command to the decoder 45 via the information extraction signal line when the failure is notified from the functional unit. The decoder 45 decodes this command and sets "1" to the destination address register 47.
Then, the source address register 48 and the destination address register 47 are enabled, and the stored source address and destination address are transmitted to the common bus 12.

Therefore, as described in FIG. 1, the service adapter 11
Uses the source address and the destination address indicating the functional unit in which the failure has occurred, and releases the binding of the occupied port in place of the functional unit in which the failure has occurred.

〔The invention's effect〕

As described above, according to the present invention, instead of the functional unit in which the service adapter has failed, the port in which the functional unit remains connected is released, so that the processing efficiency of the device can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, FIG. 3 is a block diagram illustrating a conventional technique, and FIG. 4 is a port and automatic allocation control. FIG. 5 is a block diagram showing an example of a circuit, FIG. 5 is a block diagram showing an example of a channel adapter and a device adapter, FIG. 6 is a block diagram showing an example of a resource manager, and FIG. 7 is a block diagram explaining an example of a service adapter. Is. In the figure, 1 is a shared memory, 2, 3 and 4 are ports, 5 is an automatic allocation control circuit, 6 is a resource manager, 7 and 8 are channel adapters, 9 and 10 are device adapters, 11 is a service adapter,
12 is a common bus, 13, 21, 49 is a comparison circuit, 14 is a port address, 15, 45 is a decoder, 16, 17, 22, 26, 27 are AND circuits, 18 is a flip-flop, 19 is a NOT circuit, 20, 25 is an address register, 23 and 46 are data buffers, 24 is a command buffer, 28 is an interface circuit, 29, 34 and 39 are common bus control circuits, 30, 33 and 38 are processors, 31, 32 and 37 are control memories, 35
Is RAM, 36 is a RAM access control circuit, 40 is a peripheral device control circuit, 41 and 42 are functional units, 43 is an address sending means, 44 is an instruction analyzing means, 47 is a destination address register, 48 is a source address register, and 50 is a source address register. Is the destination address register.

Claims (1)

[Claims] 1. A functional unit (41) (42) classified by function.
And a plurality of ports for controlling the access to the shared memory for temporarily storing the data transferred between the functional units by combining the access with the functional unit that requested the access, separately from the access from other functional units. (2) (3),
A service adapter (11) that detects the occurrence of a failure in the functional unit (41) (42) and sends a command for information collection,
In the control device connected to the common bus (12), an instruction analysis means (4) for analyzing the command transmitted by the service adapter (11) for each of the functional units (41) (42).
4) and the functional unit (41) based on the instruction from the instruction analysis means (44).
An address sending means (43) is provided for sending a source address set for each (42) and an address of the port (2) (3) to which the functional unit (41) (42) is connected. When the service adapter (11) is notified of the occurrence of a failure by one functional unit, the service adapter (11) sends a command to the instruction analysis means (44) of the functional unit that has notified the occurrence of the failure, and receives and analyzes the command. In response to the instruction of the instruction analysis means (44), the service adapter (11) receives the source address and the port address transmitted by the address transmission means (43), Instead, in the same procedure that the functional unit executes in order to release the binding with the port at the end of the data transfer in the normal process, the source address is sent to the port to which the faulty functional unit is bound. And a control device characterized by transmitting a command for canceling the connection with the address of the port.