JPS6362898B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a master slice type semiconductor integrated circuit having a gate array, and particularly to improvements in its input/output buffer cells.

FIG. 1 shows an input/output buffer cell of a conventionally proposed master slice type semiconductor integrated circuit, and the area inside the dashed line 100 is the input/output buffer cell. Reference numeral 101 denotes an external pad, which is used to connect the semiconductor integrated circuit and an external circuit by bonding. 102 is an input buffer amplifier; 103 is an output of the input buffer amplifier 102 and an internal logic gate cell 20 of the semiconductor integrated circuit;
104 is an output buffer amplifier capable of tri-state (high resistance) operation, and 105 is a terminal for connecting the input of the output buffer amplifier 104 to a certain part of the internal logic gate cell 200. Logic gate connection terminal 106 for output buffer amplifier 104
A signal for controlling the output of the amplifier 104 to a tri-state state (high resistance state) is used when the amplifier 104 is used in tri-state operation.
107 is an output buffer connection terminal of the output buffer amplifier 104, 108 is a pad connection terminal of the external pad 101, and 109 is an input buffer connection terminal of the input buffer amplifier 102. ，
By connecting 108 and 109, the external pad 101
can be used for input only, output only, or bidirectional use. In other words, when terminals 107 and 108 are connected, external pad 101 becomes output-only, and when terminals 109 and 108 are connected, external pad 101 becomes
are input only, terminals 107, 108, 109
When all are connected, the external pad 101 becomes bidirectional.

FIG. 2 shows an example of a semiconductor integrated circuit using two buffer cells shown in FIG. are connected outside the integrated circuit.

Conventionally, the input/output buffer cells of master slice type semiconductor integrated circuits are as described above, in which one or a set of predetermined buffer cells is prepared in advance for one external pad. cannot use buffer cells that correspond to other external pads. Therefore, when a single external circuit signal requires two buffer cells, the wiring must be connected outside the integrated circuit as shown in FIG. 2, making the external wiring complicated. Further, when the wiring is connected as shown in FIG. 2, the input buffer amplifier 102 is not used, and the external pad 101 and buffer amplifiers 102 and 104 cannot be used effectively.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional circuit. By providing general-purpose wiring in advance within the buffer cell, the correspondence between the buffer cell and external pads can be fluidized, and wiring outside the integrated circuit can be easily performed. Provided is a semiconductor integrated circuit having an input/output buffer cell that simplifies the process, and also allows the input buffer amplifier and output buffer amplifier, which were not used in the conventional method, to be used for other external pads, thereby making it possible to effectively use the buffer cells and external pads. It is intended to.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows an input/output buffer cell according to an embodiment of the present invention, in which 110, 111
112 and 113 are feedback terminals used to connect these terminals 110 and 111 to buffer and pad connection terminals 107, 108, and 109; , 131 are the terminals 110 and 1
12 and terminals 111 and 113, and is a fixed feedback wiring for connecting the output of the output buffer amplifier 104 or the input of the input buffer amplifier 102 to each part of the internal logic gate 200 in a feedback manner.

FIG. 4 shows an example of a semiconductor integrated circuit using the input/output buffer cell shown in FIG.
When a is used as an input-only pad, the output buffer connection terminal 107 of the unused output buffer amplifier 104 is connected to the feedback terminal 112, and the logic gate connection terminal 110 and the logic gate of the second buffer cell 100b are connected. Connection terminal 110
By connecting the feedback terminal 112, output buffer, and pad connection terminals 107 and 108 of the second buffer cell 100b, the external pad 1 of the second buffer cell 100b is connected.
01b can be used as an output-only pad. or,
The remaining unused input buffer amplifier 102 can be used for other purposes by connecting the feedback terminal 113 and the input buffer connection terminal 109.

In addition, in FIG. 4, the pad connection terminal 108 of the second buffer cell 100b is further connected to the input buffer connection terminal 109 or the feedback terminal 113.
By connecting to the external pad 101b
It can also be used as a two-way external pad.

In addition, in the above embodiment, the general-purpose wiring 120, 1
Although the case where there are two 31s has been described, it is also possible to have one or three or more.
Furthermore, the case has been described in which the output buffer amplifier 104 is capable of tri-state operation and further includes the input buffer amplifier 102.
The output buffer amplifier 104 may not have tri-state operation, or may have a buffer cell configuration without the input buffer amplifier 102.

Further, in the above application example, the case where two buffer cells are used has been described, but the same effect can be obtained when three or more buffer cells are used.

Further, although the feedback wiring is fixed in the above embodiment, it does not necessarily have to be fixed, and may be wired in the slicing process if necessary.

As described above, according to the present invention, a general-purpose circuit that can connect an internal logic gate cell or other buffer cell to an external pad, an input buffer connection terminal of an input buffer amplifier, or an output buffer connection terminal of an output buffer amplifier is provided. Since the feedback wiring is provided inside the input/output buffer cell, wiring for external circuits can be simplified, and buffer amplifiers that were previously unused can be used for other purposes. This has the effect of making effective use of external pads and buffer cells.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an input/output buffer cell of a conventional master slice type semiconductor integrated circuit, FIG. 2 is a circuit configuration diagram of a semiconductor integrated circuit using the buffer cell of FIG. FIG. 4 is a circuit diagram of the input/output buffer cell according to the embodiment. FIG. 4 is a circuit diagram of a semiconductor integrated circuit using the buffer cell described above. 100... Input/output buffer cell, 101... External pad, 102... Input buffer amplifier, 103...
Logic gate connection terminal, 104... Output buffer amplifier, 105... Logic gate connection terminal, 106... Logic gate connection terminal, 107... Output buffer connection terminal, 108... Pad connection terminal, 109... Input buffer connection terminal, 110, 111... Logic Gate connection terminal, 112, 113... Feedback terminal, 120, 1
31...Return wiring. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. In a master slice type semiconductor integrated circuit having internal logic gate cells arranged in an array and a group of input/output buffer cells arranged around the group of gate cells, input and output buffer amplifiers and feedback wiring are provided. A plurality of input/output buffer cells are arranged, and an external pad is provided corresponding to each of the plurality of buffer cells, and the output (or input) of the output (or input) buffer amplifier of a certain cell is connected to the feedback wiring of the cell, A semiconductor integrated circuit characterized in that the cell is connected to an external pad provided corresponding to the other cell via an internal wiring connected to the other cell and a feedback wiring of the other cell. circuit.