JPS6363930B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a timeout detection method using a TOD (Time Of Day) clock and an interval timer.

[Conventional technology and problems]

Machine language instructions are executed by a microprogram, and the time it takes to execute a machine language instruction is determined by the number of steps in the microprogram. However, if a microprogram jumps to the wrong address during execution or an error occurs during interrupt processing, the computer will be unable to execute the next machine language instruction no matter how long it takes, and the computer will hang. To prevent such situations from occurring, the execution time of machine language instructions is monitored by hardware, and when the monitoring time is exceeded, a machine check interrupt is generated or a system is installed to notify maintenance personnel of the occurrence of an error. A timeout detection circuit is provided. Conventional timeout detection circuits have their own counters, but the counters require a relatively large amount of material. For example, if the machine clock is 120 ns, the counter needs 8 bits or 10 bits to count 1 ms.
Requires a bit flip-flop.

[Purpose of the invention]

The present invention is based on the above considerations, and includes:
Using the computer's inherent hardware,
Moreover, it is an object of the present invention to provide a timeout detection method that can always perform timeout detection reliably.

[Structure of the invention]

Therefore, the timeout detection method of the present invention is a timeout detection method in which timeout is detected using either a TOD clock or an interval timer, and when the TOD clock is not stopped, the TOD clock is When the TOD clock is stopped, the timeout is detected using the interval timer.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

The figure is a block diagram of one embodiment of the invention. In the figure, 1 is the TOD clock and 2 is the interval clock.
Timer, 3 is TOD stop instruction flip-flop, 4 to 7 are AND circuit, 8 is OR circuit, 9
indicates a NOT circuit, and 10 and 11 indicate flip-flops, respectively. Also, SEL0 to SEL
2 indicates a selection signal.

TOD clock 1 and interval timer 2 are
This is something that computers usually have. To update the contents of TOD clock 1, a set clock command is issued. Then, the TOD clock 1 is temporarily stopped, its contents are updated to the desired value, and then started. The TOD stop instruction flip-flop 3 outputs a signal to stop the TOD clock 1, and a logic "1" indicates a stop, and a logic "0" indicates a start.
Repeated pulse signal every 1ms from TOD clock 1,
A repetitive pulse signal every 16 ms and a repetitive pulse signal every 256 ms are taken out. interval·
Timer 2 repeatedly outputs a pulse signal every 3.3ms. The repetitive pulse signal every 1 ms is supplied to one input of the AND circuit 4, the repetitive pulse signal every 16 ms is supplied to one input of the AND circuit 5, and the repetitive pulse signal every 256 ms is supplied to one input of the AND circuit 6.
A repeating pulse signal every 3.3 ms from the interval timer is supplied to one input of the AND circuit 7. The selection signal SEL0 is supplied to the other input of the AND circuit 4, and
The selection signal SEL1 is supplied to the other input of the circuit 5, and the selection signal SEL is supplied to the other input of the AND circuit 6.
2 is supplied to the other input of the AND circuit 7.
The output of TOD clock stop instruction flip-flop 3 is supplied. When a microprogram corresponding to one machine language instruction is executed, first
A BOP (Beginning of operation) signal is generated, and finally an EOP (End of operation) signal is generated. The output signals of the AND circuits 4 to 7 and the BOP signal are input to the OR circuit 8. OR circuit 8
The output of is applied to the clock terminals of flip-flops 10 and 11. An inverted version of the BOP signal is applied to the upper input of flip-flop 9,
A BOP signal is applied to the lower input of flip-flop 9. The upper output of flip-flop 10 is applied to the upper input of flip-flop 11.

Now, it is assumed that the selection signal SEL0 is logic "1", the other selection signals are logic "0", and the TOD clock 1 is not stopped. Under such conditions, a pulse signal repeating every 1 ms is output from the OR circuit 8. If the BOP signal is left at logic "0", the first pulse signal causes a flip.
Flop 10 outputs a logic "1" and on the second pulse signal flip-flop 11 outputs a logic "1". A logic "1" output of flip-flop 11 indicates that a timeout error has occurred. The machine language instruction is executed successfully,
If the BOP signal is generated at time intervals of less than 1 ms, the output of flip-flop 11 will never be a logic "1".

When the TOD clock 1 stops, the OR circuit 8 outputs a repetitive pulse signal from the interval timer 2 every 3.3 ms. Under these conditions, flip-flop 11 will never output a logic "1" if the BOP signal is generated at a time interval of less than 3.3 ms. Furthermore, TOD clock stop instruction flip/flop 3 is TOD clock 1.
It outputs logic ``1'' even when it is stopped due to an error or the like.

〔Effect of the invention〕

As is clear from the above description, the timeout detection method of the present invention has the advantage that it requires only a small amount of equipment and can also detect a hang state of the computer when executing a set clock instruction.

[Brief explanation of drawings]

The figure is a block diagram of one embodiment of the invention. 1...TOD clock, 2...Interval timer, 3...TOD stop instruction flip-flop, 4 to 7...AND circuit, 8...OR circuit,
9...NOT circuit, 10 and 11...flip-flop.

Claims (1)

[Claims] 1 A timeout detection method in which timeout is detected using either the TOD clock or an interval timer, and when the TOD clock has not stopped, timeout is detected using the TOD clock, and the TOD clock A timeout detection method characterized in that when the timeout is stopped, timeout detection is performed using the interval timer.