JPS6364899B2 - - Google Patents
Info
- Publication number
- JPS6364899B2 JPS6364899B2 JP57010534A JP1053482A JPS6364899B2 JP S6364899 B2 JPS6364899 B2 JP S6364899B2 JP 57010534 A JP57010534 A JP 57010534A JP 1053482 A JP1053482 A JP 1053482A JP S6364899 B2 JPS6364899 B2 JP S6364899B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode pattern
- electronic component
- substrate
- lsi chip
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は基板に形成した電極パターンにLSIチ
ツプをボンデイングする電子部品の構造に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of an electronic component in which an LSI chip is bonded to an electrode pattern formed on a substrate.
従来のこの種電子部品の構造は第１図及び第２
図に示す通り、基板１に形成した電極パターン２
の上に図示の如くLSIチツプ４を載置し、半田バ
ンプ３のところで該チツプとパターンを電気的に
接続するとともに、基板１とLSIチツプとの隙間
に遮光用樹脂５を流し込んでのち、該チツプをボ
ンデイング樹脂６にて封入している。 The structure of conventional electronic components of this type is shown in Figures 1 and 2.
As shown in the figure, an electrode pattern 2 formed on a substrate 1
Place the LSI chip 4 on top of the chip as shown in the figure, electrically connect the chip and the pattern at the solder bumps 3, and pour the light-shielding resin 5 into the gap between the board 1 and the LSI chip. The chip is sealed with bonding resin 6.
然し乍ら、上記従来の電子部品の構造では非常
に狭い隙間に遮光用樹脂５を流入させる工程が必
要であるために製造が煩雑となる欠点があり、さ
らに今一つの欠点はLSIチツプの下が樹脂である
がために、該チツプがノイズを受けて誤動作し易
いということである。 However, the structure of the conventional electronic component described above has the disadvantage that manufacturing is complicated because it requires a process of flowing the light-shielding resin 5 into a very narrow gap.Another disadvantage is that the bottom of the LSI chip is made of resin. As a result, the chip is susceptible to noise and malfunctions.
本発明はかかる従来の欠点に鑑み、遮光用樹脂
５の流入工程を省き且つノイズによる誤動作を防
止することができる電子部品の構造の提供を目的
とするものである。 In view of these conventional drawbacks, the present invention aims to provide a structure of an electronic component that can omit the step of introducing the light-shielding resin 5 and prevent malfunctions due to noise.
以下、第３図にもとづいて本発明の一実施例を
詳細に説明すると、本発明の電子部品は電極パタ
ーン２の１つである接地用の電極パターン７を基
板１の遮光用樹脂を流入塗布すべき部分、即ち図
に示す如く四方に分散形成した電極パターン群２
の中央部まで延長し、さらに他の電極パターン２
と接触しない程度にできるだけ広い領域８にわた
つて形成している。 Hereinafter, one embodiment of the present invention will be described in detail based on FIG. 3. In the electronic component of the present invention, the grounding electrode pattern 7, which is one of the electrode patterns 2, is coated with the light-shielding resin of the substrate 1. electrode pattern group 2 distributed in all directions as shown in the figure.
and further extend to the center of the electrode pattern 2.
It is formed over as wide an area 8 as possible without coming into contact with.
かかる構成によれば、従来基板１の遮光用樹脂
を流入塗布すべき領域８に不透明な導電部材から
ある接地用電極パターン７を延長形成しているの
で、このパターンによつて光を遮断することがで
きる。このため、電極パターン２にLSIチツプを
ボンデイングしたのちは該両者間の狭い隙間に遮
光用樹脂を流入させる必要がない。つまり、ボン
デイング後は直ちにポツデイング樹脂にてLSIチ
ツプを封入することができる。 According to this configuration, since the grounding electrode pattern 7 made of an opaque conductive material is extended and formed in the region 8 of the conventional substrate 1 where the light-shielding resin is to be applied, the light can be blocked by this pattern. I can do it. Therefore, after bonding the LSI chip to the electrode pattern 2, there is no need to flow light-shielding resin into the narrow gap between the two. In other words, the LSI chip can be immediately encapsulated with potting resin after bonding.
さらに、LSIチツプの底部は上記領域８に設け
た導電膜、すなわち接地用電極パターン７により
被覆された形となつているので、ノイズの影響を
防止し、LSIの誤動作の原因を解消することがで
きる。 Furthermore, since the bottom of the LSI chip is covered with the conductive film provided in the area 8, that is, the grounding electrode pattern 7, it is possible to prevent the influence of noise and eliminate the cause of LSI malfunction. can.
以上のように本発明によれば、ボンデイングす
るLSIチツプ底面の所定の領域に対向する基板上
の領域を該基板に形成する電極パターン構成部材
にて被覆するものであるから、遮光用樹脂の流入
工程を省き且つノイズによる誤動作を防止するこ
とができる。 As described above, according to the present invention, since the area on the substrate opposite to the predetermined area on the bottom surface of the LSI chip to be bonded is covered with the electrode pattern component formed on the substrate, the inflow of the light-shielding resin is prevented. It is possible to save steps and prevent malfunctions due to noise.
第１図は従来の電子部品の要部構造を示す図、
第２図は同電子部品の縦断面図、第３図は本発明
に係る電子部品の要部構造を示す図である。
１は基板、２は電極パターン、４はLSIチツ
プ、７は接地用電極パターン、８は接地用電極パ
ターンの延長形成部。
Figure 1 is a diagram showing the main structure of a conventional electronic component.
FIG. 2 is a longitudinal sectional view of the electronic component, and FIG. 3 is a diagram showing the main structure of the electronic component according to the present invention. 1 is a substrate, 2 is an electrode pattern, 4 is an LSI chip, 7 is a grounding electrode pattern, and 8 is an extension of the grounding electrode pattern.
Claims (1)
ボンデイングする電子部品に於て、上記LSIチツ
プ底面の所定の領域に対向する上記基板上の領域
を上記電極パターン構成部材にて被覆して成るこ
とを特徴とする電子部品の構造。 ２ 上記電極パターンのうち接地用電極パターン
を上記基板上の領域まで延長形成してなることを
特徴とする特許請求の範囲第１項に記載の電子部
品の構造。[Claims] 1. In an electronic component in which an LSI chip is bonded to an electrode pattern formed on a substrate, an area on the substrate opposite to a predetermined area on the bottom surface of the LSI chip is covered with the electrode pattern constituent member. A structure of an electronic component characterized by comprising: 2. The structure of an electronic component according to claim 1, wherein a grounding electrode pattern of the electrode pattern is formed to extend to a region on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57010534A JPS58127338A (en) | 1982-01-25 | 1982-01-25 | Structure of electronic part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57010534A JPS58127338A (en) | 1982-01-25 | 1982-01-25 | Structure of electronic part |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58127338A JPS58127338A (en) | 1983-07-29 |
| JPS6364899B2 true JPS6364899B2 (en) | 1988-12-14 |
Family
ID=11752924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57010534A Granted JPS58127338A (en) | 1982-01-25 | 1982-01-25 | Structure of electronic part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58127338A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60147140A (en) * | 1984-01-11 | 1985-08-03 | Hitachi Ltd | Mounting process of semiconductor element chip |
| JP4212255B2 (en) | 2001-03-30 | 2009-01-21 | 株式会社東芝 | Semiconductor package |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5420315B2 (en) * | 1974-07-15 | 1979-07-21 | ||
| JPS53112061A (en) * | 1977-03-11 | 1978-09-30 | Sharp Corp | Wiring substrate of semiconductor chip |
| JPS5474369A (en) * | 1977-11-26 | 1979-06-14 | Fujitsu Ltd | Semiconductor device |
| JPS56110292A (en) * | 1980-02-06 | 1981-09-01 | Hitachi Ltd | Semiconductor device |
| JPS56148840A (en) * | 1980-04-22 | 1981-11-18 | Citizen Watch Co Ltd | Mounting structure for ic |
| JPS5827935U (en) * | 1981-08-18 | 1983-02-23 | 株式会社村田製作所 | Hybrid integrated circuit device |
-
1982
- 1982-01-25 JP JP57010534A patent/JPS58127338A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58127338A (en) | 1983-07-29 |
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