JPS6364904B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a multilayer wiring layer of a semiconductor device.

The multilayer wiring layer of a semiconductor device consists of a lower (first) wiring on a semiconductor substrate, an interlayer insulating layer, and an upper (second) wiring, and if necessary, through holes (called contact holes or electrode windows) are formed in the interlayer insulating layer. The upper and lower (first and second) wirings are connected by connecting the upper and lower (first and second) wirings. This through-hole formation is performed by selective etching using a photoetching method.

Conventionally, for example, when the wiring is made of Al and the interlayer insulation layer is PSG (phosphsilicate glass),
When selective etching is done by dry etching
Only the PSG interlayer insulation layer is etched away.
Al wiring is hardly etched. In addition,
The dry etching at this time is, for example, sputter etching or plasma etching using CCl ₄ or PCl ₃ or BCl ₃ as an etching gas. When forming through-holes using such dry etching, if the position of the through-hole deviates from the set position on the lower wiring, it is likely to shift, especially if it is a fine wiring pattern, and it may cause defects in the upper wiring to be formed later. (points where step coverage deteriorates) may occur, and in some cases, the wire may be disconnected. In other words, as shown in Figure 1, PSG
When through-holes 2 are formed in layer 1 by dry etching, step defects 4 occur in the upper Al wiring 3 as shown in FIG. Note that in FIGS. 1 and 2, the Al lower wiring 5 is formed on the insulation film (SiO ₂ film) 7 on the semiconductor substrate 6. In FIG.

Furthermore, if selective etching is performed by wet etching in the above case, the result will be as shown in FIG. 3. Note that the etching solution used at this time is
For example, H ₃ PO ₄ + ammonium fluoride or ammonium fluoride and a hydrofluoric acid aqueous solution are used.
The etching solution penetrates into the interface between the PSG layer 1 and the lower Al wiring 5, and etching progresses.
Moreover, this etching solution also slightly etches Al, causing roughness on the surface of the Al wiring. Then, when the Al upper wiring 3 is formed, a step defect 4 occurs as shown in FIG. In some cases, the upper wiring may be disconnected.

In order to prevent the above-mentioned step defects, the lower wiring portion corresponding to the through-hole formation point should be made larger so that even if there is some misalignment, only the upper surface of the lower wiring will not be exposed. However, this method does not allow for high integration of semiconductor devices.

An object of the present invention is to propose a method for forming a multilayer wiring layer that can avoid step defects from occurring in the upper wiring when the through holes provided in the interlayer insulating layer are formed out of alignment with the lower wiring. That's true.

The present invention relates to a method for forming a multilayer wiring layer of a semiconductor device that includes an etching process for forming a through hole in an interlayer insulating layer for connecting a lower wiring and an upper wiring. This is a method for forming a multilayer wiring layer, characterized in that etching is performed at an etching speed that is approximately equal to the etching speed of the lower wiring.

When the lower wiring is Al and the interlayer insulation layer PSG, chloride gas (e.g., CCl ₄ , PCl ₃ , BCl ₃ , preferably PCl ₃ ) and fluoride gas (e.g., CF ₄ ,
The above-mentioned etching process is preferably carried out by sputter etching or plasma etching using a mixed gas of C ₂ F ₅ Cl, CHF ₃ (preferably CF ₄ ). Further, instead of such dry etching, wet etching can be performed in which the etching solution is H ₃ PO ₄ , ammonium fluoride, or HNO ₃ .

The invention will be explained below by means of embodiment examples in conjunction with the accompanying drawings.

A predetermined functional area (for example, collector, base, emitter or
An oxide film (SiO ₂ film) 12 is formed by thermal oxidation or CVD on the surface of a semiconductor (silicon) substrate 11 on which the source and drain (in the case of a MOS transistor) are formed (FIG. 5). A conductive layer (Al, AlSi,
A layer (AlCu, Ti, Mo or W) 13 is formed, and a predetermined pattern of lower wiring 13 is formed by ordinary photoetching techniques. Next, the interlayer insulating layer 14 is
_For example, _CVD ( _chemical
(vapor deposition) film. Conductor layer 13
After forming the interlayer insulating layer 14 of Al and PSG, the through hole 15 is formed by sputter etching or plasma etching using a mixed gas of PCl ₃ and CF ₄ as an etching gas. With this dry etching, not only the PSG extreme layer but also the Al
The lower layer wiring is also etched at approximately the same etching speed as the PSG. In this dry etching, the proportion of CF ₄ gas in the mixed gas is preferably 30 to 50 mol %.

Next, a conductor layer (Al, AlSi, AlCu, Ti, Mo or W) 16 is formed by vapor deposition on the insulating layer 14 and the exposed lower wiring 13 for the upper wiring (sixth layer). figure). Since the shape of the lower wiring, which is etched at the same time as the formation of the through hole, has a smooth slope similar to the external shape of the insulating layer 14, it is possible to obtain the upper wiring 16 with almost no disconnections or step defects. Of course, the upper wiring is formed by photo-etching the conductive layer into a predetermined pattern.

In order to make the etching speed of the lower wiring and the interlayer insulating layer almost the same according to the present invention,
The combination of materials that make up each (e.g.
(AlSi wiring and SiO ₂ insulation layer, Mo wiring and Si ₃ N ₄ insulation layer)
The composition of the etching gas or etching solution is determined accordingly.

[Brief explanation of drawings]

1 and 2 are schematic partial cross-sectional views of a semiconductor device illustrating a method of forming a multilayer wiring layer using conventional dry etching, and FIGS. 5 is a schematic partial cross-sectional view of a semiconductor device illustrating a method for forming a multilayer wiring layer according to the present invention; FIGS. be. DESCRIPTION OF SYMBOLS 1... Interlayer insulating layer, 2... Through hole, 3... Upper wiring, 4... Step defect, 5... Lower wiring, 6... Semiconductor substrate, 11... Semiconductor substrate, 13... Lower wiring,
14... Interlayer insulating layer, 15... Through hole, 16...
Upper wiring.

Claims (1)

[Scope of Claims] 1. A method for forming a multilayer wiring layer of a semiconductor device, which includes an etching process for forming a through hole in an interlayer insulating layer for connecting a lower wiring and an upper wiring, wherein the etching process is performed as described above. A method for forming a multilayer wiring layer, characterized in that etching is carried out so that the etching speed of the interlayer insulating layer and the etching speed of the lower wiring are approximately equal. 2. A patent claim characterized in that when the lower wiring is made of Al and the interlayer insulating layer is made of PSG, a dry etching process is performed using a mixed gas of chloride gas and fluoride gas as the etching gas. The method described in item 1. 3. Process according to claim 2, characterized in that the chloride gas is PCl ₃ and the fluoride gas is CF ₄ in a proportion of 10 to 90 mol %. 4. A patent characterized in that, when the lower wiring is made of Al and the interlayer insulating layer is made of PSG, a wet etching process is performed using a mixed solution of phosphoric acid, ammonium fluoride, and nitric acid as an etching solution. The method according to claim 1.