JPS6365271B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the field to which the invention pertains The present invention relates to an improvement in a line memory circuit applied to a facsimile two-dimensional redundancy suppressing code/decoder.

(2) Description of conventional technology Conventionally, facsimile two-dimensional redundancy suppression code/decoder, such as Consultative Committee for International Telegraph and Telephone (CCITT)
Modified leads are standardized for telephone network facsimile systems in
The line memory circuit of the encoder/decoder using the Read (abbreviated as MR) encoding method includes a memory #1 having a capacity capable of storing image signals for at least one scanning line of the current scanning line being encoded; The memory #2 has a capacity capable of storing image signals for one scanning line of the reference scanning line encoded one scanning line before, and also has a capacity for storing image signals for one scanning line in order to continuously input image signals. memory #3 having a capacity capable of storing image signals of
It was designed to be used by switching between the two. For this reason, for example, if one scanning line has 1728 pixels, the total number of pixels is 5184.
Required pixel memory. When converting a code or decoder into an LSI using a line memory with this configuration,
The memory requires approximately 3Kgates in terms of logic circuits, which is approximately 25% of the approximately 12Kgates required for logic circuits that perform encoding or decoding processing, and it is difficult to simultaneously provide memory and logic circuits on one LSI chip. was difficult. Therefore, even if the encoding or decoding logic circuit is made into an LSI, the memory will be placed on a separate chip.
Since it was constructed using LSI, the encoder or decoder as a whole had the disadvantage of requiring multiple chips. In addition, as terminals for the logic circuit LSI for encoding or decoding, approximately 18 terminals are required for an address and data bus that can be connected to memory in the case of 1728 pixels, which has the disadvantage of complicating the terminal configuration of the LSI.

(3) Purpose of the Invention In order to solve these drawbacks, the present invention provides a memory a having a capacity capable of storing image signals for one scanning line.
A line memory circuit is constructed using only memory b, which has a capacity to store one or more blocks of one pixel or several blocks.In the case of one scanning line of 1728 pixels, the logic The aim is to make it possible to realize a line memory circuit by using approximately 1Kgate in circuit terms, which is approximately 8% of the logic circuit.

The drawings will be explained in detail below.

(4) Description of structure and operation of the invention FIG. 1 shows an embodiment of the invention used in an MR encoder, in which 1 is a memory a having a capacity capable of storing image signals for one scanning line, and 2 is a memory a having a capacity capable of storing image signals for one scanning line. Memory b is capable of storing image signals for one block of four pixels, 3 is an address pointer indicating blocks of memory a and memory b, 4a is an MR encoder, and 5a is a memory that directly stores the input image signal four pixels at a time. Shift register for parallel conversion and input; 6 is a counter that displays an interrupt every 4 clocks of the image signal; 7 is a latch that indicates whether image signal input is possible; 8 is an address register for memory b; 9 is a memory a 10 is a read address register for memory a, 1
1 is the change point address a ₀ register, 12 is the change point address a ₁ register, 13 is the change point address a ₂ register, 14 is the change point address b ₁ register, 15 is the change point address b ₂ register, 16 is the memory (a )1 and memory (b)2 and memory address pointer 3 and MR
A data bus connects the encoder 4a and the shift register 5a, 17 is a write control line to the memory address pointer 3, 18 is an address bus to memory a and memory b, and 19 is a write control line to memory a and memory b. Control line 20 is a read control line to memory a and memory b,
21 is an interrupt control line, 22 is an output line, 23a is an input image signal, 24 is an image signal clock, and 25a is an image signal input enable display line.

FIG. 2 is an explanatory diagram for writing and reading image signals into and from memory in the embodiment of FIG.
This shows the case where the number of pixels in one scanning line is 28 pixels and 7 blocks. 30 is a reference scanning line, 31 is a current scanning line, and 32a is a block stored in the memory (b) 2.

The operation of the embodiment shown in FIG. 1 will be explained with reference to FIG.

Before one scanning line of the image signal is encoded, all the pixels 30 of the reference scanning line have already been stored in the memory (a) 1. At the start of a page, all white is stored in memory (a) 1. In addition, the MR encoder 4a
sets the memory a write address register 9 and the memory a read address register 10 in the first block.

In each step, the image signal is input by dividing the image signal clock 24 into 1/4 by the counter 6 and interrupting the MR encoder 4a via the interrupt control line 21. The MR encoder 4a receives an input image signal 23a
One block's worth of image signals inputted from the block, serial-parallel converted for each block, and stored in the shift register 5a are written into the block of memory (a) 1 indicated by the write address register 9 for memory a. Also, MR encoder 4
A compares the block indicated by the memory a write address register 9 and the memory a read address register (a) 10a, and determines whether the block indicated by the memory a write address register 9 is the memory a read address register (a). a) Inspect to ensure that the block indicated by 10a is not exceeded. Write address register 9 for memory a
Immediately before the block indicated by exceeds the block indicated by the memory a read address register (a) 10a, the MR
The encoder 4a uses the latch 7 via the output line 22 to disable the image signal input/display line 25a. 1
The latch 7, which displayed the disabled display, is returned to the enabled display when the block a of the read address register 10a for the memory a is incremented. Image signal input possible display line 2
While 5a indicates disable, the image signal clock 2
4 is stopped and no image signal is input.

(Step 1) When the MR encoder 4a starts encoding one scanning line, it first detects change point addresses b ₁ and b ₂ of the reference scanning line 30. To do this, the contents of the memory a read address register (a) 10a are output to the memory address pointer 3 using the write control line 17 to the memory address pointer 3. Ra indicates block 1, which is connected to memory (a) by address bus 18.
Output to 1.

Next, the MR encoder 4a inputs one block worth of pixels from block 1 of the memory (a) 1 to the MR encoder 4a via the data bus 16 using the read control line 20 of the memory a.

The MR encoder 4a examines the change points in block 1.

In the case of FIG. 2, block 1 of the reference scanning line 30
There is no change point. The MR encoder 4a increments the contents of the memory a read address register (a) 10a by 1 and indicates block 2. As in the case of block 1, MR encoder 4a receives block 2 as input and checks the change point in block 2. This process is repeated until a change point within the block is detected. In the case of FIG. 2, changing points are detected in pixels 11 and 12 in block 3, and the addresses of pixels 11 and 12 are stored in changing point address b ₁ register 14 and changing point address b ₂ register 15. MR when change point detection is completed
The encoder 4a writes the block in which _b2 was detected, that is, the last detected block 3, into the memory (b) 2a.

The MR encoder 4a then detects the change point addresses a ₁ and a ₂ of the current line. Since reading up to block 3 of reference scanning line 30 has already been completed,
Blocks 1 to 3 of the current scanning line 31 are input to the area of blocks 1 to 3 of the memory (a) 1 by the image signal input by the above-mentioned interruption.

The MR encoder 4a uses the memory a read address register (b) 10b to detect a change point for each block in the same way as for the reference line. Second
In the case of the figure, pixel 3 of block 1 and block 3
A change point is detected at pixel 10, and the change point address a ₁
The addresses of pixels 3 and 10 are stored in register 12 and change point address _a2 register 13. The change point address a ₀ is pixel 0. Change point address
Since a ₀ a ₁ a ₂ b ₁ b ₂ has been found, MR encoding is possible. In this case, |a ₁ b ₁ | > 3a ₁ < b ₂ , so encoding is performed in horizontal mode |a ₀ a ₁ |, |a ₁ a ₂ |.

(Step 2) When the encoding of one mode is completed, the MR encoder 4a detects the change point addresses b ₁ and b ₂ of the reference scanning line 30 again. This is done according to the previously encoded mode. In the case of horizontal mode encoding, b ₁ and b ₂ are detected as a pair until a ₂ <b ₁ . In the case of FIG. 2, since a ₂ <b ₁ already holds, no change point detection of the reference scanning line 30 is performed.

The MR encoder 4a then detects a change point in the current scanning line 31.

In the case of FIG. 2, block 3 is read out according to the read address register (b) 10b for memory a, but a ₀
No other change points are detected. However, since only up to block 3 of the reference scanning line has been read by the memory a read address register (a) 10a, the current scanning line is read up to block 3 according to the memory a read address register (b) 10b. . In this case, it can be determined that b ₂ <a ₁ without detecting the change point address a ₁ , and it can be encoded in pass mode.

(Step 3) After encoding in pass mode, the MR encoder 4a
Blocks 4 and 5 of reference scanning lines with b ₁ and b ₂ as one set
is inspected, change pixels 15 and 17 are detected, and change point addresses b ₁ and b ₂ are stored in each register. Next, change points of the current line are detected using block 5 as the upper limit, change pixels 14 and 17 are detected, and the change point address is
Accumulate a ₁ and a ₂ in each register. In this case | a ₁ b ₁
Since |≦3, it is encoded as vertical mode.

(Step 4) After the MR encoder 4a encodes in vertical mode,
To detect the change point of the reference scanning line, change b ₂ from the previous step to b ₁
, only b ₂ is detected. In the case of Fig. 2, up to block 6 is inspected and the change point addresses b ₁ and b _{2 are}
is accumulated in each register.

Furthermore, after the change point detection of the current scanning line is also encoded in the vertical mode, only _a2 is detected by setting _a2 of the previous step to _a1 . In this case, |a ₁ b ₁ |=0 and is encoded in vertical mode.

(Step 5) Similar to (Step 4), the changing points b ₁ b ₂ and a ₁ a ₂ can be detected, and |a ₁ b ₁ |≦3, so they are encoded in the vertical mode.

(Step 6) Similar to (Step 4), changing points b ₁ b ₂ and a ₁ a ₂ can be detected. However, in this case, the 29th pixel is set as the virtual change point. In this case, |a ₀ a ₁ | |a ₁ a ₂ | is encoded in horizontal mode. Since the last pixel of the current scan line has been encoded, the encoding of one scan line is completed.

At this time, the current scanning line 3 in FIG. 2 is stored in memory (a) 1.
1 blocks 1 to 7 are stored and can be used as reference scan lines when encoding the next scan line.

Because it operates in this way, only memory (a) 1, which has a capacity to store image signals for one scanning line, and memory (b) 2, which has a capacity to store one block of four pixels, are used. , the line memory circuit of the MR encoder can be configured.

Although one block has four pixels in this embodiment, it can be any number of pixels. Furthermore, although the memory (b) 2 is made to have one block, it is clear that the same operation as in this embodiment is possible if it has one or more blocks.

FIG. 3 shows an embodiment of the present invention used in an MR encoder, and the configuration is almost the same as the line memory circuit of the MR encoder shown in FIG. 4b is the MR decoder,
23b is an output image signal.

FIG. 4 is an explanatory diagram of writing and reading of image signals into and from memory in the embodiment of FIG.
The figure shows the decoding of encoded scan lines.

The operation of the embodiment shown in FIG. 3 will be explained with reference to FIG.

Before one scanning line of the image signal is encoded, all the pixels 30 of the reference scanning line have already been stored in the memory (a) 1. At the start of a page, all white is stored in memory (a) 1. In addition, the MR decoder 4b
sets the memory a write address register 9 and the memory a read address register 10 in the first block.

In each step, the image signal is output by dividing the image signal clock 24 into 1/4 by the counter 6 and interrupting the MR decoder 4b via the interrupt control line 21. The MR decoder 4b outputs an image signal for each block and outputs it to the shift register 5b. The image signal accumulated in the shift register 5b is
It is output in synchronization with the image signal clock 24. 1st
Unlike the case of the MR encoder shown in the figure, the image signal of one scanning line can be output regardless of the write/read address of the memory (a) 1. However, MR decoder 4b
However, when writing the decoded image signal to the memory (a) 1, the block indicated by the write address register 9 for memory a and the read address register (a) 10a for memory a are compared, and the block indicated by the memory a write address register 9 is compared. Writing to memory (a) 1 is possible by preventing the block indicated by the write address register 9 from exceeding the block indicated by the read address register (a) 10a for memory a.
Determine whether or not it is possible.

(Step 1) When the MR decoder 4b starts decoding one scanning line, it first detects the change point addresses b ₁ and b ₂ of the reference scanning line 30. To do this, the contents of the memory a read address register (a) 10a are output to the memory address pointer 3 using the write control line 17 to the memory address pointer 3. Ra indicates block 1, which is output to memory (a) 1 via address bus 18.

Next, the MR decoder 4b inputs one block worth of pixels from block 1 of the memory (a) 1 to the MR decoder 4b via the data bus 16 using the read control line 20 of the memory a.

MR decoder 4b examines the change points in block 1.

In the case of FIG. 4, block 1 of the reference scanning line 30
There is no change point. The MR decoder 4b has a memory a
The contents of the read address register (a) 10a are incremented by 1 to indicate block 2. As in the case of block 1, MR decoder 4b inputs block 2 and examines the change point in block 2. In this way,
Repeat until a change point within the block is detected.
In the case of FIG. 4, a change point is detected at pixels 11 and 12 in block 3, and the change point address _b1 register 14,
The addresses of pixels 11 and 12 are stored in the change point address _b2 register 15.

The MR decoder 4b then creates change point addresses a ₁ and a ₂ for the current scanning line. The current scan line is written after blocks up to block 3 of the reference scan line have been output by the aforementioned interrupt. As described above, this is done by comparing the memory a write address register 9 and the memory a read address register 10a.

The MR decoder 4b uses the decoding mode H (2.7) to determine the change point a ₁ and a ₂ using the change point a ₀ as a reference.
Outputs pixel data up to a ₂ . In this case, the last block 3 is temporarily stored in memory (b) 2, and 1
After the block is completed, it is stored in memory (a)1. From then on, the last block is always treated the same way.

(Step 2) When the decoding of one mode is completed, the MR decoder 4b detects the change point addresses b ₁ and b ₂ of the reference scanning line 30 again. This is done according to the previously decoded mode. In the case of horizontal mode decoding, b ₁ and b ₂ are detected as a pair until a ₂ <b ₁ . In the case of FIG. 4, since a ₂ <b ₁ already holds, no change point detection of the reference scanning line 30 is performed.

The MR decoder 4b then creates change point addresses a ₁ and a ₂ for the current scanning line. In this case, the next path mode is P, and a ₁ and a ₂ are not created or output.

(Step 3) After encoding in pass mode, the MR decoder 4b inspects blocks 4 and 5 of the reference scanning line using b ₁ and b ₂ as one set, detects changed pixels 15 and 17, and detects changed pixels. Store point addresses b ₁ and b ₂ in each register. The next decoding is in vertical mode V(-1), and _a1 , which is one pixel to the left, is created based on _b1 and stored in the memory (a)1.

(Step 4) After the MR decoder 4b decodes in vertical mode,
To detect the change point of the reference scanning line, use _b2 in the previous step.
Only b ₂ is detected as b ₁ .

The decoding in this step is in vertical mode V(0), and _a1 is created in the pixel immediately below based on _b1 , and the memory
(a) Accumulated in 1.

(Step 5) Similarly to (Step 4), V(-2) is decoded.

(Step 6) Similarly to (Step 1), H(1.9) is decoded. This completes the decoding of one scanning line. At this time, blocks 1 to 7 of the current scanning line 31 in FIG. can be used as a reference scanning line.

Since it operates in this way, only memory (a) 1, which has a capacity to store image signals for one scanning line, and memory (b) 2, which has a capacity to store one block of four pixels, are used. , can configure the line memory circuit of the MR decoder.

In this embodiment, as in the embodiment shown in FIG. 1, the number of pixels in one block and the number of blocks in memory b can be arbitrary.

Furthermore, in both embodiments, there is no mention of a logic circuit that communicates the start and end of a scanning line with the sensor and the recording unit to advance the scanning line, but this is omitted because it can be realized using the same conventional circuit. It has been done.

Also, in the encoder embodiment of FIG.
In the embodiment of the decoder shown in FIG. 3, memory b is used when reading the image signal from memory a, but the operation is reversed, that is, when the encoder writes the image signal. It goes without saying that it is also possible to use memory b when reading the image signal and use memory b when reading the image signal with the decoder.

(5) Explanation of Effects As explained above, according to the present invention, a memory a having a capacity capable of storing image signals for one scanning line is used.
and the line memory of the facsimile two-dimensional redundancy suppression encoder and decoder can be constructed using only the memory b which has a storage capacity for one or more blocks each consisting of one pixel or several pixels;
It is possible to configure a line memory circuit with a small memory capacity, and is particularly effective when constructing a two-dimensional redundancy suppression encoder/decoder including a line memory circuit on a single LSI chip.

[Brief explanation of drawings]

Figure 1 shows an embodiment of the present invention used in an MR encoder.
FIG. 2 is an explanatory diagram of writing and reading image signals into and from memory in the embodiment of FIG. 1, FIG. 3 is an embodiment of the present invention used in an MR decoder, and FIG. 4 is an example of the embodiment of FIG. 3. FIG. 6 is an explanatory diagram of writing and reading image signals into and from memory in FIG. In the figure, 1 is memory a, 2 is memory b, 3 is the memory address pointer, 4a is the MR encoder, and 4b
is an MR decoder, 5 is a shift register, 6 is a counter, 7 is a latch, 8 is an address register for memory b, 9 is a write address register for memory a, 10
a is a read address register for memory a, 10b is a read address register for memory a, 11 is a change point address a ₀ register, 12 is a change point address a ₁ register, 13 is a change point address a ₂ register, 14
is the change point address b ₁ register, and 15 is the change point address b ₂ register.

Claims (1)

[Scope of Claims] 1. A memory a having a capacity capable of storing image signals for one scanning line, and means for writing image signals into the memory a in units of blocks each consisting of one pixel or several pixels;
means for reading out image signals from the memory a in units of one pixel or blocks each consisting of several pixels;
to the memory a so that the writing means does not write image signals to an area of the memory a in which image signals that have not been read out by the reading means out of the image signals of one scanning line written in the memory a are stored; It is possible to write
a block of one or more pixels recently read out from the memory a;
Alternatively, a memory b having a capacity capable of storing a plurality of blocks, a means for writing an image signal into the memory b in units of blocks each consisting of one pixel or several pixels, and a means for writing the image signal from the memory b from one pixel or several pixels. and encoding or decoding using means for reading in blocks, and pixels on the current scanning line and pixels on a reference scanning line, which is a scanning line earlier than the current scanning line, based on the contents from the memory a. A line memory circuit for a facsimile two-dimensional redundancy suppressing code/decoder, comprising a code converter for performing the following steps. 2. A memory a having a capacity capable of storing image signals for one scanning line, and means for writing image signals into the memory a in units of blocks each consisting of one pixel or several pixels;
means for reading out image signals from the memory a in units of one pixel or blocks each consisting of several pixels;
to the memory a so that the writing means does not write image signals to an area of the memory a in which image signals that have not been read out by the reading means out of the image signals of one scanning line written in the memory a are stored; It is possible to write
a memory b having a capacity capable of storing one or more blocks of one or more pixels to be written to the memory a next;
means for writing image signals into the memory b in units of one pixel or blocks each consisting of several pixels; means for reading out image signals from the memory b in units of one pixel or blocks each consisting of several pixels; and a code converter that performs encoding or decoding using pixels on the current scanning line and pixels on a reference scanning line, which is a scanning line earlier than the current scanning line, based on the contents of the scanning line. Line memory circuit for facsimile two-dimensional redundancy suppression code/decoder.