JPH0149072B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a facsimile image encoding circuit,
In particular, the present invention relates to an encoding circuit suitable for performing run-length encoding processing such as a modified Huffman code.

[Prior art]

A conventional facsimile image encoding circuit has a memory that stores one bit of a digital image signal as one word, reads out the image signal serially from this memory, and changes from a white pixel to a black pixel or from a black pixel to a white pixel. (hereinafter referred to as the change point)
Find out the number of pixels (run length) from the previous change point to the current change point using a counter,
A run-length encoding process was performed to encode the value. In run-length encoding processing using this method, in order to perform encoding processing faster than conventional methods, it is necessary to read out image signals from memory at high speed, which requires expensive high-speed memory. . As a means to overcome these drawbacks, a memory that stores multiple bits as one word is used, and multiple bits of the image signal are read out in parallel in word units from this memory, and this is converted into serial data to find the change point. There are possible ways. For example, if one word is made up of 8 bits, each bit can be read eight times faster than when one word is made up of one bit. However, in the method of finding the change point as described above, the circuit for converting parallel data into serial data, the circuit for finding the change point, and the circuit for counting the run length are 8 times faster than reading the image signal from memory in words. Double high-speed operation is required, and high-speed operation type circuit elements are required.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an encoding circuit that can encode digital image signals such as facsimile signals at high speed even when using circuit elements that operate at relatively low speeds.

[Summary of the invention]

The present invention sequentially reads image signals stored in a memory and detects change points where the image signal changes from a white pixel to a black pixel and a change point where the image signal changes from a black pixel to a white pixel. In an encoding circuit that calculates and encodes the number of consecutive white or black pixels of A word address generation circuit that generates an address, an inversion circuit that inverts the white and black of the image signal read from the memory, and a selection circuit that selects the image signal read from the memory or its inverted image signal. , a temporary storage circuit that temporarily stores the selected image signal, and detects a change point in the word-based image signal outputted in parallel from the temporary storage circuit, and detects a change point presence signal and a change position signal within the word. a change position detection circuit that outputs a change position signal, a change point storage circuit that stores a change position consisting of a change position signal in the word and a word address of the word, and a change point storage circuit that stores the change position in the temporary storage circuit in response to a change point presence signal. A circuit that inverts the image signal and eliminates the change point, and detects a change from the previous change position stored in the change point storage circuit, a change position detection circuit, and a change position output from the word address generation circuit. The present invention is characterized in that it includes a calculation circuit that calculates the number of pixels between positions, and a controller that controls the operation timing of each of the circuits.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows a typical process in the encoding circuit for the international standard Modified Huffman Code (hereinafter referred to as MH code), which is a typical run-length code used in facsimile equipment. FIG. There are many facsimile devices on the market that use the MH code.
Since this process is explained in detail in Japanese Patent Application Laid-open No. 55-37003 and Japanese Patent Application Laid-open No. 55-63171, only a brief explanation of the processing flow will be given here. The serial digital image signal a obtained by scanning the original with a facsimile reader etc. is temporarily stored in the RAM.
A circuit 3 that detects a change point after being stored in a memory 200 consisting of a random access memory (Random Access Memory), etc.
Reads out as 00. The change point detector 300 reads the digital image signal b from the memory 200 and converts the position information signal c of the change point into the run length calculation circuit 4.
Output to 00. Run length calculation circuit 400
calculates the run length from the position information signal c at the change point and outputs the run length signal d. And M.H.
Run length signal d is converted into MH code signal e using table 500 storing codes. In FIG. 1, a controller (often composed of a microcomputer or the like) that controls these is omitted.

FIG. 2 shows a change point detection circuit 300 according to the present invention.
This is to explain in detail. In the following embodiment, one byte (8 bits) will be explained as one word.

The memory 200 is, for example, an IC manufactured by Hitachi, Ltd.
(Integrated Circuit) memory (HM6116), where 1 byte (8 bits) constitutes 1 word. Byte address generation circuit 310
is an IC (HD6844) made by Hitachi, Ltd.
DMAC (Direct Memory Access Controller)
In response to a DMA request signal p, a specific byte address signal g and a read signal f of the memory are given to the memory 200, a digital image signal b is read out from the memory 200 in units of bytes, and a latch pulse q is output. Now, set the white pixel to “0”,
Assuming that a black pixel is "1", the digital image signal b depends on whether the change point of the image signal b is detected from "1" to "0" or from "0" to "1". The selection signal s and the selection circuit 340 control whether to select the image signal h as it is or to select the inverted image signal h obtained by inverting it by the inversion circuit 320. The image signal i passes through a mask circuit 350, which will be described later, and is then stored in a latch circuit 360 as a modified image signal j. Further, the image signal k output from the latch circuit 360 is transmitted to the inverting circuit 3.
30 as the inverted image signal l by the selection circuit 34
0 and is selected when the change point presence signal O is output. The change position detection circuit 370 is, for example, an IC manufactured by Texas Instruments.
(SN74LS148), and a change point presence signal O indicating whether or not there is "0" in the change image signal k output from the latch circuit 360, that is, whether or not a change point exists; The bit address m of the position where "0" appears for the first time as viewed from the lower bits, that is, the point of change, is output. memory 200
The above series of operations is repeated while incrementing the byte address signal g of the memory until a changing point exists in the 1-byte digital image signal read from the 1-byte digital image signal, that is, until a changing point presence signal O is output. The mask circuit 350 does nothing when the change point presence signal O is not output, but when the change point presence signal O is output, it moves from the "0" bit to the change point indicated by the bit address m, or ( By forcibly recoloring up to the m-1) bit to "1", the already detected change point is eliminated.

FIG. 6 describes the mask circuit 350, latch circuit 360, and change position detection circuit 370 of FIG. 2 in more detail. The mask circuit 350 is composed of an IC (SN74LS138) made by Texas Instruments, indicated by the reference numeral 351, and a gate circuit 352, and the latch circuit 360 is made up of an IC made by Texas Instruments.
(SN74LS373) is an example in which the change position detection circuit 370 is configured with an IC manufactured by the same company (SN74LS148).

These series of operations will be explained with reference to the time chart of FIG. 4, taking as an example the case where the contents of the memory 200 are as shown in FIG. As for the signals in the memory 200, the smaller the byte address, the more the image signal is for the left pixel within one line of the document, and within each byte, the smaller the bit address, the more the signal is the image signal for the left pixel. Sections IV to V in FIG. 4 are provided for convenience of explanation. In section I, the calculation starting point n of byte address g and run length d is assumed to be "0" as an initial value. Further, initially, it is assumed that a change point of the image signal b from "1" to "0" is detected, and the selection signal s is "0". First, the byte address generation circuit 310
Address 0 is output as the byte address g, a read signal f is output to read the image signal b from the memory 200, and a latch pulse q is output to cause the latch circuit 360 to latch the image signal j. From FIG. 3, the image signal at address 0 is "11111111" starting from the 7th bit, so the latch circuit 36
The image signal k outputted from 0 becomes "11111111" (this is expressed in hexadecimal notation in FIG. 4).
Since "0" does not exist in this image signal k, the change point presence signal O remains "0". In the section, the contents of byte address g at 1 are read out in the same way as in section I, and latched in the latch circuit 360. At this time, the image signal k output from the latch circuit 360 becomes "00000111", the bit address "3" which becomes "0" for the first time from the lower bit is output to the bit address m, and the change point existence signal O is output. It becomes "1". Differential circuit 420
Since the byte address g is "1" and the bit address m is "3", "11" is input to the A port, and "0" of the starting point n is input to the B port, so the difference is "11'' is output as the run length d. The controller 600 knows that a change point has occurred from the change point presence signal O, inputs the run length d, and performs a predetermined encoding process. In addition, the selection signal s is inverted in the interval, and the latch pulse r
and u are output. "11" is latched in the latch circuit 410 by the latch pulse u, and the difference circuit 4
The starting point n input to the B port of No. 20 is "11". The image signal j latched by the latch circuit 360 in the section is an image signal that has passed through the inversion circuit 330 and the mask circuit 350 because the change point presence signal O is "1". The signal "00000111" in the section becomes "11111000" by the inverting circuit 330, and then the mask circuit 350 recolors up to the third bit indicated by the bit address m to "1", resulting in "11111111", which is then latched. It is latched in circuit 360 and becomes image signal k. As a result, the change point presence signal O output from the change position detection circuit 370 becomes "0". The section is a mode for detecting the point where the image signal changes from "0" to "1". Since the selection signal s is "1", the image signal b at the byte address of address 2 read in the section is sent to the inverting circuit 320.
The signal is latched by the latch circuit 360 via the latch circuit 360. 2
Since the image signal b at the address is "00000000", the image signal k latched by the latch circuit 360 and outputted is "11111111", and the change point existence signal O remains "0". In section V, the image signal "11100000" with byte address 3 is read out,
Since the inverted one is selected and latched by the latch circuit 360, the image signal k becomes "00011111".
Therefore, the change point presence signal O becomes "1" and the bit address m becomes "5". Since byte address g is "3" and byte address m is "5",
The A port of the differential circuit 420 is "29". Also, since the starting point n of the B port is "11", the difference "18" is output as the run length d. Similarly, the run length is obtained by repeating the above operation.

FIG. 5 is a flowchart showing the flow of operations of the controller 600. This flowchart is activated for each scanning line. Processing 1000
At this point, the change point detection circuit 300 and run length calculation circuit 400 are initialized. That is, byte address generation circuit 310 has memory 2
Set the start address of 00, start it,
The latch circuit 410 is cleared and the selection signal s is set to "0". In process 2000, the change point presence signal O is monitored and the presence or absence of a change point is determined. If a change point exists, the process advances to step 3000 and inputs the run length d. In process 4000, the run length d is converted into an MH code by referring to the MH code table based on the run length d. Processing 50
At 00, it is determined whether all processing for one scanning line has been completed. This is because the number of pixels of the image signal that exists in one scanning line is fixed to a certain value by the system, so it can be determined by, for example, whether the sum of the run lengths matches the number of pixels for one scanning line. . If all processing for one scanning line has not been completed, the process advances to processing 6000. In processing 6000,
The selection signal s is inverted and the latch circuits 410 and 3
Output latch pulses u and r to 60, and process 2
Return to 000.

As is clear from the above explanation, since the image signal b is read out from the memory 200 in units of 1 byte (8 bits) for run-length encoding processing, a large amount of image signal b can be read out with a small number of memory accesses. Therefore, even when performing high-speed encoding processing, a relatively low-speed operating memory can be used. In addition, since change point detection is also performed by parallel data processing in 1-byte units, a large amount of image signal b can be processed with a relatively small number of operations, and the circuit elements for this are also relatively slow-operating types. That's enough. For example, if the run length is "256" and the process is performed in units of 1 bit as in the conventional method, the number of memory accesses will be 256 and the number of times the change point detection circuit will operate will be 256. If it is processed in units, the number of memory accesses is only 32. Further, the number of operations of the change point detection circuit is only (32+N) times when the number of change points is N. This means that when processing the same amount of image signals in the same amount of time, the operating speed of the circuit elements required is at least 1/8, and if the circuit elements have the same operating speed, the processing speed can be up to 8 times faster. means to be

〔Effect of the invention〕

As described above, according to the present invention, the image signal from the memory is read out in byte units, and the change point detection is also performed by parallel signal processing. This has the effect of realizing high-speed encoding processing depending on the element.

[Brief explanation of drawings]

Figure 1 is a block diagram of the central part of the circuit that performs encoding processing, Figure 2 is a detailed block diagram of the change point detection circuit according to the present invention, Figure 3 is a memory storage data allocation diagram, and Figure 4 is the operating time. 5 is a flowchart of the controller, and FIG. 6 is a partially detailed diagram of FIG. 2. 200...Memory, 310...Byte address generation circuit, 320, 330...Inversion circuit, 340
...Selection circuit, 350...Mask circuit, 360...
... Latch circuit, 370 ... Change position detection circuit, 4
10... Latch circuit, 420... Differential circuit, 60
0...Controller.

Claims (1)

[Claims] 1. By sequentially reading out the image signals stored in the memory and detecting the change points where the image signals change from white pixels to black pixels and from black pixels to white pixels, the continuous change points between each change point are detected. In the encoding circuit that calculates the number of white or black pixels and encodes it, a memory that can read out the image signal in parallel in word units, each word consisting of multiple bits, and a word address for the image signal read out from this memory are generated. a word address generation circuit,
an inversion circuit that inverts the white and black of the image signal read from the memory; a selection circuit that selects the image signal read from the memory or the inverted image signal; and a temporary storage for the selected image signal. a temporary storage circuit for detecting a change point in an image signal in units of words outputted in parallel from the temporary storage circuit, and a change position detection circuit for outputting a change point presence signal and a change position signal within the word; a change point memory circuit that stores a change position consisting of a change position signal in a word and a word address of the word; and a change point memory circuit that inverts the image signal stored in the temporary storage circuit in response to a change point presence signal and stores the change point. A calculation circuit that calculates the number of pixels between the change positions from the previous change position stored in the change point storage circuit, the change position detection circuit, and the word address generation circuit. and a controller that controls the operation timing of each of the circuits.