JPS6367697B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to tracers (state history storage devices).

A conventional tracer includes a trigger generating means that outputs a trigger signal when an input signal satisfies a preset trigger condition, and a transition to a second state if it is in a first state when the trigger signal is supplied. a state display means for outputting a state signal that transitions to the first state when a write end signal is supplied; and a clock signal is supplied when the state signal indicates the first state. a first storage means that writes and stores the input signal every time the state signal transitions to a second state, and starts reading out the stored input signal when the state signal transitions to a second state; and an input read from the first storage means. and second storage means for writing and storing signals, outputting the write end signal at the end of writing, and reading out the stored input signal for display on the display means.

Next, a conventional tracer will be explained with reference to the drawings.

Figure 1 is a block diagram showing a conventional example.
The tracer shown in the figure includes a storage device 1 that stores an input signal 100, a storage device 2 for display, a display device 3, and a counter 4 that provides an address of the storage device 1.
and a counter 5 giving the address of the storage device 2.
and a trigger generation circuit 6 that outputs a trigger signal.
Flip-flop 12 indicating that data is being transferred from storage device 1 to storage device 2;
a flip-flop 11 that indicates that an input signal is being stored into the circuit; delay circuits 10 and 14; AND gates 7 and 8; an OR gate 9; and a clock signal 10 that provides sample timing for the input signal.
5 and a clock signal 106 for controlling the display device.

Next, the operation of the conventional tracer will be sequentially explained using FIG.

Flip-flop 11 is initially set to "1". (When the power is turned on) The input signal 100 (processed by a known method according to the sample mode, latch mode, etc.) is ANDed by the clock signal 105 and the output signal 114 of the flip-flop 11 by the AND gate 7. The output signal 107 is used as a write signal for the memory device 1 to write to the address indicated by the counter 4, and then the counter is updated by the signal 110 that has passed through the OR gate 9 and the delay circuit 10. By the above operation every time the clock signal 105 is output, the input signal 100 is transferred to the storage device 1.
will be written to.

When the trigger condition is satisfied at a certain timing, the trigger signal 111 is output from the trigger generation circuit 6. When the trigger signal 111 becomes "1", the flip-flop 12 is set, and the flip-flop 11 and counters 4 and 5 are reset.

Since the flip-flop 12 is set and the counters 4 and 5 are reset, the input signal stored in the memory device 1 is transferred to the memory device 2 via the signal 101, and then becomes the clock signal 106 and the output signal 115 of the flip-flop 12. are sequentially transferred from address 0 by the write signal logically ANDed by AND gate 8.

When counter 5 overflows, signal 112
becomes "1", flip-flop 12 is reset, flip-flop 11 is set, data transfer from storage device 1 to storage device 2 is completed, and writing to storage device 1 is started again. The display device 3 learns from the signal 115 that the data transfer to the storage device 2 has been completed, and sequentially reads out the input signals for display stored in the storage device 2 by the clock signal 106, and displays them in a known manner. I do.

In this way, the conventional tracer has a storage device 1 that stores data obtained by sampling an input signal, and a storage device 2 that receives and displays the input signal stored in the storage device 1. Device 2
The input signals supplied to the storage device 1 while transferring the stored input signals to the storage device 1 are not stored in the storage device 1.

In other words, the input signal is not sampled properly. At this time, even if the trigger condition based on the input signal is satisfied, the generated trigger signal will be suppressed. Therefore, if the trigger signal suppressed in this way is the last one, that is, if an error occurs and the trigger signal is stopped so that no further trigger signals are generated, the input signal for the last trigger signal is not secured. Therefore, a situation arises in which failure analysis is not easy.

That is, the conventional tracer has a drawback in that failure analysis becomes difficult.

An object of the present invention is to provide a tracer that allows easy failure analysis.

That is, an object of the present invention is to have two storage devices for storing input signals, and to have a means for instructing which of the two storage devices sampled data is to be stored, and a means for instructing when the last trigger occurs. Provided is a tracer that solves the above drawbacks by having means for outputting data stored in a storage device that holds the data, and that makes it possible to collect the history of input signals when the last trigger occurs. It's about doing.

The tracer of the present invention includes a trigger generating means that outputs a trigger signal when an input signal satisfies a preset trigger condition, and a tracer that alternately switches between a first state and a second state when the trigger signal is supplied. a status display means for repeatedly outputting a status signal; and a status display means for writing and storing the input signal each time a clock signal is supplied when the status signal indicates the first status, and writing and storing the input signal so that the status signal indicates the second status. a first storage means that starts reading out the stored input signal when the state signal transitions to the second state;
a second state that writes and stores the input signal every time a clock signal is supplied when the state signal is in the first state, and starts reading the stored input signal when the state signal transitions to the first state; storage means; selecting the input signal read from the first storage means when the state signal indicates a second state; and selecting the input signal read from the first storage means when the state signal indicates the first state; The third storage means is configured to include a selection means for selecting an input signal read out from the storage means, and a third storage means from which the input signal stored is read out in order to write and store the selected input signal and display it on the display means. Ru.

That is, the tracer of the present invention samples the input signal at a preset timing, and
means for storing the input signal in an internal storage device and updating the address of the storage device; when a preset trigger condition is satisfied, storing the input signal in the storage device is stopped; A tracer having means for outputting data stored in the tracer, the tracer having two internal storage devices, means for instructing which of the two storage devices the sampled data is to be stored, and the presetting. The trigger condition is configured to include means for outputting data stored in a storage device that holds data when the trigger condition was last satisfied.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. The tracer shown in FIG. Device 3 and storage devices 1-1, 1-
Counters 4-1, 4-2 giving addresses of 2
and a counter 5 giving the address of the storage device 2.
and a trigger generation circuit 6- that outputs a trigger signal.
1, 6-2, selector 16, and storage device 1-
Flip-flops 12-1, 12-2 indicating that data is being transferred from 1, 1-2 to storage device 2
and a flip-flop 19 for instructing which of the storage devices 1-1 and 1-2 the input signal is to be stored.
, delay circuits 10-1, 10-2, 14, and AND gates 7-1, 7-2, 8-1, 8-2, 17
and orgate 9-1, 9-2, 15-1, 15
-2, 18, 20, 21, a clock signal 105 that provides sample timing of the input signal, and a clock signal 106 for controlling the display device.

Next, the operation of the tracer shown in FIG. 2 will be sequentially explained using FIG.

The case where the flip-flop 19 is in the "1" state will be explained.

The input signal 100 (which has already been processed in a known manner according to the sample mode, latch mode, etc. mode) is ANDed by the clock signal 105 and the output signal 121 of the flip-flop 19 by the AND gate 7-1. and its output signal 10
7-1 is used as a write signal for the storage device 1-1 to write to the address indicated by the counter 4-1, and then the OR gate 9-1 and the delay circuit 10
The counter is updated by the signal 110-1 that has passed through -1. Each time the clock signal 105 is output, the input signal 100 is written into the storage device 1-1 by the above operation.

When the trigger condition is satisfied at a certain timing, the trigger signal 111-1 is outputted from the trigger generation circuit 6-1. This trigger signal 111-1 is “1”
Then, flip-flop 12-1 is set, and flip-flop 19 and counter 4-1 are set.
1 and 5 are reset.

Since the flip-flop 19 has been reset, the input signal 100 is ANDed by the clock 105 and the complement output signal of the flip-flop 19 at the AND gate 7-2, and is used as a write signal for the memory device 1-2. The counter 4-2 is updated by the signal 110-2 which is then written to the address indicated by the counter 4-2 and then passed through the OR gate 9-2 and the delay circuit 10-2. Each time the clock signal 105 is output, the input signal 100 is written into the storage device 1-2 by the above operation.

On the other hand, since the flip-flop 12-1 is set and the counters 4-1 and 4-5 are reset, the input signal stored in the storage device 1-1 is transferred to the storage device 2 as the signal 101-1 and the selector 1.
6. Through the signal 120, the clock 106, the output signal 115-1 of the flip-flop 12-1, and the AND gate 8-1 are ANDed, and the data is sequentially transferred from address 0 by the write signal through the OR gate 20. be done.

When counter 5 overflows, signal 112
becomes "1", the flip-flop 12-1 is reset by the output signal 123 of the AND gate 17 via the OR gate 15-1, and data transfer from the storage device 1-1 to the storage device 2 is completed.

The display device 3 learns from the output signal of the OR gate 18 that the data transfer to the storage device 2 has been completed, and uses the clock signal 106 to sequentially read out the input signals for display stored in the storage device 2 to display the known data. Display by method.

In the tracer of the present invention, instead of providing only one storage means for storing input signals, two storage means are provided, so that the input signals written in the storage means can be transferred to the storage means for displaying the input signals. Since the signal can be written to another storage means, it is possible to prevent the input signal from being missed.
Furthermore, since the input signal for the last trigger signal can also be secured, there is an effect that failure analysis can be facilitated.

That is, the tracer of the present invention has two storage devices that sample and store input signals.
By having a means for instructing which storage device to store data in and a means for outputting the data at the time of the last trigger, it is possible to collect triggers that occur in a short period of time, which was previously difficult to collect. This has the effect of being able to collect the input signal history at the time of the last trigger.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1, 1-1, 1-2, 2...Storage device, 3...
Display device, 4, 4-1, 4-2, 5... Counter, 6, 6-1, 6-2... Trigger generation circuit,
7, 7-1, 7-2, 8, 8-1, 8-2, 17
...and gate, 9, 9-1, 9-2, 18,
20, 21... or gate, 10, 10-1, 1
0-2, 14...Delay circuit, 11, 12, 12-
1,12-2,19...Flip-flop, 10
0...Input signal, 105,106...Clock signal.

Claims (1)

[Claims] 1. Trigger generation means that outputs a trigger signal when an input signal satisfies a preset trigger condition, and outputs a status signal that alternately repeats a first state and a second state when the trigger signal is supplied. a state display means for writing and storing the input signal each time a clock signal is supplied when the state signal indicates the first state, and writing and storing the input signal when the state signal transitions to the second state; a first storage means for starting reading out the stored input signal; and a first storage means for writing and storing the input signal each time a clock signal is supplied when the state signal indicates the second state; a second storage means that starts reading out the stored input signal when the signal transitions to a first state; and a second storage means that starts reading out the stored input signal when the signal transitions to a first state, and reads out the input signal from the first storage means when the state signal indicates a second state. selecting means for selecting an input signal read from the second storage means when the state signal indicates a first state; and means for writing and storing the selected input signal and displaying the selected input signal. third storage means from which input signals stored are read out for display on the tracer.