JPS637495B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention utilizes an automatic repeat method, which is a type of error control method in data transmission.
Request (abbreviated as ARQ method) is particularly useful for data transmission that continuously sends data blocks over a line with a long response delay time, and can achieve high throughput (transmission This invention relates to a highly efficient automatic retransmission method that can obtain characteristics (efficiency).

The automatic retransmission method, or ARQ method, is an error correction method using automatic retransmission that has a response line, and is a continuous ARQ method that continuously sends data blocks.
As for the conventional GBN ( Go Back - N ) method,
The SR ( Selective - Repeat ) method is generally known. In the GBN method, when the transmitting side receives a retransmission request signal ( Negative - Ack Nowledgement, abbreviated as NACK) from the receiving side, the data block corresponding to the retransmission request signal (NACK) and all subsequent data are sent to the transmitting side. This method sends the block again. On the other hand, the SR method selectively retransmits only the data block corresponding to the NACK from the receiving side. These typical examples of conventional continuous ARQ methods each have their advantages and disadvantages.
A brief explanation will be given below with reference to FIGS. 1 and 2. Note that both Figures 1 and 2 are examples of a line in which the response delay time is 7 blocks long. Figure 1 shows the transmission and reception method of the GBN method, and Figure 2
This shows how to transmit and receive the SR method.

In FIG. 1, a represents a transmission block sequence, b represents a reception block sequence, and c represents a reception output sequence, respectively.
D ₁ , D ₂ , D ₃ ... are data blocks, and ACK
is an acknowledgment signal ( Ack nowledgement). Also, an X mark placed at the bottom of the receiving block row indicates that an error has been detected, and the data block marked with an
A NACK is sent, and an ACK is sent to the sender for correct data blocks for which no errors were detected. Therefore, in the case of Figure 1, the first NACK
Once sent to the third data block _D3 , since the response delay time of the line is 7 blocks long, the 7 data blocks _D3 to _D9 are sent next to the ninth data block _D9 . The data blocks are transmitted again and this retransmission is repeated (three times in FIG. 1) until an ACK is received for the data block _D3 . In the receive block sequence where the ACK was sent
The 24th data block _D3 is output to the receiving output string, and the 3rd to 23rd data blocks in the same receiving block string are discarded and are not output to the receiving output string. Thereafter, data blocks D ₄ , D ₅ ,
If a NACK is received for ..., the same retransmission as above is performed. However, in FIG. 1, the 25th and subsequent data blocks D ₄ , D ₅ ,
Since the data blocks D ₄ , D ₅ , . . . are correctly received, these data blocks D 4 , D 5 , . In this way, in the GBN system, among correctly received data blocks, only those in the correct numerical order are output as a received output string, and the others are discarded (Fig. 1c). in this case,
The receiving side has the advantage of not requiring buffer memory, but since many correctly received retransmitted data blocks are discarded, the throughput (transmission efficiency) η given by the following equation (1) is limited by the response delay time as in a satellite communication line. The disadvantage is that it deteriorates significantly over long lines.

η=1-P _B /1+P _B (N-1) ......(1) However, P _B is the block error rate of the line, N is the response delay time of the line expressed in the number of blocks, and a is the transmission b is the receiving block string, c is the receiving buffer input string,
d indicates each received output string. In this SR method,
When a NACK is received for the third data block _D3 , _D3 is transmitted again after the ninth data block _D9 after a delay of 7 blocks, and then _D10 is transmitted. Similarly, for other data blocks D ₅ , D ₁₀ , etc. for which NACKs have been received, only those data blocks are retransmitted, and this selective retransmission is repeated until an ACK is received (D ₃ in Figure 2 is retransmitted three times). resend). Then, all correctly received data blocks in the received block sequence are sequentially input to the buffer memory (Fig. 2c), and from the buffer memory, as shown in Fig. 2d, when the numerical order of the buffer input blocks is correct, _D1 , _D2 , _D3 , _D4 ,...
It is output sequentially as follows. Therefore, the throughput η in the SR method is given by the following equation (2), which exhibits ideal throughput characteristics independent of the response delay time.

η=1−P _B (2) However, in this SR method, it is necessary to store all previously correctly received data blocks in the buffer memory until the numerical order of the buffer input blocks is correct, and in order to avoid overflow, The disadvantage is that a large capacity (theoretically infinite) buffer memory must be prepared on the receiving side.

The present invention is intended to improve the drawbacks of the above-mentioned conventional technology in the continuous ARQ system, and its purpose is to simply prepare a small-capacity buffer memory on the receiving side when data blocks are continuously transmitted over a line with a long response delay time. The purpose of this invention is to provide an ARQ method that can obtain throughput characteristics close to ideal values. In order to achieve this object, the present invention provides a method for inputting only the correctly received new data block and the first correctly received retransmitted data block into the buffer memory at the receiving end, and inputting only the first correctly received retransmitted data block into the buffer memory at the transmitting end. The technical idea is to control the transmission of retransmitted data blocks and new data blocks so as to avoid overflow and improve throughput.

Hereinafter, the highly efficient continuous ARQ method according to the present invention will be explained in detail, and then the specific circuit configuration will be explained.

First, the transmission and reception control procedures in the system of the present invention will be explained in general terms. In this case, for ease of explanation, let the transmission data block sequence be D ₁ ,
Let D ₂ , D ₃ , ..., D _j , ... and the first error data block be D _j .

(1) Transmission procedure A From the time the transmitter receives the NACK of D _j from the receiver to a certain point, retransmission is performed using the SR method. In other words, from the time when the NACK of D _j is received until the time when the ACK of the D _j is received,
D _j is retransmitted every time NACK is received up to n times. During this retransmission, other data blocks D _l
(However, l>j), if _Dl is NACK, _Dl is retransmitted each time, and if _Dl is ACK, the next new data block is transmitted.

(2) Transmission procedure B Even by retransmission n times in the above transmission procedure A
If the ACK of D _j cannot be received, retransmission using this transmission procedure B is performed. That is, (n+1)
From the time when D _j 's NACK is received, D _j 's
Send D _j continuously until receiving ACK.
However, if a NACK for another data block D _l (l>j) is received during this continuous transmission, D _l is retransmitted once at that time.

(3) Transmission procedure C After the ACK of D _j is received on the transmitting side by the above transmission procedure A or the transmission procedure B after A, the subsequent data blocks of D _j are D _j+1 , D _j+2 ,... If there is an error in the error block, the one with the smaller number among the error blocks is regarded as the first error block and the process returns to transmission procedure A. However, if there is no error block after _Dj , new data blocks are transmitted sequentially.

(4) Receiving procedure The receiving side sends an ACK or NACK to the transmitting side depending on whether or not the transmitted data block is correctly received for any of the above transmission procedures A to C. Then, only the correctly received new data block and the first correctly received retransmitted data block are input into the reception buffer memory.

According to the procedures (1) to (4), the capacity of the reception buffer memory only needs to be able to store the buffer input block based on n retransmissions of D _j in transmission procedure A, so the response delay time is N. In the case of a block length, overflow on the receiving side can be avoided by simply setting the buffer memory capacity to (n+1)N block length. Furthermore, as the limit number of retransmissions n in transmission procedure A increases, the throughput characteristics in this case approach the ideal value of η = 1 - P _B (Equation (2)) in the SR method, but a relatively small value of n is sufficient. Good throughput can be obtained. The throughput characteristics of the method of the present invention were obtained by computer simulation using n as a parameter.
As shown in the figure. In FIG. 7, the solid line represents the block error rate (P _B ) for n=1, n=2, n=3, n=4, and n=10, taking the case of N=128 as an example.
The relationship with throughput (η) is shown respectively. Note that the throughput characteristics in the GBN method given by equation (1) and the throughput characteristics in the SR method given by equation (2) are shown in the figure by broken lines GBN and SR for reference comparison.

FIG. 3 specifically shows the transmission and reception system of the present invention, taking as an example the case where the response delay time is N=7 block length and the limit number of retransmissions in transmission procedure A is n=1. In Figure 3, a
is a transmission block sequence, b is a reception block sequence, c is a reception buffer input sequence, and d is a reception output sequence.

In FIG. 3a, from time t ₀ to t ₁ , step A
Since D ₃ is the first error block (see Figure 3b), the SR method
D ₃ is retransmitted only once. During this t ₀ to _{t 1}
D ₅ and D ₈ resulting in NACK are retransmitted using the normal SR method. Even if D ₃ was retransmitted according to procedure A, there was no ACK of D ₃ by time t ₁ , so transmission according to procedure B was performed from time t ₁ to t ₂ , and the second NACK of D ₃ was not received by time t 1. the time it was received
Continuously from t ₁ until time t ₂ when ACK of D ₃ is received.
D ₃ is sent. At the time when D ₁₀ NACK is received between t ₁ and _{t 2} , even if D ₃ is being continuously transmitted,
D ₁₀ is retransmitted. After the ACK for D ₃ is received by continuous retransmission of D ₃ according to procedure B, this
From the ACK reception time _t2 , the transmission of procedure C is performed, but until time _t2 , _D3 , _D5 , _D8 , and _D10 , which were error blocks earlier, all become ACKs, so
New data blocks D ₁₄ , D ₁₅ . . . are transmitted in sequence.

In response to the above transmission, on the receiving side, as shown in Figure 3c,
Of the many retransmitted data blocks _D3 that have been continuously retransmitted in accordance with procedure B, only the first one that becomes ACK is input to the buffer memory. Then, as shown in Figure 3d, the new data block that has been correctly received
After D ₁ and D ₂ are output from the buffer memory, the 10 subsequent data blocks D ₄ to D ₁₈ that have already been input to the buffer memory are not stored until the retransmission D ₃ is input to the buffer memory. There is no output. In this case, if the capacity of the buffer memory on the receiving side is (1+1)×7=14 block lengths, no overflow will occur.

FIG. 4 shows the general configuration of a data transmission device that implements the system of the present invention. In the figure, 1 is the transmission buffer memory, which receives the ACK of the transmitted data block.
This is a memory that holds the transmitted data block until it is received, and a memory capacity of N blocks, which is the same as the response delay time of the line, is sufficient. Reference numeral 2 denotes a data transmitting device, which transmits input data from the transmitting buffer memory 1 in a predetermined format.
3 is a receiving device on the transmitting side, which receives the response signal from the receiving side.
This is a device for detecting whether it is ACK or NACK. Reference numeral 4 denotes a transmission control device which controls data transmission from the transmission buffer memory 1 to the data transmission device 2 in response to a detection signal (ACK/NACK) from the transmission receiving device 3.
This is a device that controls data blocks sent to. Reference numeral 5 denotes a data receiving device, which receives a transmission data block from the transmitting side. Reference numeral 6 denotes a reception monitoring device, which is a device for determining whether or not the data receiving device 5 correctly receives a data block. Reference numeral 7 denotes a reception output control device, which controls the reception data blocks of the data reception device 5 according to the determination result of the reception monitoring device 6, and outputs only correctly received data blocks in numerical order. Built-in. Reference numeral 8 denotes a receiving side transmitting device, and according to the determination result of the receiving monitoring device 6,
This is a device for sending ACK or NACK as a response signal to the transmitting side. 9 is a communication line. In the device configuration shown in FIG. 4, the transmission control device 4 on the transmitting side and the reception output control device 7 on the receiving side are different from those in the conventional continuous ARQ system. Hereinafter, a specific example of the configuration of the transmission control device 4 will be explained with reference to FIG. 5, and a specific example of the configuration of the reception output control device 7 will be explained with reference to FIG.

FIG. 5 shows the transmission control device 4 (within the two-dot chain line) together with the transmission buffer memory 1. The transmission buffer memory 1 is implemented as a random access memory.
The transmission control device 4 includes a block number detection circuit 10
This is realized by a write address designation circuit 11, a write address holding memory 12, a read address designation circuit 13, an ACK end confirmation block number holding memory 14, and a transmission procedure determination circuit 15. That is, the block number detection circuit 10 is a circuit for detecting the block number of the input data block a to the transmission buffer memory 1. The write address designation circuit 11 is a logic circuit, and is based on the information signal f indicating the ACK reception block number from the transmitting receiving device 3 and the information signal d indicating the state of the write address in the transmitting buffer memory 1 from the write address holding memory 12. Then, an address signal c designating the write address number of the input data block a corresponding to the block number indicated by the information signal b from the block number detection circuit 10 is sent to the transmission buffer memory 1 and the write address holding memory 12. That is, by the block number detection circuit 10, write address designation circuit 11, and write address holding memory 12, data blocks that have already received an ACK are sequentially erased from the transmission buffer memory 1, and data blocks that have not yet received an ACK, including new data blocks, are stored in the transmission buffer memory 1. N blocks of data corresponding to the line response delay time are stored. On the other hand, the read address designation circuit 13 is also a logic circuit, and the information signal f from the transmitting side receiving device 3 is
(ACK reception block number display) and the information signal e indicating the NACK reception block number, the information signal d from the write address holding memory 12 (indication of the write address state in the transmission buffer memory 1), and transmission from the transmission procedure determination circuit 15. Step A,
Upon receiving the information signal g specifying the selection of B and C,
Address signal h specifying the address number of the data block to be read from transmission buffer memory 1
is sent to the transmission buffer memory 1 and the ACK unconfirmed block number holding memory 14. Also j
is the read data block. Also,
The ACK unconfirmed block number holding memory 14 transmits the data based on the information signal d from the write address holding memory 12 and the address signal h from the read address designation circuit 13 (designating the address of the data block to be read from the transmission buffer memory 1). It identifies the block numbers and stores and holds the block numbers of the transmitted data blocks in order until it receives the ACK information signal f from the transmitting receiving device 3. The transmission procedure determination circuit 15 is a logic circuit, and determines the transmission procedure to be used among transmission procedures A, B, and C from the order of ACK unconfirmed block numbers stored in the ACK unconfirmed block number holding memory 14, and selects one of the transmission procedures. The information signal g specifying whether it is a transmission procedure is output. Note that i is
This is a signal from the ACK unconfirmed block number holding memory 14. That is, the transmission procedure determination circuit 15
ACK The lowest block number stored in the unconfirmed block number holding memory 14 is detected, and as long as the block number is stored, selective retransmission of the data block of that block number is performed up to n times. Specify A to the read address designation circuit 13, and then specify subsequent continuous retransmission, that is, transmission procedure B, and when the memory of the block number disappears, change the transmission procedure to C and transmit to the next lowest block number. It instructs step A.
In response to this, the read address designation circuit 13
This causes the transmission buffer memory 1 to read a new data block, a data block retransmitted up to n times, an interrupt retransmission block, and a continuous retransmission block.

FIG. 6 shows the configuration of a reception output control device 4 on the reception side, which includes a reception buffer memory 16 and a write address designation circuit 1.
7 and write/read address holding memory 1
8 and a read address designation circuit 19. Then, the reception buffer memory 16 is (n+
1) It is realized by a random access memory of ×N block length, and its function is to write only correctly received data blocks k from the data receiving device 5 according to the judgment result from the receiving monitoring device 6, and The written data blocks are outputted to the outside as an output data block m until they are in the correct numerical order. This write/read control is performed by a write address designation circuit 17, a write/read address holding memory 18, and a read address designation circuit 19. This write address designation circuit 1
Reference numeral 7 denotes a reception buffer memory 16 which receives the information signal o from the reception monitoring device 6 indicating the ACK reception block number which is the number of the data block that the reception monitoring device 6 has determined to be correctly received, and also receives the information signal o from the write/read address holding memory 18. The receiving buffer memory 16 receives an address signal q specifying the address number of the correct data block to be written to the receiving buffer memory 16.
and write/read address holding memory 18
This is a logic circuit that sends data to This write/read address holding memory 18 receives the write address signal q from the write address designation circuit 17.
and the read address signal r from the read address designation circuit 19, respectively. The read address designation circuit 19 is a logic circuit that receives the write address signal q' stored in the write/read address holding memory 18 and selects the correct block number among the data blocks written in the reception buffer memory 16. The relevant reception buffer memory 16 up to the point where
A read address signal r indicating the address number to be read is sent out. That is, a correctly received data block is stored in the reception buffer memory 16 with its block number and address number associated with each other in the holding memory 18, and then read out by the read address designation circuit 19 with reference to the contents of the holding memory 18. The blocks are read out from the reception buffer memory 16 in correct block number order. Data block receives buffer memory 1
6, the correspondence of the data block in the holding memory 18 is erased and a new correct data block is written.

As explained in detail above, according to the ARQ method of the present invention, that is, the automatic playback method, the conventional continuous ARQ
Compared to the GBN method, which is a typical example of this method, the throughput characteristics are significantly improved, and even if the buffer memory on the receiving side required for this is small, it will not overflow. Characteristics extremely close to ideal throughput characteristics can be obtained.

[Brief explanation of the drawing]

Figures 1 and 2 are explanatory diagrams for explaining two typical examples of conventional continuous ARQ methods, Figure 3 is an explanatory diagram for explaining the present invention method, and Figure 4 is an explanatory diagram for explaining the present invention method. 5 is a block diagram showing an example of the main part of the transmitting side of FIG. 4, and FIG. 6 is a block diagram showing an example of the main part of the receiving side of FIG. 4. , FIG. 7 is a graph showing the throughput characteristics of the system of the present invention in comparison with that of the conventional system. In the drawing, 1 is a transmission buffer memory, 2 is a data transmitter, 3 is a transmitting side receiving device for ACK/NACK detection, 4 is a transmission control device, 5 is a data receiving device, 6 is a reception monitoring device, and 7 is a reception output control device. Device,
8 is a receiving side transmitter for sending ACK/NACK, 9
is a communication line, 10 is a block number detection circuit, 11
1 is a write address designation circuit, 12 is a write address holding memory, 13 is a read address designation circuit, 14 is an ACK unconfirmed block number holding memory, 15 is a transmission procedure determination circuit, 16 is a reception buffer memory, 17 is a write address designation circuit, 1
8 is write/read address holding memory, 1
9 is a read address designation circuit, D ₁ , D ₂ , D ₃ ,
... is the data block, n is the limit number of retransmissions,
ACK is an acknowledgment signal, NACK is a retransmission request signal,
a is the input data block, b is a signal indicating the block number, c is a signal specifying the write address number, e is a signal indicating the NACK reception block number,
f is a signal indicating the ACK reception block number, g is a signal specifying the selection of the transmission procedure, h is a signal specifying the address number of the data block to be read from the transmission buffer memory, j is the transmission data block, k is the reception data block, m is the output data block, o is a signal indicating the block number of the data block determined to be received correctly, q is a signal specifying the address number of the data block to be written to the reception buffer memory, r is the address of the data block to be read from the reception buffer memory This is a signal that specifies a number.

Claims (1)

[Claims] 1. In data transmission using error control, which has a line for the receiving side to respond to data blocks from the sending side and automatically retransmits data blocks corresponding to retransmission request signals, the receiving side Only the received new data block and the first correctly received retransmission data block are stored in the buffer memory, and the data blocks are read out from the buffer memory in the correct numerical order, and on the transmitting side, the data block corresponding to the first received retransmission request signal is stored. Until it receives an acknowledgment signal for the first retransmission request signal, retransmission is performed each time a retransmission request is made up to a predetermined number of times, and continuous retransmission is performed for subsequent retransmission requests, and an acknowledgment signal is sent for the data block corresponding to the first retransmission request signal. After receiving the signal, the data block corresponding to the first received retransmission request signal is retransmitted the predetermined number of times and continuously retransmitted until the acknowledgment signal is received, and this is repeated thereafter. Automatic retransmission method for data transmission.