JPS637637B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a timing circuit for an electronic watch, and in particular to an improvement in a method for timing hours, minutes, and seconds using three timing switches. Conventionally, as a method for adjusting the clock mode of an electronic watch with a digital display, a method has been proposed in which three timing switches are provided, each of which serves as a switch for correcting hours, minutes, and seconds. Although this method is relatively easy to understand and convenient for the user, it has the disadvantage that it is difficult to make minute corrections. Generally, when making corrections using a push button switch, pressing it once will
There is a method in which the display is fast-forwarded while the switch is pressed, but in the former method
Correcting the time from 00 minutes to 59 minutes requires pressing the switch a maximum of 59 times, which can be said to be impractical. In the latter method, if the timing of releasing the push button switch is a little late, it will go too far, and if the fast forward speed is slow, it will take too much time to make corrections, which is also inconvenient. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to realize a timing system that is convenient for the user. In the present invention, there are three timekeeping switches in clock mode, each of which adjusts the hour digit, 10 minute digit, and 1 minute digit. Seconds can be adjusted by changing the lock switch, which determines whether the function of these timing switches is enabled or disabled, from the locked state (no correction even if the timing switch is pressed) to the unlocked state (correction when the timing switch is pressed). This is performed at the first input of the minute digit after the clock mode is selected from another mode with the lock switch in the unlocked state. According to such a method of the present invention,
The minute adjustment is divided into 10 minutes and 1 minute, making it easy to adjust the time. The present invention will be explained in detail below with reference to the drawings. FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment shown in FIG. 1. The following description will be made with reference to FIG. 2. Reference numeral 1 is a lock switch that determines whether the timing switch is enabled or disabled.As will be described later, when lock switch 1 is turned on, timing switches 2, 3,
4 input becomes valid. 5 is a mode selection switch, and in this embodiment, it has five modes: clock, alarm, calendar, timer, and stopwatch, and each mode is CL, AL, CA, TM, and STW as shown in the drawing. When the terminal is selected, that mode is selected. (Also, the function of the timing switch changes according to the selected mode, as described below.) Now, as shown in FIG.
When the CL terminal is selected from the other terminals by the mode changeover switch 5 in the off state, this terminal becomes "H" (V _DD ) level. This signal is
As shown in Figure 1, a D-type flip-flop (hereinafter referred to as D
-FF) 6 and 7, their output signals Q ₂₁ and Q ₂₂ are connected to the clock signal CLK.
Accordingly, it changes as shown in FIG. Therefore, the output a of the exclusive OR circuit (hereinafter abbreviated as EX-OR circuit) 8 also changes as shown in FIG. This signal a is input to the reset terminal Re of the JK flip-flop circuit (hereinafter abbreviated as JK-FF) 10 via the OR circuit 9, and resets the JK-FF, and its output _Q31 is output regardless of the previous state. It becomes "L" ( _Vss ) level. At this time, since the lock switch 1 is off, as is clear from FIG. 2, the output C of the AND circuit 14 is also "L".
Therefore, timing switches 2 to 4 are used as input signals.
AND circuits 15 to 17 are closed, and even if this timing switch is turned on, it has no effect. Next, when the lock switch is turned on, the outputs Q ₁₁ and Q 12 of the D-FFs 11 _{and 12} become "H" in sequence according to the clock signal CLK, as shown in FIG. At this time, the output b of the EX-OR circuit 13 becomes a signal as shown in FIG.
The FF10 is reset, but since it has already been reset as described above, the state of the output _Q31 does not change. Moreover, the output C of the AND circuit 14 is “L”
Since the signal from each timing switch 2 to 4 connected to the AND circuits 15 to 17 becomes "H" from
The state becomes ready for input. Now, the mode is selected as clock mode and lock switch 1 is unlocked.
It is now possible to adjust the time. Here, time switch 2
When is pressed, the output d of the AND circuit 15 becomes the second
As shown in the figure, it becomes "H". This signal is then sequentially input to the D-FFs 16 and 17. As a result, the outputs Q ₄₁ , Q ₄₂ of D-FF, AND circuit 18
The output e changes as shown in FIG. This signal is input to AND circuits 20 and 21,
When the signal e changes from “L” to “H”,
Since the output Q ₃₁ of the JK-FF 10 remains “L”, the signal at this time passes only through the AND circuit 21 . The output f of the AND circuit 21 is transmitted to a seconds reset circuit of a clock circuit (not shown) to reset the seconds. (At this time, to reset the seconds, even if you carry it up to minutes and display "00", do not simply carry it up.
It may be set to “00” seconds. ) Then, timing switch 2
is released and turned off, the outputs Q ₄₁ and Q 42 of the D-FFs 16 and ₁₇ change sequentially as shown in the second diagram, and the output e of the AND circuit 18 changes as in the case described above.
becomes “L”. This signal change from "H" to "L" is transmitted to the JK-FF10 via the inverter 19.
Since it is input to the clock input CL of
_Q31 changes from "L" to "H". Note that when the timing switch 2 is pressed again after the seconds are reset, the output d of the AND circuit 15 becomes "H" again.
This signal is transmitted to the D-FF16, as in the case described above.
17. Change the AND circuit 18 as shown in Figure 2,
The input is input to the AND circuits 20 and 21, but the AND circuit 21 is closed because the output ₃₁ of the JK-FF10 is "L", and this time it passes through the AND circuit 20, and its output g is "L". This signal is transmitted to a one-minute digit correction circuit of a clock circuit (not shown) and changes the display to +1 minute. Then, when the timing switch 2 is released again and turned off, the D-FF 16, 17 AND circuit 18 changes as shown in FIG. 2, as in the case described above. At this time, JK−FF
The clock input CL changes from "H" to "L" again, but if the connection is made as shown in FIG. 1, the second and subsequent signal changes are ignored and the state does not change. Therefore, no matter how many times the timing switch 2 is pressed, only the one-minute digit is corrected unless the lock switch 1 or mode changeover switch 5 changes. When timing switch 3 is pressed, like timing switch 2, D-FF22, 23AND circuit 24
are connected, and the operation is the same during this time.
The input signal of the timing switch 3 is transmitted via the AND circuit 25 to a 10-minute digit correction circuit of a clock circuit (not shown), and the display is increased by +10 minutes. Timing switch 4
Similarly, if is pressed, D-FF26,27AND
The signal is transmitted via circuits 28 and 29 to the hour digit correction circuit of the clock circuit (not shown), and the display is changed to +1.
Make it time. (Of course, in the case of 1 minute digit correction, when the display reaches 9 minutes, the next input will be 0.
It will be a minute. Thereafter, each digit changes cyclically in the same way. ) In the above, the clock mode is selected first,
Next, we have described the operation when the lock switch is turned on, but the same applies even when the lock switch is turned on first and then the watch mode is selected. As mentioned above, immediately after the lock switch is turned on and immediately after the clock mode is selected, the outputs b and a of the EX-OR circuits 13 and 8 are always
Since JK-FF remains "H" for a certain period of time, JK-FF is reset, so that the subsequent input signal to the timing switch 2 necessarily passes through the AND circuit 21 and resets the seconds in the clock circuit. Furthermore, depending on the signal from the mode selection switch, the five AND circuit groups A, B, C, D, and E are connected to each circuit in order to use timing switches 2 to 4 in common in each mode. This is a switching circuit. That is, when the clock mode is selected and the CL terminal becomes "H", all AND circuits except A are cut off, and the alarm mode is selected.
When the AL terminal becomes “H”, other than B
All AND circuits are cut off. The same applies to the calendar timer and stopwatch. The output of each AND circuit group is connected to a circuit (not shown) for modifying each mode or giving operation instructions. An example of the relationship between the selected mode and the function of the timing switch is shown in the table below.

[Table] Also, D- connected to timing switches 2 to 4.
FFs 16, 17, 22, 23, 26, and 27 are for eliminating chattering of each switch. As described above, according to the present invention, time adjustment, which conventionally took a long time and was difficult to operate, can be done easily.
It can be easily improved by adding a simple circuit. In addition, according to this method, corrections and operation commands for modes other than clock mode can be made using the three timing switches without compromising consistency and maintaining ease of use. This is a very convenient digital watch for people.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation, where 1 is a clock switch, 2 to 4 are timing switches, and 5 is a mode. Selection switch, 10
JK flipflop.

Claims (1)

[Claims] 1. Mode switching means for switching between a plurality of modes, and when the clock mode is selected, an hour digit, a ten minute digit,
An electronic timepiece comprising respective timing switches for timing one-minute digits and a lock switch means for selecting enable or disable of the function of the timing switch, wherein the lock switch means controls the function of the timing switch. a first pulse generating circuit that generates a pulse immediately after being enabled from a disabled mode; a second pulse generating circuit that generates a pulse immediately after being switched from another mode to a clock mode by the mode switching unit; a holding circuit which uses pulses generated by the first and second pulse generating circuits as a reset signal and receives a signal from a timing switch for timing the one-minute digit as an input; and a holding circuit for timing the one-minute digit. The timing switch signal,
An electronic timepiece comprising a gate circuit for switching and inputting an output from the holding circuit to a second reset circuit or a minute digit correction circuit.