JPS63836B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern normalization system that processes a digital image signal of a character pattern read by, for example, an optical character reading device to generate an image signal of a character pattern whose height, inclination, etc. are normalized. Regarding the conversion method.

In a character reading device, when it is necessary to normalize the height, slope, etc. of a read character pattern, processing speed, scale and flexibility of processing hardware, etc. are important issues.

The present invention was made in view of the above circumstances, and
Two RAMs are provided for storing pattern images, and a microprocessor is used to normalize the height and slope of the character pattern stored in one RAM before transferring it to the other RAM, resulting in high-speed processing. The present invention provides a pattern normalization method that can perform normalization processing on pattern images using relatively simple hardware.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, 1 and 2 are a first image RAM and a second image RAM. The output terminal of the first RAM 1 and the input terminal of the second RAM 2 are connected to a pattern line 3, which in turn is connected to a microprocessor 4. Also,
Each of the RAMs 1 and 2 can be accessed two-dimensionally by a row-direction address counter 5 and a column-direction address counter 6, respectively. The address counters 5 and 6 have their address data input lines connected to a data bus 7, which in turn is connected to the microprocessor 4.
The address counters 5 and 6 are controlled by the microprocessor 4 so that control pulses necessary for clearing, incrementing, decrementing, loading, etc.
Supplied from. Further, the RAMs 1 and 2 are supplied with read (R) signals and write (W) signals from the microprocessor 4.

Assume that the first RAM 1 stores, for example, a digital image signal of a character pattern as shown in FIG. 2a. This digital image signal is, for example, a signal obtained by scanning an image sensor in a character reading device according to the shading of each pixel of an image, which is digitized and then sequentially written to each address of the RAM 1. Figure 2a
, Y ₁ and Y ₂ are the row direction addresses corresponding to the upper and lower limits in the height direction of the character pattern,
The number of line addresses H ₁ between Y ₁ and Y ₂ corresponds to the height of the character pattern. Further, S is the number of column-direction addresses corresponding to the inclination of the character pattern. The number _H1 of row-direction addresses corresponding to the height of these character patterns and the number S of column-direction addresses corresponding to the slope are obtained by a well-known method.

In addition, FIG. 2c shows a second RAM 2 to which the character pattern of the first RAM 1 is normalized and transferred.
An example of the desired pattern position is shown below. Here, H ₀ is the number of addresses in the row direction corresponding to the height of the character pattern.

Next, the operation of the microprocessor will be explained according to the algorithm shown in FIG. First, the initial settings are the row address counter of the first RAM1 (hereinafter referred to as the first counter _C1 ) and the second RAM1.
Each row address counter (hereinafter referred to as second counter _C2 ) of RAM2 is cleared. next,
Load address _Y1 data into the first counter _C1 . Next, the content of the first counter C ₁ (C ₁ ) and the content of the second counter C ₂ (C ₂ ) are compared and determined. When the determination result is (C ₁ )≧(C ₂ ), the second counter C ₂ is incremented and the second RAM 2 is
After incrementing the row address, the comparison and determination are performed again. Then, the judgment result is (C ₁ )
(C ₂ ), the contents of the first counter C ₁
Add H ₁ /H ₀ to get the row address of the first RAM1
Advance by H ₁ /H ₀ . After this, the first RAM1
The column address counter 6 of the first RAM 2 and the column address counter 6 of the second RAM 2 are sequentially scanned.
A signal read from the second RAM 1 as a read signal is written to the second RAM 2 through the pattern line 3 as a write signal. As a result, the character pattern in the first RAM 1 is deleted by lines H ₁ /H ₀ and transferred by one line. The number of transfers is counted and it is determined whether the count result is _H0 or not. and,
When it is determined that H is not ₀ , the second counter _C2 is incremented and the first counter _C1 is incremented again.
Add H ₁ /H ₀ and perform one line transfer. This operation is repeated until the number of transfers becomes equal to H ₀ , and the transfer ends. Therefore, the first
This means that the character pattern in RAM1 is transferred in a form in which the lines are deleted at line intervals of H ₁ /H ₀ and the height is normalized.

When transferring the above line, the microprocessor 4
By controlling the scanning start position of the column direction address of the first RAM 1 to be shifted according to the inclination of the character pattern, that is, as shown in FIG.
The row direction address of the transfer line is Y ₃ as shown in
Then, by varying the initial value of the column address counter 6 of the first RAM 1 by Y ₃ −Y ₁ /H ₁ S,
The slope of character patterns can be normalized and transferred.

According to the pattern normalization method described above, two RAMs are provided for storing pattern images, and one
The height and inclination of the character pattern stored in the RAM are detected, and the line image of the pattern part is intermittently thinned out from one RAM so that it reaches a predetermined height to be normalized, and the line direction of the second RAM is It is controlled by a microprocessor so that the image is transferred continuously, and the column address of the transfer line image is changed in accordance with the inclination of the character pattern and the position of the transfer line. Therefore, the processing hardware is relatively simple and normalizes the height and slope of the pattern at the same time.
Its processing efficiency has been doubled, and high-speed processing is possible by using a high-speed microprocessor and setting effective microinstructions.

The above embodiment has been explained using an algorithm that normalizes the height of the pattern in the first RAM in the reduction direction, but conversely, the height of the pattern in the first RAM is Control may also be performed according to an algorithm that normalizes in the expansion direction by transferring a number of lines while inserting them.

As described above, the present invention can provide a pattern normalization method that is capable of high-speed processing and can normalize pattern images using relatively simple hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the pattern normalization method according to the present invention, and FIG. 2 is shown to explain how a pattern is transferred from the first RAM to the second RAM in FIG. 3 are flowcharts showing an example of an algorithm for pattern height normalization in the pattern transfer of FIG. 2. 1, 2...RAM, 3...Pattern line, 4
...Microprocessor, 5,6...Address counter.

Claims (1)

[Claims] 1. A pattern original image stored in a first random access memory is normalized and stored in a second random access memory, and the inclination and height of the original image in the first memory are normalized. The first step is to detect and calculate the height ratio with the normalized image. a second step of increasing the row address counter of the first memory for each address amount according to the ratio determined in the first step; A third step of reading one line of image signals at the address specified in the second step from the first memory. A fourth step of transferring and storing the image signal read in the third step to a second memory. A fifth step of incrementing the address counter of the second memory row by row. a step of repeating the second to fifth steps according to the number of lines of the image after normalization; A pattern normalization method characterized in that image tilt correction and height normalization are performed simultaneously by correcting the contents of a column address counter of a memory.