JPS638477B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fluorescent display device that displays the level of a signal using a fluorescent display tube.

For example, a conventional fluorescent display device for audio equipment is shown in FIG. Required level display -30, -20,...
...The fluorescent display panel 1 marked with +5 dB consists of n segments (anodes) 2 arranged in parallel to each other.
₁ to 2n, each segment 2 1 to 2n is formed of one fluorescent display tube consisting of a grid 3 to which a driving voltage is applied from a power source _{E 0} and a filament (not shown) to which a required voltage is applied. It is connected correspondingly to each of the comparator circuits 4 ₁ to 4n of the same number as the segments 2 constituting the segment drive circuit.
The detection output of the audio signal detected by the required peak or VU detection circuit 5 is commonly applied to one input terminal of the comparison circuits 4 ₁ to 4n, and the level is changed in stages to the other input terminal. Reference voltages _E1 to En, which increase in number, are applied in order from the comparator circuit ₄₁ to the comparator circuit 4n, and in response to the level of the detection output, a required number of segments 2 are turned on simultaneously from the lowest level side.

By the way, if such a fluorescent display tube is used to display a wide level range with high precision, a large number of segments will be required, but the conventional device described above requires the same number of drive circuits as segments, so the circuit It has the disadvantage that it becomes large and expensive, and this disadvantage is particularly noticeable in audio equipment because it usually displays two channels, L and R.

The present invention solves the drawbacks of such conventional devices, and will be described in detail below with reference to the drawings.

FIG. 2 shows a circuit diagram of an embodiment in which the device of the present invention is applied to a signal level display device for audio equipment such as a tape recorder, and there are eight fluorescent display panels 6 _L and 6 _R for each of the L and R channels. Segment 7 ₁ ~
Six identical fluorescent display tubes 8 _L and 8 _R , in which the fluorescent display tubes 7 and ₈ are arranged parallel to each other, are arranged so that the segments are parallel to each other in the parallel direction of the segments. 9
_L and 8 _R are L and R fluorescent display tubes 8 _L and 8 _R, respectively.
Although not shown, a required voltage is applied to the filaments of each of the fluorescent display tubes 8 _L and 8 _R. Each segment ₇₁ at the lowest level in each of the fluorescent display tubes 8L and 8R of the _L and _R channels is connected to a first counter via an L/R changeover switch _S1 formed by an analog switch or the like. 10 output terminal Q ₁ and the display tube side ground (not shown) are connected in parallel, and similarly, each segment 7 ₂ to 7 ₈ in each display tube 8 _L and 8 _R has a corresponding L/R switching. The corresponding output terminals Q ₂ ~ of the first counter 10 via switches S ₂ ~ S ₈
Connected in parallel between Q ₈ and ground. In addition, each grid terminal _9L of each display tube _8L of the L channel is connected to a switch _S9 to _S14 formed of a corresponding analog switch or the like and an L/R changeover switch _S15 to
Through the L side terminal of _S20 , each grid terminal _9R of each display tube _8R of the R channel is connected to the corresponding similar switch _S21 to _S26 and the R of L/R changeover switch _S15 to _S20 . It is connected to the corresponding output terminals Q ₉ to Q ₁₄ of the second counter 11 via the side terminals. The first and second counters 10 and 11 are the same counters, and for the fluorescent display tube consisting of eight segments in the embodiment, octal counters are used, and for example, counters in octal are used, such as those commercially available from Tokyo Shibaura Electric Co., Ltd. There is
Octal Counter (product number TC4022P) is preferred. Although this TC4022P is an integrated circuit having 16 terminals, only the terminals necessary for explaining the operation of the present invention are shown in FIG. The output terminals Q ₉ to _{Q 14} of the second counter 11 are the output terminals Q ₁ of the first counter 10.
〜Q ₆ , but the counter 11 corresponding to the output terminals Q ₇ and Q ₈ of the first counter 10
The output terminal of is omitted. The first and second counters 10 and 11 each have a clock terminal _CL , a reset terminal _CR and a carry-out terminal Co, and the carry-out terminal Co of the first counter 10 is connected to the clock terminal _CL of the second counter 11. However, the carry out terminal Co of the second counter 11 is open. Each counter 10,
The operation of step 11 will be explained using the time chart in Figure 3. In the following explanation, the “High” level of the signal
Alternatively, the "Low" level state is simply expressed as "H" or "L". Output terminal Q ₁ (and Q ₉ ) responds to the reset pulse applied to reset terminal _CR and changes from “L” to “H” at the rising edge of the reset pulse.
rises to the “H” state, and the clock terminal
When a series of clock pulses are applied to C _L , it falls from "H" to "L" at the rising edge of the first pulse, followed by the 8th and 9th, the 16th and 17th, and so on. It outputs "H" between each rising edge of the clock pulse. The output terminal Q ₂ (and Q ₁₀ ) is normally in the "L" state, and when a series of clock pulses are applied to the clock terminal C _L , it rises from "L" to "H" at the rising edge of the first clock pulse.
“H” at the rising edge of the second clock pulse →
The clock pulse falls to "L" and outputs "H" between the rising edges of the first and second clock pulses, and each of the subsequent 9th and 10th, 17th and 18th, etc. clock pulses. Outputs “H” during the rising edge.
Similarly output terminals Q ₃ (and Q ₁₁ ), Q ⁴ (and Q ₁₂ ), Q ₅
(and Q ₁₃ ), Q ₆ (and Q ₁₄ ), Q ₇ and Q ₈ are normally in the "L" state, as is the output terminal Q ₂ (and Q ₁₀ ), and a series of clock pulses is applied to the clock terminal C _L. When is applied, the output terminals Q ₃ (and Q ₁₁ ) are the 2nd and 3rd, 10th and 11th, ..., output terminals
Q ₄ (and Q ₁₂ ) are 3rd and 4th, 11th and 12th
Output terminal Q ₅ (and Q ₁₃ ) is the 4th and 5th, 12th and 13th, ..., output terminal
Q ₆ (and Q ₁₄ ) are the 5th and 6th, 13th and 14th, ..., output terminal Q ₇ is the 6th, 7th, and
The 14th and 15th, . . . , and output terminal _Q8 output "H" between the rising edges of the 7th and 8th, 15th and 16th, . . . clock pulses, respectively.
The carry out terminal Co is normally in the "H" state, and when a series of clock pulses are applied to the clock terminal C _L , it first falls from "H" to "L" at the rising edge of the fourth clock pulse, and then goes from "H" to "L" at the rising edge of the fourth clock pulse. “L” at the rising edge of the 8th clock pulse of
→ rises to “H”, then falls from “H” to “L” at the rising edge of the 4th and 12th clock pulse, and similarly follows the 16th and 20th, 24th and 28th clock pulses.
It outputs "H" between each rising edge of the th, . . . th clock pulse.

Here, the output of the carry-out terminal Co of the first counter 10 is applied to the clock terminal C _L of the second counter 11 as a clock pulse, so that a series of clock pulses is applied to the clock terminal C _L of the first counter 10. is applied,
First, during the period in which the first output terminals Q ₁ to _{Q 8} become “H” in sequence, the output terminal of the second counter 11
Q ₉ outputs "H", and the output terminals Q ₁₀ , Q ₁₁ ... sequentially output "H" for the second, third, etc. times, and the first and second counters 10 and 11 output "H". 1st
The number of pulses applied to the clock terminal of the counter 10 is counted, and output signals which are sequentially switched to the output terminals _Q1 to _Q14 are outputted according to the counted number. This count state is “H” at the reset terminal _CR .
It is cleared when the reset pulse of
The outputs of the output terminals Q ₁ , Q ₉ and the carry-out terminal Co are "H", and the outputs of the other output terminals are "L".
Such counters 10, 11 and fluorescent display tubes _8L , _8R
By applying a series of 48 clock pulses to the clock terminal C _L of the first counter 10, the output terminals Q ₁ to Q ₁₄ can have 48 sets of different output states that switch every clock pulse. At the same time, with this output, each of the 48 segments constituting each of the fluorescent display panels 6 _L and 6 _R of the L and R channels can be blinked one by one starting from the lowest level side.

The clock terminal C _L of the first counter 10 is connected to the output of the NAND circuit 12. An oscillator 13 oscillates at one input terminal of the NAND circuit 12.
1/2 ^m (m=1, 2, 3,
...9) Divide the frequency, and Figure 4 a to d (Figure 4 a to d are continuous parts divided into four, and the joint points are indicated as a, b, c, and d in the figure, respectively) from a frequency divider 14 that forms nine pulse signals of different frequencies with the phase relationship shown in the time chart.
A 12.8kHz pulse signal is applied, and the other input terminal is connected to the detection output of the signal under test and the function generator 15.
The output of the function generator 15 is connected to the output of a comparator 16 which compares the levels of the outputs of the function generator 15 and outputs "H" during a period in which the level of the detected output is higher than the level of the output of the function generator 15. Therefore, as shown in FIG. 3, the clock terminal C _L of the first counter 10 is connected to the frequency divider 14 from the NAND circuit 12 during the period when the output of the comparator 16 is "H".
The 12.8kHz pulse signal formed by
A 12.8kHz pulse signal is applied. Input terminal 1
7 and 18 are input terminals to which the detection outputs of the L channel and 19 and 20 of the R channel are applied,
The input terminals 17 to 20 are connected to one input terminal of the comparator 16 via switches S ₂₇ to S ₃₀ formed by analog switches or the like, respectively. According to the switching of the manual operation switch S ₃₁ , the peak detection output (or VU detection output) is input to input terminals 17 and 19, and the peak hold detection output (or peak detection output) is input to input terminals 18 and 20, respectively. . The detection output is formed by a well-known detection circuit, so a detailed explanation will be omitted.
The peak hold detection output is obtained by holding the peak level for several seconds in peak detection. ON and OFF of the switches _S27 to _S30 are controlled by the outputs of the corresponding AND circuits 21 to 24, respectively.
ON when the outputs of AND circuits 21 to 24 are “H”
Then, the detected output is applied to the comparison circuit 16. A frequency divider 1 is connected to one input terminal of the AND circuits 21 and 22.
The pulse signal from 4 to 50Hz is also connected to the AND circuit 2.
A 50Hz pulse signal obtained by inverting this 50Hz pulse signal with an inverter 25 is input to one input terminal of the AND circuits 21 and 24, and a 100Hz pulse signal from the frequency divider 14 is input to the other input terminal of the AND circuits 21 and 23. Also, the other input terminal of the AND circuits 21 and 24 has this
The 100Hz pulse signal was inverted by inverter 26.
A 100Hz pulse signal is applied. Therefore, the switches S ₂₇ to S ₃₀ are to
(=5msec) S ₃₀ →S ₂₉ →S ₂₈ →S ₂₇ →S ₃₀ →S ₂₉ ...
The ON state changes as shown below. Also, the frequency divider 14
The 50Hz pulse signal formed by the L/R changeover switches S ₁ to S ₈ and S ₁₅ to S ₂₀ is connected to the L side terminal at “H” and to the R side terminal at “L”. Connect counters 10, 11 and fluorescent display panels _6L , _6R.
Switch every 10msec.

Function generator 15 receives 200Hz and 400Hz from frequency divider 14
The pulse signal of switches S ₂₇ to _{S 30} is input.
With respect to the ON and OFF timings, etc., the phase relationship shown in Figure 4 is "H" for a period of T ₁ (= 3.75 msec), and T ₂ (=
It is controlled by a NAND circuit 27 which outputs an "L" pulse for a period of 1.25 msec). In FIG. 5a showing an embodiment of the function generator 15, the emitter of the transistor Tr ₁ having its base connected to the output of the NAND circuit 27 is connected to the power supply E and the ground G to constitute a constant voltage source _Vcc . The collector is grounded through resistors R ₂ and R ₃ at the connection point between the resistor R ₁ and the Zener diode Z _D connected in series therebetween.
A capacitor C ₁ is connected between the connection point a of the collector and the resistor R ₂ and the constant voltage source V _cc , and the connection point a
is the comparator 1 via the buffer amplifier 50 with a gain of 1.
The comparator is connected to the other human input terminal of 6, and has a reference voltage Vs applied to one input terminal from the connection point of resistors R ₄ and R ₅ connected in series between the constant voltage source V _cc and ground. It is connected to the other input terminal of 51. The comparator 51 compares the reference voltage Vs and the voltage at the connection point a, and when the voltage at the connection point a becomes lower than the reference voltage Vs, it outputs "H" to the transistor Tr _2.
Apply it to the base of and turn it ON. The collector and emitter of transistor Tr ₂ are connected between the connection point of resistors R ₂ and R ₃ and ground. In this configuration, when the output of the NAND circuit 27 is "L", the transistor Tr ₁ is turned on and the voltage at the connection point a is equal to the constant voltage source voltage Vcc;
When the output becomes "H", the transistor Tr ₁ is cut off, the capacitor C ₁ starts charging via the resistors R ₂ and R ₃ , and the level at the connection point a gradually decreases. When the voltage at the connection point a becomes lower than the reference voltage Vs, the transistor Tr ₂ is turned on and charging is performed only through the resistor R ₂ , so that the level at the connection point a decreases rapidly. Therefore function generator 1
5 outputs a signal having a waveform shown in FIG. 5b for the time T ₁ of the output "H" and the time T ₂ of the output "L" of the NAND circuit 27. In addition, in the function generator 15, a transistor is connected between the connection point a and the constant voltage source Vcc.
The emitter and collector of Tr ₃ and the capacitor C ₂ are connected in series, and the transistor Tr ₃ is normally in a cut-off state, and when an “L” signal is applied to the control terminal 52, it is turned on and the capacitor C ₁ Connect capacitor C ₂ in parallel to
as shown by the dashed line.

The output of the comparator 16 that compares the output of the function generator 15 and the detection output is input to the other input terminal of a NAND circuit 28 to which a 100 Hz pulse signal is applied from the frequency divider 14 to one input terminal. Ru.
The output of this NAND circuit 28 is applied to one input terminal of the NAND circuit 30, which receives the 200Hz, 400Hz pulse signals from the frequency divider 14 and the 800Hz pulse signals inverted by the inverter 29.
It is input to the other input terminal of 1.

The NAND circuit 31 outputs "H" and connects each grid terminal 9 _L of each display tube 8 _L and 8 _R of L and R channels.
Connect between 9 _R and the L/R changeover switches S ₁₅ to S ₂₀ , and connect the switches S ₉ to S 20 so that they open when the output is “L”.
Control _S14 and _S21 to _S26 .

Now, assuming that while the switches S ₂₇ to S ₃₀ are ON, the detection output Vx, which is lower than the constant voltage level Vcc, is input to the comparator 16, the comparator 16 is connected to a NAND circuit 27, etc. It outputs "H" during time Tx with the phase relationship shown in FIG. 4 with respect to the output waveform, etc., and the NAND circuits 28 and 31 take the output state shown in FIG. That is, NAND circuit 3
1 is the time T ₃ (=0.625 msec) corresponding to the pulse width of the 800 Hz pulse signal from when the output of the comparator 16 changes from "H" to "L" when the switch S ₃₀ or S ₂₈ is ON. "H" is output only during the elapse of , and when the switch _S29 or _S27 is ON, the output is "H" during the elapse of the time Tx+ _T3 from when the output of the comparator 16 changes from "L" to "H". Outputs “H”. Therefore, when the switch S ₃₀ or S ₂₈ is ON, it takes time T ₃ after the "H" output of the comparator 16 disappears.
During the period of time, the grid terminals 9 of display tubes 8 _L and 8 _R
Since the drive voltage is applied to the fluorescent display panels _6L and _9R , the clock pulse applied to the clock terminal _CL of the first counter 10 is applied to the fluorescent display panels 6L _{and 6R} while the comparator 16 outputs "H". One segment determined by the output terminals Q ₁ to _{Q 14} of the counters 10 and 11 based on the final count is lit to display the peak level of the detected output. On the other hand, when the switch S ₂₉ or S ₂₇ is ON, the drive voltage is applied to the grid terminals 9 _L and 9 _R for the time period Tx + T ₃ from when the comparator 16 outputs "H". While the comparator 16 outputs "H", the counter 1 is in the process of counting the clock pulses applied to the clock terminal C _L of the counter 10.
In response to the output states of the output terminals Q ₁ to Q ₁₄ of 0 and 11, the segments of the fluorescent display panels 6R _L and 6 _R are sequentially blinked from the lowest level side. The reset pulse applied to the reset terminals _CR of the first and second counters 10 and 11 is formed by the frequency divider 14.
200Hz, 400Hz, 1.6kHz, 3.2kHz, 6.4kHz, 12.8k
Hz and 800 Hz pulse signals inverted by the inverter 29 are formed by AND outputs operated through diodes D ₁ to D ₇ . This reset button is set for each of the switches _S27 to _S30 with reference to FIG.
One pulse is formed when ON, has the same pulse width as the 12.8 kHz pulse signal, and its falling edge coincides with the falling edge of the NAND circuit 31.

In the device of the present invention having the above configuration, when the manual operation switch _S31 is in the state shown in FIG.
The peak detection output of the L (or R) channel corresponds to when the switch S ₂₇ (or S ₂₉ ) is ON, and the peak hold detection output of the L (or R) channel corresponds to when the switch S ₂₈ (or S ₃₀ ) is ON. Therefore, the peak display is performed by sequentially flashing segments starting from the lowest level, and the peak hold display is performed by lighting one segment in response to the peak level that is held for several seconds. Also, when switch S ₃₁ is in the other state,
The VU detection output of the L (or R) channel is turned on when switch S ₂₇ (or S ₂₉ ) is ON, and the peak detection output of the L (or R) channel is turned on when switch S ₂₈ is turned on.
(or S ₃₀ ) corresponds to each ON time, so
The VU display is performed by sequentially flashing segments starting from the lowest level side, and the peak display is performed by lighting one segment that responds to the peak level that is not held. This peak display by lighting one segment follows the peak level of the signal more sensitively than the peak hold display, and the segment that is lit changes more sensitively.

Therefore, L/R changeover switches S ₁ to _{S 8} and
S ₁₅ to _{S 16} are switched every 10 msec, and switches S ₂₇ to S 16 are switched every 10 msec, and within 20 msec when each channel is displayed.
Since S ₃₀ is switched at high speed sequentially every 5 msec,
Furthermore, since segment blinking scanning is performed at extremely high speed, the fluorescent display panels 6 _L and 6 _R of the L and R channels operate simultaneously, and each display panel 6
In _L and 6 _R , peak display (or VU display) and peak hold display (or peak display) are observed to be displayed at the same time, and in the former peak display (or VU display), segments are blinking. appear to be lit at the same time.

The brightness of the segments in the fluorescent display tube can be adjusted by the lighting time of the segments, but in the above embodiment, the 12.8 kHz and/or 6.4 kHz pulse signals are ANDed to form the reset pulse. By excluding the rising edge of the reset pulse, the NAND circuit 31 becomes “H”.
Since the reset time of the first and second counters 10 and 11 can be controlled close to the rise of the output, the brightness of the segment in peak hold display, etc. can be adjusted.

In addition, in the case where the output waveform of the function generator is formed by the C and R time constant circuits as in the above embodiment, the waveform is flat on the low level side of the waveform, and the low level of the signal under measurement is The generation time width of the clock pulse relative to the detection output becomes unstable and the level indication becomes inaccurate, but in this embodiment, the accuracy can be achieved by making the slope of the output waveform on the low level side of the function generator 15 steep. You can get detailed level instructions. Furthermore, when an "L" signal is applied to the control terminal 52 of the function generator 15, the output waveform becomes flat as shown by the broken line in FIG.
Illuminated by Vcc. This increases the reading speed of a narrow range of levels since it is displayed in many segments.

Therefore, if the configuration is such that an "L" signal is applied to the control terminal 52 as necessary by operating a switch, it becomes possible to accurately calibrate the reference signal, for example.

According to the device of the above embodiment, the level of an audio signal with a wide dynamic range can be displayed on a fluorescent display panel with a large number of segments by simply combining two small-capacity counters, making it easy to observe the level indication. Not only can it be used for audio equipment, but also L,
The fluorescent display tubes of both R channels can be driven by the same drive circuit, and two different displays can be viewed simultaneously on one fluorescent display panel.

Furthermore, according to the device of the present invention, among the segments of the fluorescent display tube that flash sequentially, the lighting time of the segment corresponding to the maximum level is longer than the lighting time of the other segments. is displayed brighter than other segments,
The display range of segments arranged in a line becomes clear, and erroneous confirmation can be prevented even when the display level changes quickly.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a conventional device, FIG. 2 is a circuit diagram of an embodiment in which the device of the present invention is applied to a signal level display device for audio equipment, and FIG. 3 is an explanation of the operation of the counter in FIG. 2. Time chart for the 4th
Figures a to d are time charts for explaining the operation of the embodiment in Figure 2, Figure 5a is a circuit diagram of an embodiment of the function generator in Figure 2, and Figure 5b is a diagram for explaining its operation. are shown respectively. 6 _L , 6 _R ... Fluorescent display panel, 7 ₁ to 7 ₈ ... Segment, 8 _L , 8 _R ... Fluorescent display tube, 9 _L , 9 _R ...
...Grid terminal, 10...First counter, 11
... second counter, 15 ... function generator, 16
...Comparator, 12, 27, 28, 30, 31...
NAND circuit, 25, 26, 29...inverter,
21-24...AND circuit, _S9 - _S14 , _S21 - _S26
... Grid control switch, S ₁ ~ S ₈ , S ₁₅ ~ _{S 20}
...L/R selector switch, _Q1 to _Q14 ...Output terminal.

Claims (1)

[Scope of Claims] 1. Pulse generating means that generates a number of clock pulses corresponding to the level of a signal; Counter means that includes a plurality of output terminals that output signals that are sequentially switched according to the number of counts of the clock pulses; A required number of segments arranged in a line from the low level side to the high level side are connected to corresponding output terminals of the counter means, and driving is started by the output signal in response to the start of counting of the clock pulses. , and a fluorescent display tube in which the segments are sequentially driven in a direction from the low level side to the high level side; grid control means for applying a first driving voltage and for applying a second driving voltage only for a required period of time following the end of the count; When the second drive voltage is applied, the segments on the low level side to the segment corresponding to the maximum level of the signal are sequentially blinked, and when the second driving voltage is applied, only the segment corresponding to the maximum level of the signal is the desired one. A fluorescent display device characterized in that it is turned on after counting is completed based on the time of .