JPS638481B2 - - Google Patents

Description

[Detailed description of the invention]

(a) Field of the Invention The present invention relates to a program timer that controls driving or stopping a plurality of loads at preset times. (B) Background of the Invention In general, when a program timer is used to control driving and stopping of multiple loads, multiple channels (multiple loads) may be controlled to be driven at the same time. In this case, the output timing from the program timer to the load is determined by sending multiple channel outputs at the same time, so if the load to be driven and controlled is a heavy load, the contracted power may be exceeded, or the voltage on the line may drop momentarily. There is a problem in that it has a negative effect on other equipment. In order to solve this problem, it is desirable to slightly shift the output sending timing for each channel. On the other hand, in the case of a light load, there is no need to take the trouble to shift the output sending timing for each channel as described above. Therefore, even when driving and controlling a plurality of loads at the same time, it would be convenient if it were possible to select simultaneous output or staggered output for each channel depending on the load situation. (c) Purpose of the Invention The purpose of the present invention is to provide a program timer that allows the user to easily select the output mode to the loads to be simultaneously driven according to the load status (light load, heavy load). be. (d) Structure and Effects of the Invention In order to achieve the above object, the program timer of the present invention has a plurality of setting step storage areas, and each setting step storage area stores data indicating the load number and drive/stop to be controlled. and means for storing set time information such as day of the week, hour and minute, means for generating a time signal, and means for receiving the time signal from the time signal generating means and counting current time information such as day of the week, hour and minute; Comparing means for comparing each of the set time information and the current time information to confirm whether the two pieces of information match; means for outputting a signal for controlling a corresponding load based on a matching output of the comparing means; When a plurality of loads are set to be driven at the same time, a switching means is provided for switching between outputting the plurality of drive signals from the output means to each load at the same time or sequentially outputting them with a predetermined timing shift. It is configured. According to the program timer of the present invention, when driving and controlling multiple loads at the same time, it is possible to drive each load at the same time or to drive the loads by sequentially shifting the timing for each load channel depending on the load condition. The selection can be easily made by operating the switching means. (E) Description of Embodiments The present invention will be described in more detail below with reference to embodiments shown in the drawings. FIG. 1 is a block diagram of a program timer showing one embodiment of the present invention. In the same figure, 1 is 4
It is a 1-bit C-MOS microprocessor (hereinafter referred to as CPU). This CPU 1 executes a timer function based on a processing flow described later.
A clock pulse generation circuit 2 is connected to the CPU 1 to provide drive pulses and time pulses, and an interrupt signal generation circuit 3 is also connected to the CPU 1 to interrupt the CPU 1 at a predetermined period (for example, 2.5 mS). Keyboard 4 is connected to CPU 1, and can store various data in addition to numbers, days of the week, and channel numbers.
It is input to the CPU 1, and program data is written into the memory (RAM) built into the CPU 1, or the data is erased and corrected. The output of CPU1 is time display section 5, day of the week display section 6
and is added to and displayed on the setting output monitor 7. The time display section 5 is composed of a four-digit numerical display, and displays the current time, the channel number at the time of program setting, on/off data, and program time. The day of the week display section 6 is composed of seven light emitting elements corresponding to each day of the week, and displays the current day of the week as well as the day of the week when the program is set. The setting output monitor 7 is composed of light emitting elements for four channels, and displays the channel number set at the time of program setting. The weekly program switch 8 consists of seven switches corresponding to each day of the week, and is connected to the CPU 1. When the weekly program switch 8 is in the "automatic" state, the channel load is controlled according to the program for that day. but,
When in the "off" state, load control of all channels is disabled. An automatic/manual switching circuit 9 is provided between the CPU 1, the output monitor 10, and the relay section 11. Automatic/
The manual switching circuit 9 can be turned on or off for each channel.
It consists of a changeover switch that can switch between "auto" and when each channel is set to "auto", the output of CPU 1 is transmitted to output monitor 10 and relay section 11, and when it is "on", the output of CPU 1 is transmitted to The relay section 11 is forcibly driven regardless of the output. The relay unit 11 operates (drives) or stops the equipment connected to this program timer.
The output monitor 10 is made up of light emitting elements that display the operating status of the load equipment for each channel. Reference numeral 12 denotes a mode selection switch circuit for output transmission, and when this circuit is in an on state, a plurality of outputs are simultaneously transmitted at the same time (this case is referred to as simultaneous activation mode). Conversely, when it is in the off state, multiple outputs to be output at the same time are sent out sequentially every second (this case is referred to as sequential startup mode).In other words, the output transmission mode selection switch circuit 12 selects simultaneous startup mode. The startup mode is selected and set sequentially. Note that 13 is a constant voltage circuit that stabilizes the voltage E from the main power supply and supplies power to the CPU 1, and 14
is a battery that backs up the main power and allows the CPU 1 to perform processing operations even when the main power is turned off. 2 and 3 show front and back views of the external case of the program timer shown in FIG. 1, and the same numbers as those shown in FIG. 1 indicate corresponding parts, respectively. 15 is an output terminal. The CPU1 of the program counter in the above embodiment is
It has built-in RAM as a storage means, and this RAM
As shown in FIG. 4, there is a storage area M1 for stack and working, registers N1 and N2 for calculations
and is allocated to the data store area M2 of the setting step. Here, 25 setting steps can be set in the setting step data store area M2, and the storage area for each setting step includes days of the week,
Time and minute data, channel number data, and data indicating output on/off status are stored.
The data storage arrangement for the 1 setting step is shown in Fig. 5, and the 4 bits b1 to b at address n
4 contains 1 minute data, 3 bits of address n+1 b
1 to b3 contain 10 minute data, 4 bits at address n+2 contain 1 o'clock data, and b1 and b2 at address n+3.
The 2 bits of b3 and b4 contain the data at the 10 o'clock position, and the channel number is stored in the 2 bits of b3 and b4.
Day of the week data is set and stored in three bits 1 to b3, and data indicating output on/off is stored in bit b4 at the same address. Data settings for each setting step are performed using the keyboard 4. The CPU 1 also has an output register that stores the output status of each channel, and has 4-bit memory cells B1 to B4 as shown in Figure 6, and each bit cell B1 to B4 corresponds to the output register. The current output status of each channel is stored. Next, the operation of the embodiment program timer configured as described above will be explained with reference to the processing flows shown in FIGS. 7 and 8. FIG. 7 is a processing flow diagram of the interrupt routine. An interrupt signal is applied to the CPU 1 from the interrupt signal generation circuit 3 every 2.5 mS, and each time it is determined whether or not there is a power outage (step ST1), if there is no power outage, no display processing is performed (ST2), and the keyboard is searched and pressed. If there is a key, it is read (ST3) and the time is counted every 2.5 mS (ST4). In case of power outage
The determination in ST1 is YES, and in ST5 it is determined whether the power outage flag (not shown) is 1 or not. If it is 1, it is left as is; if it is not 1, it is set to 1 (ST6), and then time is counted (ST4). After this time count, the routine returns to the normal processing routine shown in FIG. Now, the setting step data shown in the table below is set in the RAM in CPU1, the current time is 12:34 on Monday, and the output status at that time is 1 channel...off, 2 channel...on ,3
The operation of the normal processing routine will be explained by taking as an example the case where channels are off and four channels are on (output register contents 1010).

[Table] Following the initial settings of ST11 after starting operation,
It is determined whether 1 minute has passed (ST12), but 1
If minutes have elapsed, the contents of the output register, that is, the current output status 1010, is stored at address N1 (ST
13). Then, the setting step address is set to 1 (ST14), and then it is determined whether all 25 setting step data have been searched (ST15). Initially judged
Since NO, it is next determined whether the time and day of the week data in setting step 1 match the current time (ST1
6). In the above example, since they match, the channel is then determined based on the channel number data stored in setting step 1. In the case of setting step 1, the channel number data is 00, which means channel number 1.
This channel No. 1 is stored as data 0001 in the accumulator Acc in the CPU 1 (ST17).
Next, in ST18, set address n+4 of setting step 1.
Determine whether the set output is on or off by referring to the b4 bit. In this case, it is 1 (on), so it moves to ST19, and the data 1010 at address N1 and the accumulator Acc are
Take the logical sum of data 0001 and the result is data 1011
is stored at address N1 (ST22). Then add +1 to the setting step address to set it to 2 (ST2
3) Jump to ST15. This time, regarding setting step 2, the operations from ST15 onward will proceed. In the above example, ST15
Have you searched all the data? Judgment NO
The process moves to ST16 and it is determined whether the time and day of the week match, but if this is YES, the process moves to ST17 and sets step 2.
The channel No. 2 is determined from the channel No. data 01, and the data 0010 is set in the accumulator Acc. Next, it is determined whether the data is on (ST1
8) Bit b4 at address n'+4 in setting step 2
is 0 (off) and the judgment is NO, which is different from the case of setting step 1, and the accumulator
The content 0010 of Acc is inverted to obtain 1101, which is reset to the accumulator Acc (ST20). next
The data 1011 at the N1 address and the data 1101 at the accumulator Acc are ANDed (ST21), and the resulting data 1001 is restored to the N1 address (ST22).
Then, add 1 to the set step address to make it 3 (ST23), and jump to ST15. Next, regarding setting step 3, the operations from ST15 onward proceed. Also for this setting step 3
Did the judgment NO in ST15 match the time and day of the week in ST16? The judgment is YES and the process moves to ST17. ST1
In step 7, channel No. 3 is determined from the channel number data 10 of setting step 3, and the data 0100 is set in the accumulator Acc. Next, setup step 3
Is the data on from bit b41 at address n'+4? A YES determination is made (ST18), and as in the case of setting step 1, the data at address N1 and the accumulator Acc are logically summed (ST19). In this case, since both data are 1001 and 0100, the resulting data is 1101 and this data is stored at address N1 (ST2
2). Then add +1 to the setting step address to make it 4.
(ST23) and jumps to ST15. Thereafter, the operations from ST15 onwards are repeated until all searches of the setting step data are completed, but in the example shown here, the setting time and day of the week match the current time and day of the week only for the three steps in the table above. . Therefore, did the time and day of the week match in ST16? The determination is NO, and in ST23, only the increment of the step address is continued. When all data searches are completed, ST15
Jumps from ST24. In ST24, the data at address N1 is compared with the output register to determine whether the current output matches the stored content at address N1. If they match, it means that the output has already been sent, so ST25 and ST
26 performs timer check and timer processing.
Move to ST27. In the above example, the store data at address N1 is 1101 and the output register data is 1010, so there is a mismatch.
Here, the transmission output mode switching selection circuit 12 is checked to determine whether it is the simultaneous start mode or the sequential start mode (ST29).If the simultaneous start mode is set, data 1101 at address N1 is transferred to the accumulator. The data 1101 stored in the accumulator Acc is loaded into Acc (ST30), and the data 1101 stored in the accumulator Acc is outputted via the output register. If the sequential startup mode is set in ST29, it is determined whether a one-second timer (built in the CPU 1) is activated (ST32).
If the 1-second timer is not activated, first load the current output state, that is, the contents of the output register 1010, into the accumulator Acc, then perform the logical product of this loaded data and the data at address N1,
The resulting value is stored at address N2 (ST33).
In the above example, 1000 is obtained as the AND of data 1010 and data 1101 at address N1. This data is
This data indicates channels whose output remains on. Next, an exclusive OR operation is performed on the N1 address and the N2 address, and the result is stored in the accumulator Acc (ST34). In the above example, it is the exclusive OR of 1101 and 1000, and 0101 is obtained as the result data.
This data indicates the channel whose output is turned on. In other words, it shows that channels 1 and 3 are turned on. Following ST34, it is determined whether the ²⁰ bit (first bit) of the accumulator Acc is 1 (ST3
5) If it is 1, move to ST36 and read the contents of address N2 +
Restore 0001 to address N2. In the above example, ²⁰ bits are 1 and 1000 is stored at address N2, so 1000+0001=1001 is newly stored at address N2. Next, start the 1 second timer (ST3
7) Next, the data 1001 at address N2 is transferred to the accumulator Acc (ST38), and the data 1001 of the accumulator Acc is outputted via the output register (ST31). As a result, channel 1 is first turned on. Channel 2 changes from on to off, channel 3 remains off, and channel 4 remains on. After that, is the ST27 key flag = 1? Return from ST12 to ST24 via NO. N1 in ST24
Since the address data 1101 and the output register contents 1001 do not match, the judgment is NO and the process moves to ST29, but since it is a sequential startup mode, the judgment at this step is also
If NO, the process moves to ST32 and it is determined whether the 1-second timer is activated. Since this judgment is YES, it is next checked whether one second has elapsed (ST25). If one second has not elapsed, the process jumps to ST27, and the same process is repeated until one second has elapsed. If you get a judgment that 1 second has passed in ST25, 1
At the same time as stopping the second timer, its contents are cleared (ST26). Operation after ST26 is ST27 judgment NO → ST12
Judgment NO → ST24 judgment NO → ST29 judgment NO →
Proceed with ST32. Is the 1 second timer on ST32 running? As mentioned above, the 1 second timer is stopped in ST26, so this judgment is NO.
Then move to ST33. In this step, data 1001 in the output register and data 1101 in address N1 are ANDed, and the result is data 1001 in the accumulator.
Stored at address N2 from Acc. Next in ST34
The data 1101 at the N1 address and the data 1001 at the N2 address are exclusive-ORed and the resulting data 0100 is stored in the accumulator Acc. Data 0100 stored in accumulator Acc
is ²⁰ bits, ²¹ bits are 0, and ²² bits are 1, so is ST35's ²⁰ bits = 1? The judgment is NO,
ST39 decision is NO, ST41 decision is YES,
The process moves to ST42. In ST42, the contents of address N2, 1001 and 0100, are added, and the resultant value is 1101 again.
Stored at address N2. Next, move on to ST37 1
Start the second timer, then load the data at address N2 into the accumulator Acc in ST38, and then in ST31
The data 1101 of the accumulator Acc is transferred to the output register and output processing is performed. This allows channel 1
One second later, channel 3 is also turned on. (Channel 2 remains off, channel 4 remains on) After output processing in ST31, judgment in ST27
NO → After the judgment NO in ST12, the process returns to ST24, but here the current output register contents 1101 and
Since the data at address N1 match, the judgment in this step is YES, and when 1 second has passed, the 1 second timer is stopped and its contents are cleared (ST25,
ST26), then proceed to ST27. As described above, when turning on (driving) outputs of multiple load channels at the same time, by setting in advance whether to start simultaneously or sequentially, it is possible to turn on multiple outputs at the same time, or to turn on a few outputs at the same time. They can be turned on sequentially by shifting the timing time (for example, 1 second). Whether to start simultaneously or sequentially can be determined depending on the weight (small or large) of the load. Note that the 1 second timer in the above embodiment counts the number of interrupts every 2.5 mS, and when it counts 400 times, it means that exactly 1 second has passed after activation, so it can be easily implemented. Repeat this count 800 times, 1200
By changing the number of times, a 2-second timer and a 3-second timer can be obtained instead of a 1-second timer, so the shift timing width in sequential activation can be arbitrarily changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a program timer showing an embodiment of the present invention, FIG. 2 is a front view of the external case of the program timer shown in FIG. 1, FIG. 3 is a back view of the same, and FIG. Figure 5 is a diagram showing the storage area allocation of the RAM built into the CPU that constitutes the program timer shown in Figure 4. Figure 5 is a diagram showing the storage area allocated to one setting step of the RAM shown in Figure 4. Figure 6 is the output Diagram showing the bit arrangement of the register, No. 7
This figure is a processing flow diagram of the program timer interrupt routine shown in FIG. 1, and FIG. 8 (FIG. 8-, FIG. 8-) is a processing flow diagram of the same normal routine. 1: CPU, 2: Clock pulse generation circuit,
3: Interrupt generation circuit, 4: Keyboard, 5: Time display section, 6: Day of the week display section, 7: Setting output monitor,
8: Weekly program switch, 9: Automatic/manual switching circuit, 10: Output monitor, 11: Relay section, 1
2: Mode selection switch circuit, 13: Constant voltage circuit, 14: Battery, 15: Output terminal.

Claims (1)

[Scope of Claims] 1. A program timer for driving or stopping a plurality of loads at preset times, having a plurality of setting step storage areas, each setting step storage area storing a load number to be controlled. , means for storing data indicating drive/stop and setting time information such as day of the week, hour and minute; means for generating a time signal; and means for receiving the time signal from the time signal generating means and determining the current time such as day of the week, hour and minute. a means of counting information;
Comparing means for comparing each of the set time information and the current time information to confirm whether the two pieces of information match; means for outputting a signal for controlling a corresponding load based on a matching output of the comparing means; When a plurality of loads are set to be driven at the same time, it is possible to switch between outputting the plurality of drive signals from the output means to each load at the same time or sequentially outputting the outputs shifted by a predetermined timing. A program timer comprising: means.