JPS638501B2 - - Google Patents

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to an input/output control device in an information processing system, and the present invention relates to an input/output control device in an information processing system. This is related to control that is identified on the device side.

(2) Prior art and problems When transferring data between a transfer device (channel) and an input/output control device (including a communication control device and a communication control processing device), the transfer device The address of the device to which the data is to be transferred is placed on the data bus, and the tag line indicates that the address information is on the data bus. At this time, the input/output control device checks whether the address information on the data bus is the address of the input/output device connected to the self-control device, and if it is, the input/output control device uses the tag line to It sends a signal to the transfer device and performs control such as transferring the data on the data bus that is subsequently sent to the relevant input/output device.

There are two types of data transfer: information is transferred in burst mode and information is transferred in multiplex mode. In the latter case, the transfer device has multiple subchannels corresponding to each input/output device, and these It corresponds fixedly to each input/output device and line connected to the output control device. In this case, the address determination in the input/output control device described above is performed depending on whether or not the address is within a predetermined value range.

FIG. ₁ is a block diagram showing an example of an address determination circuit in a conventional input/output control device.
1 _B is a bus out register, 2 _A , 2 _B are address setting boards, 3 _H , 3 _L are address range setting boards, 4 _A ,
_4B represents a comparison circuit, _5A and _5B are switches, 6 is an address range verification circuit, and 7 is an OR gate. The suffix A in each number indicates that it corresponds to the A-side interface, and B indicates that it corresponds to the B-side interface. Further, the address range setting plate _3H indicates that it is for setting a high address, and the _{plate 3L} indicates that it is for setting a low address.

In FIG. 1, when the transfer device sends address information onto the data bus for device selection, the input/output control device puts the address information on the bus out register _1A or _1B .
The value is then compared with the preset value on the address setting board 2 _A or 2 _B , or checked to see if it is within the range of the address range setting board 3 _H or 3 _L. , if any of the above applies, NAO (NSC address match signal) or EAO (ESC address within range signal) is output, indicating that the address information belongs to the input/output device under the control of the own input/output control device. The control unit is notified that this is the case.

In such conventional input/output control devices, a method such as shorting terminals on a setting board is used as a means of setting address values in advance, so it is easy to add input/output devices or change connections. There was a problem in that it was troublesome to change the address setting values. Additionally, when supporting a transfer device with multiple subchannels, due to hardware constraints, the A-side interface and the B-side interface must have the same address range and be continuous. In addition, there is a problem in that the upper limit address and the lower limit address must each be a certain boundary value (for example, 16 addresses, 4 addresses, etc.).

(3) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention provides input/output control that is easy to set up and has fewer restrictions on address setting even when supporting a transfer device having multiple subchannels. The purpose is to provide an address determination method for devices.

(4) Structure of the invention According to the present invention, this object is achieved in an input/output control device as described in the claims.
A storage section for address definition and a means for generating an access address to the storage section based on an initial selection address from a host device are provided, and each subchannel is stored in advance in the storage section in correspondence with the addresses of all subchannels. For each subchannel, whether or not the address of the subchannel is defined or whether it is within the defined address range is written for each interface with the opposing host device, and the initial request from the host device is written. This is achieved by an address determination method characterized in that, at the time of selection, the storage unit is referred to based on the address generated by the means to determine whether or not there is a selection from a host device.

(5) Embodiments of the Invention FIG. 2 is a block diagram showing an example of the configuration of a communication control processing device, in which 8 is a central control unit, 9 is a main storage device, and 1 is a block diagram showing a configuration example of a communication control processing device.
0 is the service processor (SVP), 11 ₁ to 11 _o
is a channel adapter, 12 ₁ to 12 _o are line scanning mechanisms, 13 is a common bus, and 14 is an SVP link. In the communication control processing device having such a configuration, the channel adapters 11 ₁ to 11 _o control the interface with the transfer device. When the present invention is applied to a communication control processing device, it is implemented within the channel adapter.

The communication control processing device shown in FIG. 2 is a control device with a built-in program, and can perform different types of control depending on the type of control program. In other words, when performing control using native mode, control information and data for multiple lines are transferred to and from the host computer using one subchannel (NSC address), while when performing control using the emulation program. If this is the case, multiple lines and multiple subchannels (ESC addresses) are made to correspond one-to-one, and transfer is performed in multiplex mode. Communication between the host computer and the communication control processing device proceeds by executing I/O commands issued by the transfer device. The transfer device performs an initial selection sequence for the input/output control device to be connected,
Select the desired I/O controller and issue the command. The communication control processing device checks the address transferred on the bus out in response to the initial selection from the transfer device, and determines whether or not it is the initial selection addressed to the device itself.

FIG. 3 is a block diagram showing an address determination circuit according to an embodiment of the present invention, which is a part of the circuit of a channel adapter of a communication control processing device, and 15 is a block diagram showing an address determination circuit according to an embodiment of the present invention.
SVP link control circuit, 16 local storage control register, 17 local storage data register, 18 local storage address register, 19 local storage address creation circuit, 20 local storage, 2
1 represents an address determination circuit, 22 _A and 22 _B represent bus out registers, and 23 _A and 23 _B represent switches.

Figure 4 shows the address definition information on the local storage, and 24 is on the A interface side.
NSC address definition bit, 25 is the NSC address definition bit on the B interface side, 26 is the ESC address range definition bit on the A interface side,
27 is an ESC address range definition bit on the B interface side.

FIG. 5 is a diagram showing an example of a local storage bit pattern, where the hexadecimal digits on the left side indicate the memory address, and the hexadecimal digits on the right side indicate the address of the corresponding subchannel.

This embodiment concerns a communication control processing device in which an NSC address and a plurality of ESC addresses are defined. This will be explained below with reference to FIGS. 2 to 5.

During IPL of the communication control processing unit, the service processor 10 uses the NSC address and NSC address related to interface A/B from the channel adapter-related installation information (stored on the floppy disk).
Information regarding the ESC address is read, a corresponding local storage address, local storage write data, and local storage control information are created and transferred to the selected channel adapter via the service processor 10.

On the channel adapter side, the SVP link control circuit receives this, and through scan-in operation, the above information is transferred to the local storage address register 18 and local storage data register 1, respectively.
7, and local storage control register 16. When a write access instruction is set in the local storage control register 16, the channel adapter writes address definition information to the corresponding address position.
The address definition information consists of 4 bits as shown in FIG. 4, and the NSC address and ESC address range are defined for each A/B interface.

The service processor 10 assigns "1" data to defined addresses and "0" data to undefined addresses based on the installation information for multiple addresses (256 addresses in this case) that are the address range of the channel. Create and transfer light data.

Figure 5 shows an example of a bit pattern written to local storage, but in this example, the local storage is not provided exclusively for address definition, but the empty area of the data buffer used when transferring data with the transfer device is used. It has been realized. Therefore, the address definition area is from address X “100” to
Address “3FF” is used. (X“000”~X
"Address 0FF is used as a data buffer and work area." The service processor only needs to be aware of this first address (address Then, the channel adapter sends the initial selection address (X “xx”) on the bus out to the local storage address generation circuit 19, adds a bit to the upper digit, and sets the corresponding address position in the local storage 20 as X “1xx”. The address determination circuit 21 determines the NSC address/ESC address range, interface A/B, defined address/undefined address, based on the bit position of "1" in the information read above. Detected as a defined address
The NSC/ADR/OK and ESC/ADR/OK signals are transmitted to the initial selection sequence control circuit to continue control.

(6) Effects of the Invention As explained in detail above, according to the method of the present invention, the NSC address and
It has the advantage of being easy to set the ESC address range, especially when setting the ESC address range.
Since there are no hardware restrictions, A.
It is effective because the degree of freedom in address setting increases, as the addresses can be different between the side interface and the B-side interface, and there is no need for the address values to be continuous or to adhere to a certain boundary value. is large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an address judgment circuit in a conventional input/output control device, FIG. 2 is a block diagram showing an example of the configuration of a communication control processing device, and FIG. 3 is a block diagram showing an example of an address judgment circuit in a conventional input/output control device. FIG. 4 is a block diagram showing the circuit, FIG. 4 is a diagram showing address definition information of local storage, and FIG. 5 is a diagram showing an example of a bit pattern of local storage. 1 _A , 1 _B , 22 _A , 22 _B ... Bus out register, 2 _A , 2 _B ... Address setting board, 3 _H , 3 _L ...
Address range setting board, 4 _A , 4 _B ... Comparison circuit, 5
_A , 5 _B , 23 _A , 23 _B ... Switch, 6... Address range verification circuit, 7... OR gate, 8... Central control unit, 9... Main memory, 10... Service processor, 11 ₁ ~11 _o ... Channel adapter, 12 ₁ ~12 _o ... Line scanning mechanism, 13... Common bus, 14... SVP link, 15... SVP
Link control circuit, 16...Local storage control register, 17...Local storage data register, 18...Local storage address register, 19...Local storage address creation circuit, 20...Local storage, 21...Address determination circuit, 24...NSC address definition bit on the A interface side, 25
...NSC address definition bit on the B interface side, 26...ESC address range definition bit on the A interface side, 27...ESC address range definition bit on the B interface side.

Claims (1)

[Claims] 1. In an input/output control device, a storage section for address definition and means for generating an address for accessing the storage section based on an initial selection address from a host device are provided, and all subchannels are stored in the storage section in advance. For each subchannel, write whether or not the address of the subchannel is defined or whether it is within the defined address range for each interface with the opposing host device. An address determination method characterized in that, at the time of initial selection from a higher-level device, a storage unit is referred to based on the address generated by the means to determine whether or not there is selection from a higher-level device.