JPS641057B2 - - Google Patents
Info
- Publication number
- JPS641057B2 JPS641057B2 JP57168402A JP16840282A JPS641057B2 JP S641057 B2 JPS641057 B2 JP S641057B2 JP 57168402 A JP57168402 A JP 57168402A JP 16840282 A JP16840282 A JP 16840282A JP S641057 B2 JPS641057 B2 JP S641057B2
- Authority
- JP
- Japan
- Prior art keywords
- gold
- base metal
- wiring pattern
- wiring board
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
- H05K3/4676—Single layer compositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、セラミツク配線基板の製造方法に関
し、特に卑金属導体パターンの所要部に金電極を
形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a ceramic wiring board, and more particularly to a method for forming gold electrodes at desired portions of a base metal conductor pattern.
セラミツク配線基板には、接続導体パターンお
よびボンデイングやコンタクトのための電極部な
どすべての導体を金で形成したものがある。この
ような配線基板は、ボンデイングやコンタクトが
容易でかつ信頼性も高いが高価である。一方、す
べての導体を銅ペースト等の卑金属を用いて窒素
雰囲気中で焼成して形成した配線基板は、ボンデ
イングやコンタクトが困難である。このような配
線基板には、一般にICリードや端子は半田付け
して接続するのが接続部の信頼性が低いという欠
点があつた。
Some ceramic wiring boards have all conductors, including connection conductor patterns and electrode parts for bonding and contacts, made of gold. Such a wiring board is easy to bond and contact, and has high reliability, but is expensive. On the other hand, a wiring board formed by firing all conductors in a nitrogen atmosphere using a base metal such as copper paste is difficult to bond and contact. Such wiring boards have a drawback in that the reliability of the connections is low because IC leads and terminals are generally connected by soldering.
このため、出願人は、先にセラミツク基板上に
金等の貴金属導体ペーストを印刷して乾燥し、空
気雰囲気中で焼成して、まず貴金属導体を形成
し、その後に卑金属導体ペーストを用いて主配線
パターンを印刷し、乾燥後窒素雰囲気中で焼成し
て厚膜セラミツク基板を形成する技術を提案した
（特開昭57−130443号公報）。 For this reason, the applicant first printed a noble metal conductor paste such as gold on a ceramic substrate, dried it, and fired it in an air atmosphere to form a noble metal conductor, and then used a base metal conductor paste to form the main conductor. We proposed a technique in which a thick film ceramic substrate is formed by printing a wiring pattern, drying it, and then firing it in a nitrogen atmosphere (Japanese Patent Laid-Open No. 130443/1983).
しかし、この技術は、まず貴金属導体を形成し
たのち、卑金属ペーストにより配線パターンを形
成する技術であるため、卑金属、たとえば銅を主
配線パターンとして多層配線を行う多層配線セラ
ミツク基板には適用できないものであつた。
However, since this technology first forms a noble metal conductor and then forms a wiring pattern using a base metal paste, it cannot be applied to multilayer wiring ceramic boards in which multilayer wiring is performed using a base metal, such as copper, as the main wiring pattern. It was hot.
集積回路の進歩に伴い、多層配線のセラミツク
基板が広く使用されるような現在、主配線パター
ンとして卑金属を用いる多層配線基板の製造に適
用できる技術が求められており、しかも、接続部
の信頼性を低下せしめないセラミツク配線基板の
製造方法が求められていた。 With the progress of integrated circuits, ceramic substrates with multilayer wiring are now widely used, and there is a need for technology that can be applied to the production of multilayer wiring boards that use base metals as the main wiring pattern. There has been a need for a method for manufacturing ceramic wiring boards that does not reduce the performance.
また、一旦貴金属ペーストを塗布してから空気
中で焼成し、そののち、卑金属ペーストで配線パ
ターンを形成し、窒素雰囲気中で焼成するため、
その焼成が二度手間となり、焼成工程が一回です
まない問題もあつた。 In addition, since the noble metal paste is first applied and fired in the air, then the wiring pattern is formed with the base metal paste and fired in a nitrogen atmosphere.
There was also the problem that the firing process required two steps, and the firing process could only be completed once.
本発明は、このような要請に基づきなされたも
ので、卑金属を主配線パターンとする多層配線基
板の所要の接続部に金の電極を形成する安価でか
つ高信頼度のセラミツク配線基板を簡単な工程で
製造することができる製造方法を提供することを
目的とする。 The present invention was made based on such a request, and it is a simple method to create an inexpensive and highly reliable ceramic wiring board in which gold electrodes are formed at the required connection parts of a multilayer wiring board whose main wiring pattern is a base metal. The purpose is to provide a manufacturing method that can be manufactured in a process.
本発明の製造方法は、多層基板の主配線パター
ンを銅、ニツケル等の卑金属で形成し、その基板
の表面の主配線パターンの所要部に、窒素雰囲気
中で焼成可能な金ペーストを塗布した後乾燥し、
前記主配線パターンを形成した卑金属と金の合金
の融点以下でかつ500℃以上の温度範囲の窒素雰
囲気中で焼成して、前記主配線パターンの所要部
に金の電極を形成することを特徴とする。
The manufacturing method of the present invention involves forming the main wiring pattern of a multilayer board using base metal such as copper or nickel, and applying gold paste that can be fired in a nitrogen atmosphere to the required parts of the main wiring pattern on the surface of the board. dry,
The main wiring pattern is formed by firing in a nitrogen atmosphere at a temperature below the melting point of the alloy of base metal and gold and above 500°C to form gold electrodes at required parts of the main wiring pattern. do.
ここで卑金属とは金以外の安価な金属をいう
（岩波書店発行「理化学辞典」第３版増補版
（1981年２月発行））。本発明では銅またはニツケ
ルが適する。 Base metals here refer to inexpensive metals other than gold (``Dictionary of Physical and Chemical Science'' published by Iwanami Shoten, 3rd edition, expanded edition (published February 1981)). Copper or nickel are suitable for the present invention.
次に、本発明について、図面を参照して詳細に
説明する。
Next, the present invention will be explained in detail with reference to the drawings.
第１図は、本発明の製造方法によつて製造され
たセラミツク配線基板の一例を示す平面図であ
り、第２図はそのＡ−Ａ断面図である。該セラミ
ツク配線基板は、アルミナやホーロー引き鉄板か
ら成る基板１の上に主配線パターン２，４，６が
３層に形成される。該主配線パターンは、銅等の
卑金属を用い公知の厚膜印刷技術やメツキ技術等
によつて形成される。勿論各層の間には、絶縁層
３，５が形成される。そして、ボンデイング電極
７およびコンタクト電極８には、窒素雰囲気中で
焼成可能な金ペーストを印刷技術等によつて塗布
し、オーブンやベルト炉などで乾燥する。これを
500℃以上でかつ金ペーストと接触している卑金
属（例えば銅）と金の合金の融点（銅の場合は
889℃）以下の温度範囲の窒素雰囲気中の焼成炉
で焼成する。 FIG. 1 is a plan view showing an example of a ceramic wiring board manufactured by the manufacturing method of the present invention, and FIG. 2 is a sectional view taken along the line AA. The ceramic wiring board has three main wiring patterns 2, 4, and 6 formed on a substrate 1 made of alumina or enameled iron plate. The main wiring pattern is formed using a base metal such as copper by a known thick film printing technique, plating technique, or the like. Of course, insulating layers 3 and 5 are formed between each layer. Then, a gold paste that can be fired in a nitrogen atmosphere is applied to the bonding electrode 7 and the contact electrode 8 by a printing technique or the like, and then dried in an oven, a belt furnace, or the like. this
The melting point of an alloy of base metal (e.g. copper) and gold in contact with gold paste at 500°C or higher (in the case of copper
Fired in a furnace in a nitrogen atmosphere at a temperature range below 889°C.
この窒素雰囲気中で焼成するのは、主配線パタ
ーン２，４，６の卑金属の酸化の防止するためで
ある。特に、主配線パターン６は基板１の表面に
出ているためわずかな酸素があれば酸化してしま
う。空気中で500℃以上に温度を上げると、銅の
酸化は表面のみならず数ミクロン以上の深さ方向
にまで及び導体層として使用できない場合が生ず
る。また、窒素雰囲気中でも、焼成炉中に一部の
空気が混入して２〜20PPM程度の酸素濃度とな
るが、この程度であれば、主配線パターン６の表
面には極薄い酸化膜が形成されるが、導体として
の特性上にはほとんど影響はない。なお、この主
配線パターン６上に形成される極薄い酸化膜はワ
イヤボンデイングには致命的欠陥となるが、ワイ
ヤボンデイングを行う部分やコンタクト部分は、
金ペーストを用いるため、なんら問題とはならな
い。 The purpose of firing in this nitrogen atmosphere is to prevent the base metals of the main wiring patterns 2, 4, and 6 from being oxidized. In particular, since the main wiring pattern 6 is exposed on the surface of the substrate 1, it will be oxidized if there is a small amount of oxygen. When the temperature is raised to 500° C. or higher in air, the oxidation of copper occurs not only on the surface but also in the depth direction of several microns or more, making it impossible to use it as a conductive layer. Also, even in a nitrogen atmosphere, some air gets mixed into the firing furnace, resulting in an oxygen concentration of about 2 to 20 PPM, but at this level, an extremely thin oxide film is formed on the surface of the main wiring pattern 6. However, it has almost no effect on the characteristics as a conductor. Note that the extremely thin oxide film formed on the main wiring pattern 6 is a fatal defect for wire bonding, but the wire bonding area and contact area are
Since gold paste is used, there is no problem.
本実施例では、卑金属による主配線パターンと
金ペーストとを同時に焼成するときの主配線パタ
ーンの酸化を防止するため、窒素雰囲気中で焼成
する必要がある。卑金属の酸化防止のために窒素
雰囲気中で焼成する必要性については、出願人が
先に提案した特開昭57−130443号公報中にも同じ
旨の記載がされている。 In this embodiment, in order to prevent oxidation of the main wiring pattern when the main wiring pattern made of base metal and the gold paste are fired at the same time, it is necessary to perform firing in a nitrogen atmosphere. The necessity of firing in a nitrogen atmosphere in order to prevent oxidation of base metals is also described in Japanese Patent Application Laid-Open No. 130443/1983, which was previously proposed by the applicant.
このように、焼成炉中で焼成されることによ
り、ボンデイング性が良好で密着強度が強いボン
デイング電極７およびコンタクト電極８が形成さ
れる。該配線基板１上に搭載される集積回路チツ
プ１０は、金の細線１２により容易にボンデイン
グ電極７にボンデイングすることが可能である。
また、コンタクト電極８のコンタクト信頼性は大
である。 By firing in the firing furnace in this manner, the bonding electrode 7 and the contact electrode 8 having good bonding properties and strong adhesion strength are formed. The integrated circuit chip 10 mounted on the wiring board 1 can be easily bonded to the bonding electrode 7 using a thin gold wire 12.
Further, the contact reliability of the contact electrode 8 is high.
また、本発明が搭載部品の個数や種類、あるい
は配線パターンの層数が上記実施例より多いもの
であつても適用できることは勿論である。 Furthermore, it goes without saying that the present invention can be applied even if the number and types of mounted components or the number of layers of wiring patterns are greater than those of the above embodiments.
本発明は、このように、多層配線基板の主配線
パターンを卑金属で形成し必要部分に金ペースト
の焼成によつて金電極を形成させることにより、
安価でかつボンデイング等が容易で接続信頼性が
高い多層セラミツク配線基板を製造することがで
き、しかもその焼成工程が一回ですみ製造工程を
簡単化することができる効果がある。
According to the present invention, the main wiring pattern of the multilayer wiring board is formed of base metal, and gold electrodes are formed in necessary parts by firing gold paste.
It is possible to manufacture a multilayer ceramic wiring board that is inexpensive, easy to bond, etc., and has high connection reliability, and the firing process is required only once, which has the effect of simplifying the manufacturing process.
第１図は本発明の製造方法によつて製造された
セラミツク配線基板の一例を示す平面図。第２図
はそのＡ−Ａ断面図。
１……基板、２，４，６……主配線パターン、
３，５……絶縁層、７……ボンデイング電極、８
……コンタクト電極、１０……集積回路チツプ、
１２……細線。
FIG. 1 is a plan view showing an example of a ceramic wiring board manufactured by the manufacturing method of the present invention. FIG. 2 is a sectional view taken along line A-A. 1... Board, 2, 4, 6... Main wiring pattern,
3, 5... Insulating layer, 7... Bonding electrode, 8
...Contact electrode, 10...Integrated circuit chip,
12...Thin line.
Claims (1)
の主配線パターンを形成し、 該主配線パターン上の所要部分に焼成可能な金
ペーストを塗布した後乾燥し、 前記卑金属と金との合金の融点以下であつて
500℃以上の温度範囲の窒素雰囲気中で焼成して
前記主配線パターンの所要部に金電極を形成する ことを特徴とするセラミツク配線基板の製造方
法。 ２ 上記卑金属は銅である特許請求の範囲第１項
に記載のセラミツク配線基板の製造方法。[Claims] 1. A multilayer main wiring pattern is formed using base metal on a ceramic substrate, and a sinterable gold paste is applied to required portions of the main wiring pattern and then dried, and the base metal and the base metal are coated. Below the melting point of the alloy with gold
A method for manufacturing a ceramic wiring board, characterized in that gold electrodes are formed in required parts of the main wiring pattern by firing in a nitrogen atmosphere at a temperature range of 500°C or higher. 2. The method of manufacturing a ceramic wiring board according to claim 1, wherein the base metal is copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57168402A JPS5958848A (en) | 1982-09-29 | 1982-09-29 | Manufacture of ceramic wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57168402A JPS5958848A (en) | 1982-09-29 | 1982-09-29 | Manufacture of ceramic wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5958848A JPS5958848A (en) | 1984-04-04 |
| JPS641057B2 true JPS641057B2 (en) | 1989-01-10 |
Family
ID=15867450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57168402A Granted JPS5958848A (en) | 1982-09-29 | 1982-09-29 | Manufacture of ceramic wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5958848A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3225854B2 (en) * | 1996-10-02 | 2001-11-05 | 株式会社デンソー | Thick film circuit board and wire bonding electrode forming method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4940867A (en) * | 1972-08-25 | 1974-04-17 | ||
| JPS6041859B2 (en) * | 1980-02-13 | 1985-09-19 | 三菱電機株式会社 | semiconductor container |
| JPS57130443A (en) * | 1981-02-06 | 1982-08-12 | Nec Corp | Substrate for hybrid integrated circuit |
-
1982
- 1982-09-29 JP JP57168402A patent/JPS5958848A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5958848A (en) | 1984-04-04 |
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