JPS6411170B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency synthesizer having a phase lock loop whose frequency control code is a mixed number, and which incorporates a method of reducing unnecessary phase modulated waves output from a voltage controlled oscillator.

Conventionally, in order to obtain frequency increment steps below the reference frequency using a phase lock loop,
There is a digital frequency synthesizer having a configuration as shown in FIG.

In FIG. 1, a phase detector 12 receives the output of the reference frequency oscillator 11 and the output of the variable frequency divider 16 as inputs, and outputs a voltage according to the phase difference between the two signals. The output voltage of the phase detector 12 is applied to the voltage controlled oscillator 14 via the low frequency filter 13.

The variable frequency divider 16 is of a type in which the frequency division ratio can be switched between N and N-1 in accordance with the control signal output from the arithmetic unit 15. Here, N is an integer set by the frequency control code, and the voltage controlled oscillator 1
It is equal to the integer obtained by rounding up the decimal part of the value K obtained by dividing the output frequency _p of the reference frequency oscillator 11 by the output frequency _r of the reference frequency oscillator 11. A decimal frequency control code F, which will be described next, is a decimal set by the frequency control code, and is a value obtained by subtracting the K from the frequency division ratio N.
For example, if _p = 9.9 (MHz) and _r = 1 (MHz),
K=9.9, N=10, F=NK=0.1. The arithmetic unit 15 generates a control signal to switch the frequency division ratio of the variable frequency divider 16 from N to N-1 when the value obtained by cumulatively adding the control code F every reference period A/ _r exceeds 1. Has a function.

Now, in the above-mentioned phase lock loop, the time required for the cumulative addition value of the arithmetic unit 15 to exceed the integer 1 is 1/F times the reference period 1/ _r .

When the variable frequency divider 16 counts with a frequency division ratio of N or N-1, if the time frame in which counting of N or N-1 input pulses ends is one count frame, the length of the one count frame is Since it is 1/fr,
Within the period of (1/ _r )・(1/F), that is, the arithmetic unit 1
There are 1/F count frames within the time until the cumulative addition value of 5 exceeds the integer 1. 1/
Among the F count frames, the variable frequency divider 16
operates in N-divided frequency for (1/F-1) count frames, and only the remaining 1 count frame operates in N-1 frequency divided manner. Therefore, the average frequency division ratio per count frame is
N(1/F-1)+(N-1)/1/F=N(1-F)
+F(N-1)=N-F. As a specific example, when obtaining an average frequency division ratio of 9.9, with N=10 and F=0.1, the variable frequency divider 16 operates at a period of 10 times the reference period 1/ _r , that is, out of 10 count frames of 1/F. It operates by dividing 9 count frames by 10 and by dividing 1 count frame by 9 to obtain an average frequency division ratio of 9.9. Then, the output frequency _p of the voltage controlled oscillator 14
1/(N-F) is the reference frequency at the phase detector 12.
compared to _r . Therefore, with the phase lock loop having this configuration, an output frequency of _p = _r (N-F) can be extracted from the voltage controlled oscillator 14.

If the voltage controlled oscillator 14 is currently oscillating at a frequency _r (N-F), this frequency _p can be changed to (N-F).
F) Since the frequency should be divided by N for (1/F-1) count frames, the output frequency of the variable frequency divider 16 _{is r} (N-F)/N=
_r − _r・F/N, which is higher than the reference frequency _{r .}
The F/N will be lower.

As a result, the output of the variable frequency divider 16 for each count frame is N/ _r (N-F)-1/ _r = F/
The phase lags behind the output of the reference oscillator 11 by _r (N-F), that is, F times the oscillation period 1/ _p of the voltage-controlled oscillator 14 (F<1). When this phase error is accumulated and exceeds 1/ _p period, the variable frequency divider 1
The frequency division ratio of 6 is switched from N to N-1 by the control signal of the arithmetic unit 15, and the cumulative addition phase error is 1/
Return to below _p period. That is, the phase error varies as shown in FIG. However, the phase detector 12
As a result of detecting this phase error, the output of
As shown in the figure, a ripple component (phase fluctuation wave) appears in response to fluctuations in the phase error. This ripple component causes the voltage controlled oscillator 14 to generate a phase modulation sideband of the line spectrum near the frequency _p .

In order to reduce phase modulation sideband components included in the output of the voltage controlled oscillator 14, conventionally the oscillation frequency _p is set high to reduce the phase error and the cutoff frequency of the low frequency generator 13 is lowered. Alternatively, means such as providing a fixed frequency divider on the output of the voltage controlled oscillator 14 and dividing the frequency before extracting the signal have been devised.
The effect was not sufficient.

The present invention has been made in view of the above,
By substantially matching the phase of the input signal from the variable frequency divider and the phase of the input signal from the reference frequency oscillator at the input of the phase detector, a digital frequency synthesizer with frequency increment steps below the reference frequency can be used. The purpose is to reduce phase modulation sideband components.

An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 3 is a configuration diagram of a frequency synthesizer according to one embodiment of the present invention, and FIGS.
This figure is a diagram for explaining the operation of each part in the embodiment shown in FIG. 3. Further, FIG. 7 is a configuration diagram showing a frequency synthesizer according to another embodiment of the present invention.

In FIG. 3, 17 is a D/A converter consisting of a plurality of programmable counters 21 and a constant current source 2.
2, a capacitor C1, and a discharge switch 23. 18 is a pulse width modulator consisting of a monostable multivalve generator 24, resistors R1 and R2, and a capacitor C2.

In addition, the arithmetic unit 15 has a fractional part frequency control code F.
The D/ _A
In addition to adding it to the converter 17, the cumulative addition value becomes an integer 1.
When the frequency exceeds N, the frequency division ratio of the variable frequency divider 16 is changed from N to N.
Generates a signal to switch to -1.

The output of pulse width modulator 18 and the output of variable frequency divider 16 are both applied to phase detector 12 . The phase detector 12 detects the phase difference of the trailing edge of the input pulse, and the output signal of the phase detector 12 is applied to the voltage controlled oscillator 14 via the low frequency filter 13. The output of the voltage controlled oscillator 14 is then applied to a variable frequency divider 16 and a D/A converter 17, respectively.

Moreover, FIG. 4 shows operating waveforms in each part of FIG. 3.

Since the increment of the phase delay of the output signal of the variable frequency divider 16 for each count frame is F/ _p as described above, the oscillation frequency _p of the voltage controlled oscillator 14 and the fractional part frequency control code applied to the arithmetic unit 15 are F
Depends on. For now, _p = 20724950 (Hz), F =
When set to 0.01, the increment of phase delay is F/ _p =
0.01/20724950≒4.8×10 ^-10 (seconds), which is only 0.48 nanoseconds.

In order to provide the output of the reference frequency oscillator 11 with a phase change equivalent to this increment of phase delay, a D/A converter 17 and a pulse width modulator 18, which will be described below, are used.

First, the output A of the voltage controlled oscillator 14 is applied to the programmable counter 21, and as will be described later, a pulse L having a pulse width that is an integral multiple of the oscillation period 1/ _p is taken out from the programmable counter 21. That is, the cumulative addition value (<
1) is the minimum resolution G (minimum value of F) of the calculator 15
If the integer divided by Fn is Fn, the output pulse width of the programmable counter 21 will be equal to F _o / _p . As a concrete example, if G = 0.01 and F = 0.02, the cumulative addition value of the calculator 15 will be calculated every reference period 1/ _r .
0.02→0.04→0.06--→0.98→1.00→0.02, and the above integer Fn is 2, 4, 6...98, 0, 2
becomes. Programmable counter 2 accordingly
The output pulse width _of 1 is the integer Fn of 2, 4, 6...98, 0,
The time will be multiplied by 2.

That is _, as _{shown in FIG .}
This shows a state in which a pulse with twice the pulse width is extracted. The next output pulse width τ ₂ becomes τ ₂ =4/ _p , which is four times the oscillation period 1/ _p . Similarly, the output pulse width of the programmable counter changes according to the value cumulatively added by the arithmetic unit 15. As described below, the constant current source 22 is controlled according to this output pulse width, and the pulse width modulator 18
The reference frequency oscillator 11 changes the output pulse width of the reference frequency oscillator 11.
A phase change equivalent to a change in the phase delay of the variable frequency divider 16 is given to the output of the variable frequency divider 16.

The constant current source 22 is driven only during the pulse widths τ ₁ and τ ₂ , and the capacitor C1 is charged with a constant current, so that the terminal voltage thereof increases linearly as shown in FIG. 4C. Next, the output signal of the reference oscillator 11 shown in FIG. 4D activates the monostable multivibrator 24. As a result, the pulse shown in FIG. 4(e) is generated at the output. Monostable multivibrator 2
The output pulse widths τ ₃ and τ ₄ of 4 depend on the constants of the resistor R2 and capacitor C2, but since the terminal voltage of the capacitor C1 is applied to the reference voltage control terminal of the monostable multivibrator 24 through the resistor R1, the output The pulse width varies depending on the control voltage as shown in FIG. Then, the discharge switch 23 driven by the reset pulse shown in FIG.
Accordingly, the charge on the capacitor C1 is discharged during the pause period of the pulse width modulator output pulse shown in FIG. 4E. That is, the constant current source 22 and the discharge switch 2
3 and capacitor C1 constitute a pulse width-to-voltage conversion circuit that generates a voltage proportional to the output pulse width of the programmable counter and is reset by the output of the reference frequency oscillator.

Therefore, the relative phase difference between the falling instant of the pulse width modulator output signal (t ₂ or t ₄ in FIG. 4) with respect to the falling instant t ₁ or t ₃ of the reference oscillator output signal shown in FIG. time difference) changes as shown in FIG. On the other hand, when the voltage controlled oscillator 14 oscillates at a frequency _r (N-F) as described above, the phase error of the output signal of the variable frequency divider 16 with respect to the output signal of the reference frequency oscillator 11 is It changes as shown in the figure and is similar to Fig. 6. Therefore, the output of the pulse width modulator 18 and the variable frequency divider 1
6 is applied to the phase detector 12, the above-mentioned ripple component does not appear in the output of the phase detector 12 when the phase lock loop shown in FIG. 3 is synchronized.

FIG. 7 shows another embodiment of the present invention, in which the individual circuits are as explained in the first embodiment, but the duration and frequency division ratio of the pulse width modulator 18,
The setting of the control code and the function of the variable frequency divider 16 are different. That is, the output of the variable frequency divider 16 is applied to the pulse width modulator 18, and the phase detector 12 maintains the reference frequency oscillator output and the pulse width modulator output. M and P are set by a frequency control code and are equal to the integer part M and the fractional part of a value K obtained by dividing the output frequency _p of the voltage controlled oscillator 14 by the output frequency _r of the reference frequency oscillator 11. The variable frequency divider 16 normally operates at a frequency division ratio M, but when the cumulative value of the arithmetic unit 15 that cumulatively adds the fractional part frequency control code P exceeds an integer 1, the frequency division ratio changes from M to M
It has a function of switching to +1.

Now, when the voltage controlled oscillator 14 is oscillating at a frequency _r (M+P), the variable frequency divider 16 is set to (1/F-) out of 1/F count frames.
1) Divide the frequency by M for the count frames,
The remaining 1 count frame is divided by M+1.

Therefore, the phase of the output of the variable frequency divider advances by P times the oscillation period 1/ _p of the voltage controlled oscillator 14 every reference period 1/ _r while the variable frequency divider is operating at M frequency division. This phase advance is temporarily canceled because it is delayed by 1/ _p period when the variable division period 16 is divided by M+1.

However, since the above-described operation is repeated, a fluctuation in the phase error as shown in FIG. 2 occurs.

The variable frequency divider output, including this phase error variation, is
A phase change is given by the output of the D/A converter 17 which is added to the pulse width modulator 18 and converts the accumulated value outputted from the arithmetic unit into an analog signal according to the output signal of the voltage controlled oscillator 14. Here, D/A
The converter 17 outputs an analog signal that widens the pulse width of the pulse width modulator output and retards the phase of the trailing edge of the pulse with respect to the phase advance of the variable frequency divider output. Therefore, fluctuations in the phase error of the variable frequency divider output are canceled out, and no ripple component appears in the output of the phase detector 12 when the phase lock loop shown in FIG. 7 is synchronized.

Incidentally, in the first embodiment of the present invention, a phase change equivalent to the fluctuation of the phase error of the variable frequency divider output is applied to the reference frequency oscillator output, and in the second embodiment, a variable frequency divider is applied to the variable frequency divider output. Although a pulse width modulator was used to provide a fluctuation in the output phase error and a phase change in the opposite phase, such a modulator is not limited to the above embodiment. Since it is sufficient to add a signal that has undergone predetermined signal processing, an analog pulse modulator such as a pulse phase modulator may be used.

As explained above, according to the present invention, the ripple component corresponding to the fluctuation of the phase error of the variable frequency divider output does not appear in the output of the phase detector, so that the phase modulation sideband component of the voltage controlled oscillator can be reduced. .
Furthermore, since the effect of canceling the fluctuation of the phase error is performed at the input end of the phase detector, even if there is a dead zone due to the circuit type of the phase detector, there is an advantage that the canceling phase modulation component can be avoided from being added to the phase lock loop as a disturbance. be.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a conventional digital frequency synthesizer, FIG. 2 is a phase fluctuation waveform diagram of a phase detector output with a conventional configuration, and FIG. 3 is a configuration diagram of a frequency synthesizer showing a first embodiment. Figure 4 is an operating waveform diagram for each part in Figure 3, Figure 5 is a modulation characteristic diagram of the pulse width modulator shown in Figure 3, and Figure 6 is a phase fluctuation waveform diagram of the output of the pulse width modulator shown in Figure 3. , FIG. 7 is a block diagram showing the second embodiment. 11... Reference frequency oscillator, 12... Phase detector, 13... Low-pass filter, 14... Voltage controlled oscillator, 15... Arithmetic unit, 16... Variable frequency divider, 17
...D/A converter, 18...Pulse width modulator.

Claims (1)

[Scope of Claims] 1. In the frequency synthesizer having a phase lock loop in which the frequency control code of the frequency synthesizer is a mixed number, the frequency synthesizer includes a voltage controlled oscillator, a reference frequency oscillator, and an oscillation period at the leading edge of the output pulse of the reference frequency oscillator. an arithmetic unit that cumulatively adds a decimal value F obtained by subtracting the required frequency division ratio K from an integer value N obtained by rounding up the decimal part of the required frequency division ratio K, and dividing the output of the voltage controlled oscillator by the integer value N; and a variable frequency divider with a switchable division ratio that divides the frequency by N-1 when the output of the arithmetic unit exceeds 1, and an integer obtained by dividing the cumulative addition value of the arithmetic unit by the minimum resolution of the arithmetic unit. a programmable counter that outputs a pulse with a time width multiplied by the oscillation period of the voltage controlled oscillator; and a pulse width-to-voltage converter that generates a voltage proportional to the output pulse width of the programmable counter and that is reset by the output of the reference frequency oscillator. an analog pulse modulator that changes the trailing edge of the output pulse of the reference frequency oscillator by the output voltage of the pulse width-to-voltage conversion circuit; and a phase difference between the output of the analog pulse modulator and the output of the variable frequency divider. A frequency synthesizer comprising: a phase detector for detecting a phase detector; and a low-pass filter for filtering the output of the phase detector and supplying the filtered output to a control input of the voltage controlled oscillator. 2. In the frequency synthesizer having a phase lock loop in which the frequency control code of the frequency synthesizer is a mixed number, the frequency synthesizer includes a voltage controlled oscillator, a reference frequency oscillator, and a required frequency division ratio for each oscillation period at the leading edge of the output pulse of the reference frequency oscillator. an arithmetic unit that cumulatively adds a decimal value P of K; and a frequency division ratio that divides the output of the voltage controlled oscillator by an integer value M of the frequency division ratio K and divides it by M+1 when the output of the arithmetic unit exceeds 1. a programmable counter that outputs a pulse with a time width equal to the oscillation period of the voltage controlled oscillator multiplied by an integer obtained by dividing the cumulative addition value of the arithmetic unit by the minimum resolution of the arithmetic unit; a pulse width-to-voltage conversion circuit that generates a voltage proportional to the output pulse width of the programmable counter and is reset by the output of the reference frequency oscillator, and a pulse width-to-voltage conversion circuit that converts the trailing edge of the output pulse of the variable frequency divider into an analog pulse modulator that varies depending on the circuit output voltage; a phase detector that detects a phase difference between the output of the analog pulse modulator and the output of the reference frequency oscillator; A frequency synthesizer, characterized in that it has a low-pass filter feeding a control input.