JPS6412103B2 - - Google Patents
Info
- Publication number
- JPS6412103B2 JPS6412103B2 JP54056159A JP5615979A JPS6412103B2 JP S6412103 B2 JPS6412103 B2 JP S6412103B2 JP 54056159 A JP54056159 A JP 54056159A JP 5615979 A JP5615979 A JP 5615979A JP S6412103 B2 JPS6412103 B2 JP S6412103B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- contact
- conductor
- unit
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/209—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only resistors
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は抵抗回路網を備える半導体装置に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a resistor network.
近年、半導体装置の応用分野の拡大はめざまし
いものがあり、従来個別部品、または調整技術を
用いて十分な精度が必要とされる分野へと急速に
浸透している。 In recent years, the field of application of semiconductor devices has been expanding at a remarkable rate, and they are rapidly penetrating into fields that require sufficient precision using conventional individual components or adjustment techniques.
このような一例として、抵抗回路網と基準電圧
源を用いた電圧分割回路が考えられる。この電圧
分割回路は並列形アナログ・デジタル変換器でよ
く使用されるものである。並列形アナログ・デジ
タル変換器は、電圧分割回路と複数個の比較器群
により構成されるものである。入力アナログ信号
の電圧と電圧分割回路の電圧を比較器群により比
較し、デジタル出力信号を得る機能を持つてい
る。このため、電圧分割回路の精度が並列形アナ
ログ・デジタル変換器の精度を決めることにな
る。 One such example is a voltage divider circuit using a resistor network and a reference voltage source. This voltage divider circuit is often used in parallel analog-to-digital converters. A parallel analog-to-digital converter is composed of a voltage dividing circuit and a plurality of comparator groups. It has the function of comparing the voltage of the input analog signal and the voltage of the voltage divider circuit using a group of comparators and obtaining a digital output signal. Therefore, the accuracy of the voltage divider circuit determines the accuracy of the parallel analog-to-digital converter.
電圧分割回路を構成する抵抗回路網を高精度で
実現する方法として、単位抵抗体群を縦続接続し
てなる抵抗回路網が一般的である。一例を第1図
(平面図)に示す。半導体基板に多数の単位抵抗
体(例えば拡散抵抗またはポリシリコン抵抗等)
11が並んで設けられ、それらが相互接続導体1
2と一定面積のコンタクト部13において電気的
に接続され、直列接続される。第1図の抵抗回路
網は精度に関して優れた方法であるが、単位抵抗
体群のそれぞれを分離する必要があるため、集積
度の低下という問題点はさけられない。 As a method for realizing a resistor network constituting a voltage dividing circuit with high precision, a resistor network formed by cascading a group of unit resistors is commonly used. An example is shown in FIG. 1 (plan view). A large number of unit resistors (e.g. diffused resistors or polysilicon resistors) on a semiconductor substrate
11 are provided side by side, which interconnect conductors 1
2 and a contact portion 13 having a constant area, and are connected in series. Although the resistor network shown in FIG. 1 is an excellent method in terms of accuracy, it is necessary to separate each of the unit resistor groups, so the problem of a reduction in the degree of integration cannot be avoided.
第1図の抵抗回路網を集積度を向上する目的で
改善した一例を第2図(平面図)に示す。第2図
に示すように第1図における相互接続導体をでき
るだけ省略しコンタクト部を重ねることにより集
積度の向上を計つている。すなわち、第1図の単
位抵抗体を直接接続した長い抵抗体21を相互接
続導体12によつてコンタクト部13において直
列接続するとともに、該長い抵抗体に単位抵抗体
に相当する間隔で設けられたコンタクト部23か
ら分割電圧取り出し導体24が導出される。 An example of an improved resistor network shown in FIG. 1 for the purpose of increasing the degree of integration is shown in FIG. 2 (plan view). As shown in FIG. 2, the interconnection conductors in FIG. 1 are omitted as much as possible and the contact portions are overlapped to improve the degree of integration. That is, long resistors 21, each of which is directly connected to the unit resistors shown in FIG. A divided voltage extraction conductor 24 is led out from the contact portion 23 .
第2図の抵抗回路網は集積度の向上を計つてい
るものの、コンタクト抵抗のばらつきに対し精度
上の欠点を有している。すなわち、第1図の如き
抵抗回路網においては単位抵抗体の抵抗値のばら
つきと、コンタクト抵抗のばらつきが独立に生じ
た場合においても単位抵抗体毎に同じ2個のコン
タクトを有するので、抵抗回路網の精度には影響
がない。これに対し、第2図の如き抵抗回路網の
構成においては、抵抗体の抵抗値のばらつきとコ
ンタクト抵抗のばらつきが独立に生じた場合、抵
抗体の折り返し部分にだけ2個のコンタクトを有
するので、その部分で精度が劣化するのは明らか
である。 Although the resistor network of FIG. 2 is intended to improve the degree of integration, it has a drawback in terms of accuracy due to variations in contact resistance. In other words, in a resistor network as shown in Fig. 1, even if variations in resistance value of unit resistors and variations in contact resistance occur independently, each unit resistor has the same two contacts, so the resistance circuit The accuracy of the net is not affected. On the other hand, in the configuration of a resistor network as shown in Figure 2, if variations in resistance value of the resistor and variations in contact resistance occur independently, two contacts are provided only at the folded portion of the resistor. , it is clear that the accuracy deteriorates in that part.
第2図の抵抗回路網の等価回路図を第3図に示
す。第3図において、31は一つのコンタクトか
ら次のコンタクト迄の抵抗(単位抵抗)を、32
は相互接続導体の抵抗を、33はコンタクト抵抗
を、34は取り出し導体端子をそれぞれ示す。第
3図から分るように、単位抵抗31と次の単位抵
抗31との間には通常は1個のコンタクト抵抗3
3が介在するだけであるが、折り返し部(長い抵
抗体同志の接続部)においては2個のコンタクト
抵抗33が介在することになる。したがつて、単
位抵抗体の抵抗値のばらつきとコンタクト抵抗の
抵抗値のばらつきが独立して生じるときには、こ
の折り返し部分におけるコンタクト抵抗のばらつ
きが抵抗回路網の精度の限界を決めることにな
る。 An equivalent circuit diagram of the resistor network shown in FIG. 2 is shown in FIG. In Figure 3, 31 is the resistance (unit resistance) from one contact to the next, and 32
indicates the resistance of the interconnection conductor, 33 indicates the contact resistance, and 34 indicates the lead-out conductor terminal. As can be seen from FIG. 3, there is usually one contact resistor 3 between one unit resistor 31 and the next unit resistor 31.
However, two contact resistors 33 are present at the folded portion (connection portion between long resistors). Therefore, when variations in the resistance value of the unit resistor and variations in the resistance value of the contact resistor occur independently, the variation in the contact resistance in this folded portion determines the limit of accuracy of the resistor network.
コンタクト抵抗の抵抗値に比較して単位抵抗体
の抵抗値を大きくすれば精度は向上するが、集積
度の低下はさけられない。 If the resistance value of the unit resistor is made larger than the resistance value of the contact resistor, accuracy will be improved, but a decrease in the degree of integration cannot be avoided.
本発明は前記欠点を改善し、集積度を低下させ
ることなく、精度の優れた抵抗回路網を備える半
導体装置を提供するものである。 The present invention improves the above-mentioned drawbacks and provides a semiconductor device equipped with a highly accurate resistor network without reducing the degree of integration.
以下、実施例に基づき本発明を詳細に説明す
る。 Hereinafter, the present invention will be explained in detail based on Examples.
第4図a及びbは本発明の第1の実施例を説明
するための平面図及び断面図である。同図におい
て、46は半導体基板、41は該半導体基板に形
成された拡散抵抗(長い抵抗体)、47は表面に
被覆された絶縁膜(通常はシリコン酸化膜)、4
2は前記拡散抵抗同志を相互に接続するための導
体、45は拡散抵抗と接続導体のコンタクト部、
44は分割電圧の取り出し導体、43は該取り出
し導体と拡散抵抗のコンタクト部である。 FIGS. 4a and 4b are a plan view and a sectional view for explaining the first embodiment of the present invention. In the figure, 46 is a semiconductor substrate, 41 is a diffused resistor (long resistor) formed on the semiconductor substrate, 47 is an insulating film (usually a silicon oxide film) coated on the surface, 4
2 is a conductor for connecting the diffused resistors to each other; 45 is a contact portion between the diffused resistor and the connecting conductor;
Reference numeral 44 denotes a divided voltage extraction conductor, and 43 a contact portion between the extraction conductor and the diffused resistor.
本実施例では、抵抗体と取り出し導体とのコン
タクト部43の面積に対して、抵抗体と接続導体
とのコンタクト部45の面積を約2倍にして形成
している点が特徴である。コンタクト面積を約2
倍にすることにより従来の欠点を除去するもので
ある。 This embodiment is characterized in that the area of the contact section 45 between the resistor and the connecting conductor is approximately twice the area of the contact section 43 between the resistor and the lead-out conductor. The contact area is approximately 2
By doubling the amount, the disadvantages of the conventional method are eliminated.
一般にコンタクト部のコンタクト抵抗Rconは、
単位抵抗器1と相互接続導体2間の表面伝導率
σcとコンタクト部の面積Sの関数で表現される。 Generally, the contact resistance Rcon of the contact part is
It is expressed as a function of the surface conductivity σc between the unit resistor 1 and the interconnection conductor 2 and the area S of the contact portion.
Rcon=K1/σcS ……(1)
(ただしK;定数)
式(1)より、表面伝導率σcが一定とすれば、コ
ンタクト部の面積を2倍にすればコンタクト抵抗
Rconは1/2にすることができる。すなわち抵抗体
の折り返し接続部分のコンタクト抵抗の和は折り
返し部分以外のコンタクト抵抗と同じ抵抗値とす
ることができ、コンタクト抵抗のばらつきと抵抗
体の抵抗値のばらつきが独立して生じた場合に
も、抵抗回路網の精度を劣化させることはない。 Rcon=K1/σcS...(1) (K: constant) From formula (1), if the surface conductivity σc is constant, doubling the area of the contact area will increase the contact resistance.
Rcon can be reduced to 1/2. In other words, the sum of the contact resistances of the folded connection parts of the resistor can be the same as the contact resistance of the parts other than the folded parts, and even if the variation in contact resistance and the variation in the resistance value of the resistor occur independently. , without degrading the accuracy of the resistor network.
第5図は本発明の第2の実施例を示す平面図で
ある。本実施例も抵抗体51と分割電圧取り出し
導体54のコンタクト部53の面積に対して、抵
抗体51と接続導体52とのコンタクト部55の
面積を約2倍に形成したものであるが、更に抵抗
体のコンタクト部以外の部分を細く形成してある
ので、前記第4図の実施例に比較して単位抵抗体
の抵抗値を高くすることができる。 FIG. 5 is a plan view showing a second embodiment of the invention. In this embodiment as well, the area of the contact portion 55 between the resistor 51 and the connecting conductor 52 is approximately twice the area of the contact portion 53 between the resistor 51 and the divided voltage take-out conductor 54. Since the portions of the resistor other than the contact portions are formed thin, the resistance value of the unit resistor can be increased compared to the embodiment shown in FIG. 4.
尚、前記第4図の実施例では拡散抵抗の場合に
ついて述べたが、本発明はその他の抵抗、例えば
ポリシリコン抵抗、その他の薄膜抵抗などにも十
分適用することができる。 In the embodiment shown in FIG. 4, the case of a diffused resistor has been described, but the present invention can be sufficiently applied to other resistors such as polysilicon resistors and other thin film resistors.
以上、図面を用いて詳細に説明した如く、本発
明を用いれば、集積度が高く、精度の優れた抵抗
回路網を持つた半導体装置を実現でき、半導体装
置の応用分野の拡大に有効である。 As described above in detail with reference to the drawings, by using the present invention, it is possible to realize a semiconductor device with a high degree of integration and a resistor network with excellent accuracy, which is effective in expanding the field of application of semiconductor devices. .
第1図および第2図は従来の抵抗回路網の平面
図、第3図は第2図の等価回路図、第4図a及び
bは本発明の第1の実施例の平面図及びA―A断
面図、第5図は本発明の第2の実施例の平面図で
ある。
11…単位抵抗体、12,22,42,52…
接続導体、13,23,43,53…相互接続導
体、21,51…抵抗体、24,44,54…取
り出し導体、31…単位抵抗、32…接続導体の
抵抗、33…コンタクト抵抗、34…取り出し端
子、45,55…抵抗体と接続導体とのコンタク
ト部、46…半導体基板、47…絶縁膜。
1 and 2 are plan views of a conventional resistor network, FIG. 3 is an equivalent circuit diagram of FIG. 2, and FIGS. 4a and 4b are plan views and A- A sectional view and FIG. 5 are plan views of a second embodiment of the present invention. 11... Unit resistor, 12, 22, 42, 52...
Connection conductor, 13, 23, 43, 53... Interconnection conductor, 21, 51... Resistor, 24, 44, 54... Takeout conductor, 31... Unit resistance, 32... Resistance of connection conductor, 33... Contact resistance, 34... Output terminal, 45, 55... Contact portion between resistor and connection conductor, 46... Semiconductor substrate, 47... Insulating film.
Claims (1)
た複数の単位抵抗体同志を接続導体により直列に
接続した抵抗回路網を半導体基板に形成した半導
体装置において、前記接続導体と前記単位抵抗と
の各接続部の接触部を前記取り出し導体と前記単
位抵抗体との回接続部のほぼ半分の接触抵抗とな
るようにしたことを特徴とする半導体装置。1. In a semiconductor device in which a resistor network is formed on a semiconductor substrate in which a plurality of unit resistors each having one or more lead-out conductors led out from an intermediate portion are connected in series by a connecting conductor, the connection between the connecting conductor and the unit resistor is A semiconductor device characterized in that a contact portion of each connection portion has a contact resistance approximately half that of a circuit connection portion between the lead-out conductor and the unit resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5615979A JPS55148453A (en) | 1979-05-08 | 1979-05-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5615979A JPS55148453A (en) | 1979-05-08 | 1979-05-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55148453A JPS55148453A (en) | 1980-11-19 |
| JPS6412103B2 true JPS6412103B2 (en) | 1989-02-28 |
Family
ID=13019307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5615979A Granted JPS55148453A (en) | 1979-05-08 | 1979-05-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55148453A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0342909U (en) * | 1989-09-04 | 1991-04-23 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5673458A (en) * | 1979-11-20 | 1981-06-18 | Nec Corp | Semiconductor device |
| JPS59104159A (en) * | 1982-12-07 | 1984-06-15 | Nec Corp | Resistance row voltage dividing circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5384579A (en) * | 1976-12-29 | 1978-07-26 | Fujitsu Ltd | Manufacture for semiconductor device |
-
1979
- 1979-05-08 JP JP5615979A patent/JPS55148453A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0342909U (en) * | 1989-09-04 | 1991-04-23 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55148453A (en) | 1980-11-19 |
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