JPH0225260B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a resistor network.

In recent years, the field of application of semiconductor devices has been expanding at a remarkable rate, and they are rapidly penetrating into fields that require sufficient precision using conventional individual components or adjustment techniques. As an example of this, consider the field of analog-to-digital conversion signal processing that converts analog signals into digital signals. This involves converting a time-continuous signal such as an analog signal into a time-discrete signal such as a digital signal. For this reason, the analog-to-digital conversion circuit naturally requires a sample-and-hold circuit. When converting an analog signal into a sample-and-hold digital signal at a certain period, it is necessary to limit the band of the analog signal using an aliasing distortion prevention filter in order to ensure the accuracy of the conversion system. For example, when converting a 4KHz analog signal to a digital signal, it takes 125μs.
The sample-hold period is the minimum period for preventing aliasing distortion. That is, in order to avoid aliasing distortion, it is necessary to band limit the input analog signal. For this purpose, the technology used for semiconductor devices has generally been to construct a CR filter with a capacitor using polycrystalline silicon or diffusion as a resistor and an insulator as a dielectric. In order to increase the time constant of CR and extend the operating frequency of the filter to the low frequency range, the resistance R must be increased, but the capacitance C
It is obvious that the only option is to increase the

Conventionally, this purpose required a large semiconductor area. To avoid this, a resistor with a reduced amount of impurities diffused into polycrystalline silicon can be considered, but the sheet resistance of such a resistor varies significantly depending on manufacturing conditions, and it is difficult to control the CR time constant. Improving one's sexuality will naturally be restricted. Also, resistors using P-well and N-well regions used in CMOS etc. can be considered, but such resistors have a large voltage-to-resistance coefficient and a large junction capacitance, resulting in large fluctuations in frequency characteristics. It had the following drawbacks.

The present invention does not have such drawbacks, makes it possible to minimize the semiconductor area, and construct a resistor with excellent specific accuracy using polycrystalline silicon, and is very useful for expanding the field of application of semiconductor devices.

A semiconductor device according to the present invention includes a first resistor made of a first polycrystalline silicon on an oxide film formed on a silicon substrate, and a first resistor made of a first polycrystalline silicon on an oxide film formed on a silicon substrate, and a first resistor made of a first polycrystalline silicon and a first resistor made of a first polycrystalline silicon on an oxide film formed on a silicon substrate. The present invention is characterized in that two second resistors made of polycrystalline silicon are formed adjacent to each other.

Hereinafter, the present invention will be explained in detail based on Examples. The present invention significantly reduces the area of a semiconductor device by combining a first polycrystalline silicon to be used as a first resistor layer and a second polycrystalline silicon to be used as a second resistor layer, and the combined resistance This method is characterized by being able to minimize variations occurring during body manufacturing, and explanatory diagrams of examples thereof are shown in FIGS. 1 and 2. FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along line X-X' in FIG. 1. A first layer formed on an oxide film 8 formed on a silicon substrate by thermal oxidation.
After thermally oxidizing the polycrystalline silicon resistor 4 and the first polycrystalline silicon resistor, the second polycrystalline silicon resistor 5 is formed adjacent to each other, and then the contact 3 is opened and the lead-out conductor 1 and 2, an example of a resistor constructed by interconnecting conductors 6 and 7. With this configuration, the spacing required by the whiskers of polycrystalline silicon when forming polycrystalline silicon using photoengraving technology is no longer required, and the area of the semiconductor device does not need to be increased. It is clear that there is no.
That is, after forming the first polycrystalline silicon by photolithography and forming an oxide film, an electrical connection is established between the first polycrystalline silicon and the second polycrystalline silicon in order to form the second polycrystalline silicon. No conduction occurs, and therefore approximately twice as much resistance can be created in the same area. Since the oxide film 10 is interposed between the first polycrystalline silicon and the second polycrystalline silicon, no electrical conduction occurs. In this example, the first polycrystalline silicon resistor and the second polycrystalline silicon resistor are explained as having the same shape, and the first polycrystalline silicon resistor is provided in the take-out portion.
Although the explanation uses a polycrystalline silicon resistor,
In carrying out the present invention, the first polycrystalline silicon resistor and the second polycrystalline silicon resistor are formed adjacent to each other regardless of their shape or number. It is also possible to form the polycrystalline silicon resistor and the second polycrystalline silicon resistor so that they overlap each other. As described above in detail with reference to the drawings, by using the present invention, a semiconductor device with a high degree of integration and less manufacturing errors can be realized by using the first and second polycrystalline silicon resistors. It is effective in expanding the field.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are respectively a plan view and a cross-sectional view of an embodiment of the present invention. 1, 2...Output conductor, 3...Contact, 4
... first polycrystalline silicon, 5 ... second polycrystalline silicon, 6, 7 ... interconnection conductor, 8 ... oxide film,
9...Silicon substrate.

Claims (1)

[Claims] 1. Each first layer is placed on the insulating layer covering the silicon substrate.
a plurality of first resistors formed of polycrystalline silicon; and a plurality of second resistors each formed of second polycrystalline silicon on the insulating layer; A semiconductor device characterized in that the resistors are alternately arranged adjacent to each other with an insulating film interposed therebetween, forming a resistor whose resistance value is a combined resistance value of a predetermined number of first and second resistors.