JPS641745B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a cathode ray tube that displays analog waveforms by horizontal raster scanning, and a buffer memory that transfers display data corresponding to the longitudinal amplitude of the cathode ray tube for each vertical scan. The display memory is equipped with a display memory, and every time a horizontal raster scan is performed while shifting vertically on the screen, all addresses are read out from this memory, and a dot is placed at the intersection of the display data of each address and the horizontal raster. The present invention relates to a horizontal raster scanning type cathode ray tube waveform display device.

[Problems to be solved by conventional technology and invention]

In this type of device, if the number of dots displayed on the screen is small, the analog waveform may be displayed in a step-like manner, and although it is desirable to have a large number of dots, the number of dots displayed on the screen may be small. Limited by response speed, etc. For this reason, a well-known method is to convert the data read from the display memory into an analog signal, smooth it, and then display it as dots through an analog comparator.
In the case of a spike-like waveform, even if a peak is detected during data sampling, its amplitude is displayed small due to smoothing. In addition, there is a well-known method of displaying multiple dots for each address by interpolating dots between display data of adjacent addresses, but since dots are not displayed at intermediate positions between each address, However, there was a limit to the ability to perform smooth interpolation corresponding to the original analog waveform.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a horizontal raster scanning cathode ray tube waveform display device that can improve waveform reproducibility by performing dot interpolation at intermediate positions between addresses.

[Means to solve the problem]

In order to achieve this object, the present invention provides a waveform display device as shown in FIG. 2, a display memory 3 to which data is transferred from this memory, a circuit 4b that generates a horizontal synchronizing pulse every time a number of clock pulses corresponding to the total number of addresses of this memory is input, and a circuit 4b that generates a predetermined number of horizontal synchronizing pulses. A control circuit 4 includes a circuit 4a that generates a vertical synchronizing pulse for each horizontal raster scan, causes all addresses to be read for each horizontal raster scan, and performs the transfer for each vertical scan; A counter 5 that is reset for each scan, and a first latch circuit 6 that sequentially holds display data of address N that is sequentially generated by reading out data from the display memory 3.
, a second latch circuit 7 that holds the display data of address N-1 one address before, and these first
And in order to Z-divide the output display data of the second latch circuit, calculate Z-1 division points D ₁ , D ₂ ...D _Z-1 from address N to N-1 display data, respectively. Z-1 division point calculation circuits 8 ₁ to
8 _Z-1 , a comparator 9 that compares the count value n of the counter 5 and the output display data of the latch circuits 6 and 7 for each horizontal raster scan, and the output data of this comparator is input to address N and N-. A dot display signal is generated every time a count value n corresponding to the display data of 1 is generated, and the dot display signal when the signal matches the display data of address N is relatively displayed for a time T to other dots. A dot display signal generation circuit 10 that delays the display signal, Z-1 comparators 11 ₁ to 11 _Z-1 that compare the count value n and each division point, and the output data of these comparators and the comparator 9. Count value n using each output data as input
Z-1 count value judgment circuits 12 ₁ to 12 _Z-1 which judge whether or not the dot is on the display data side of the address N with respect to the division point to which it belongs, and the dot display signal T/Z each. Consisting of Z-1 pieces with increasing delay times, and dividing point D _Z-1 ...D ₂ ,
It is equipped with delay circuits 13 ₁ to 13 _Z-1 corresponding to D ₁ , and inputs the output data of the count value judgment circuit to calculate the count value n.
Dividing point to locate on the display data side of address N
D ₁ , D ₂ ...D Output a dot display signal through a delay circuit corresponding to the dividing point closest to the display data among _Z-1 , or without going through the delay circuit if such a dividing point does not exist. The dot display signal output circuit 13 is configured to include a dot display signal output circuit 13.

[Effect]

This will be explained with reference to FIG. 1b.

The display data transferred from the buffer memory 2 to the display memory 3 for each vertical scan is read out in synchronization with each horizontal raster scan from one end face of the cathode ray tube 1 to the other end face.
Therefore, the display data of addresses N and N-1 are sequentially latched in the first and second latch circuits 6 and 7 while being updated. Further, the counter 5 is reset every vertical scan, and the number n of horizontal raster scan lines is
Count. Comparator 9 has addresses N, N-
The display data of 1 and the count value n of the counter 5 are compared, and each time a count value n corresponding to the data value between these display data is generated, comparator output data B, C, D, ...X is generated. In addition, if a count value n that matches the display data of address N is input, comparator output data A that means this is input.
(display data) is generated. The dot display signal generation circuit 10 generates the signals B, C, D,
...A dot display signal Ad delayed by a predetermined time T relative to X is generated. In FIG. 1b, every dot display signal is shown with its own delay time t. During this time, division point calculation circuits 8 ₁ , 8 ₂ ...
...8 _Z-1 calculates the division points D ₁ , D ₂ ...D _Z-1 , and the comparators 11 ₁ , 11 ₂ ... 11 _Z-1 compare the belonging division point data and the count value n. , outputs data representing the magnitude of the count value n with respect to the division point. The count value judgment circuit 12 ₁ , 12 ₂ , ... 12 _Z-1 is connected to the comparator 9 and the associated comparators 11 ₁ , 1
1 ₂ ,...11 With the output data of _Z-1 as input, comparator output data B, C, D... between each division point and display data A of address N.
Determine whether or not X exists. The delay circuit 13 determines the dividing point closest to the display data A among the dividing points that locate the comparator output data B, C, D... Delay circuit 13 ₁ or 13 ₂
...or output via 13 _Z-1 . That is, when horizontal raster scanning line _H1 is generated, its count value n matches display data A at address N, so its dot display signal Ad is output with a relative delay of time T (absolutely T+t). be done. The comparator output data B of the horizontal raster scanning line H ₂ is on the display data A side with respect to all division points, but the division point D ₁ is closest to this, and the corresponding delay circuit 13 ₁ is selected. Been (Z-1)/Z・T+t
is output as a dot display signal Bd. Similarly, for comparator output data C and D, (Z-2)/Z・T+t, (Z-3)/
It is output with a delay of Z·T+t. Regarding the _{comparator output} data It becomes Xd.

[Embodiments of the invention]

In Fig. 2a, the display data at addresses N and N-1 is divided into two and interpolated in a gradient manner, and the dot display signal corresponding to the display data at address N is output for exactly one address lock time T of horizontal raster scanning. An example in which the delay is performed will be shown. In the same figure, Figure 1a
The same reference numerals as in the above indicate the same parts. The comparators 19a and 19b functionally correspond to the comparator 9, and output data outputs a, b, c, d, and e based on the results of the logical judgments below, respectively.

a: “1” when n>N b: “1” when n<N c: "1" when n>N-1 d: "1" when n<N-1 e: "1" when n=N-1 Here, N: display data of address N.

n: Count value n The division point calculation circuit 18 calculates 1/2 points of the display data at addresses N and N-1. The dot display signal generation circuit 20 outputs the next logical operation result Y as a dot display signal.

Y=ad+bc+e The comparator 21 outputs a data output f based on the next comparison result.

f: "1" when n>{N+(N-1)}/2.

The exclusive OR circuit 22 receives the data outputs b and f and functions as the count value judgment circuit 12.

The dot display signal output circuit 23 has T/2 (T:
As described above, a switch 23 supplies output data Y, which becomes a dot display signal, to the delay circuit 23a when the output data g of the exclusive OR circuit 22 is "0".
b, and an OR gate 2 that outputs the T/2 delayed or non-delayed output data Y as a dot display signal h.
3c.

The operation is as follows.

FIG. 2b shows the waveforms of various circuits and dot display signals when the analog input signal is a triangular wave. For example, display data A at address 2, which coincides with horizontal raster H, is delayed by one address clock interval T and becomes a dot display signal Ad having the same time width T. Comparator output data B at address 2 according to horizontal raster H is the 1/2 division point (coinciding with comparator output data C)
Because the display data is on the A side, it is delayed by T/2 and becomes the dot display signal Bd, and the comparator output data D at address 5 is on the opposite side to the 1/2 divided display data A side, so it becomes a dot as it is. It becomes a display signal. The comparator output data C at the 1/2 division points at addresses 2 and 5, which coincide with the horizontal raster H, is delayed by T/2 at address 2, which is a rising region, and becomes a dot display signal Cd, and at address 5, which is a falling region, it is output as a dot display signal Cd. A dot display signal is generated without delay. horizontal raster H
For , the comparator output data D at address 2 is on the opposite side of the address display data A at the 1/2 division point, so there is no delay, and at address 5, it is on the side of address display data A, so it is 1/2 Delayed dot display signal
Becomes Bd.

FIG. 2c shows a case where the analog input waveform is a rectangular wave. At address 1, display data A is delayed by T, and dot display data on the display data A side including division point D is delayed by T/2. Also, dividing point D
There is no delay on the anti-display data side. At the top of the waveform, since there is display data at addresses 2 and 3, a continuous dot display signal is generated. At address 4, there is no delay on the anti-display data side including dividing point D,
On the display data A side, there is a delay of T/2.

In addition, in order to make the waveform display smoother, the second
When increasing the number of division points according to the embodiment shown in the figure, the division point calculation circuit 18, the comparator 21, the exclusive OR circuit 2, and the delay circuit 23a are arranged in parallel as many as the number of division points, and the dot display signal output circuit 23 is configured as follows. By calculating the number of exclusive OR circuits 22 where g=0, the delay circuit 23a having the required delay time corresponding to the counted value is selected.

〔Effect of the invention〕

As described above, according to the present invention, the dot display signal appearing between the display data of addresses N-1 and N read out in synchronization with the horizontal raster scanning of the display memory is
By displaying dots at an intermediate position through a delay circuit between the dot display positions of address N delayed by the horizontal scanning clock interval T from the dot display position of address N-1, dot display can also be performed between the next address display positions. As a result, a smooth waveform can be displayed in accordance with the original waveform, which is inclined from the dot display position of address N-1 to the dot display position of address N. Furthermore, since all processing is done using digital signals, even if the waveform is spike-like, the amplitude will not be lost.

[Brief explanation of drawings]

FIG. 1a shows a circuit configuration according to the basic principle of the present invention, FIG. 1b is an explanatory diagram of its operation, FIG. 2a is a circuit configuration according to an embodiment of the present invention, and FIGS. 2b and c are explanatory diagrams of its operation. be.

Claims (1)

[Claims] 1. A cathode ray tube that is supplied with horizontal and vertical synchronizing pulses and displays waveforms by horizontal raster scanning, a buffer memory that stores digitized analog input signals, a display memory to which data is transferred from this memory, and a display memory that stores data from this memory. It includes a horizontal synchronization pulse generation circuit that generates the horizontal synchronization pulse every time a number of clock pulses corresponding to the total number of addresses are input, and a vertical synchronization pulse generation circuit that generates the vertical synchronization pulse every time a predetermined number of horizontal synchronization pulses are generated. , a control circuit that causes all addresses of the display memory to be read for each horizontal raster scan and for performing the transfer for each vertical scan; and a control circuit that counts the horizontal synchronization pulses and is reset for each vertical scan. a counter, a first latch circuit that sequentially holds display data of an address N that is sequentially generated by performing the reading from the display memory, and a first latch circuit that holds display data of an address N-1 one address before. In order to Z-divide the output display data of the second latch circuit and the first and second latch circuits, Z-1 division points from address N to display data of N-1 are set as D ₁ and D. ₂ ...
_Z-1 division point calculation circuits that calculate D Z-1, respectively, and comparators that compare the count value n of the counter with the output display data of the first and second latch circuits for each horizontal raster scan. With the output data of this comparator as input, a dot display signal is generated every time a count value n corresponding to the display data of addresses N and N-1 occurs, and of this signal, a dot display signal is generated that matches the display data of address N. The dot display signal at this time is relatively delayed from other dot display signals by a time T (T: the clock pulse interval), and the count value n is compared with each division point Z-1.
of the comparators, the output data of these comparators, and the output data of the comparator following the latch circuit, respectively, and determine whether the count value n is on the display data side of address N with respect to the division point to which it belongs. It consists of Z-1 count value judgment circuits that judge the dot display signal, and Z-1 circuits that have delay times that increase by T/Z for the dot display signal, and dividing points D _Z-1 ...D ₂ , D ₁ , and inputs the output data of the Z-1 count value judgment circuits and outputs the count value n to the address N.
Division points D ₁ , D ₂ ,... to be located on the display data side of
...D A dot display that outputs the dot display signal through the delay circuit corresponding to the dividing point closest to the display data among _Z-1 , or without going through the delay circuit if such a dividing point does not exist. 1. A horizontal raster scanning cathode ray tube waveform display device, comprising: a signal output circuit, and the dot display signal is supplied to the cathode ray tube.