JPH0774810B2 - Waveform display device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a waveform display device that inserts interpolation data between discretely sampled waveform data to reproduce and display a waveform. It relates to improvements in data interpolation.

<Prior Art> For example, a digital oscilloscope is configured to convert an analog input signal into a digital signal, perform various kinds of digital arithmetic processing, and then display it on a display such as a CRT.

Further, this CRT usually has a resolution of 500 to 1000 in the vertical direction. Therefore, in order to display one screen (hereinafter referred to as a frame), sample data having the same resolution as or higher than this resolution is required.

On the other hand, one screen may be displayed using less sampling data Din than a line (hereinafter referred to as a raster) along the vertical resolution of the display device. FIG. 2 shows the relationship among the raster, the sampling data Din, and the displayed data Dout at this time. In FIG. 2, to display 1 / k sample data Din of the number of rasters on one screen (hereinafter referred to as RA) continuously (given data Dout to all rasters), the sampling data It is necessary to generate data (Dout for interpolating data) for displaying k−1 rasters between rasters displaying Din.

Examples of such data interpolation methods include a digital method of calculating interpolation data by performing a product-sum operation by an electronic circuit or software processing based on the concept of a digital filter, or converting sample data into an analog signal. In addition to the analog filter, there is an analog method for converting the output signal into a digital signal again to obtain interpolation data.

<Problems to be Solved by the Invention> However, according to the former method, when an electronic circuit is used, a circuit for performing arithmetic processing such as multiplication becomes complicated,
High-speed elements are required, resulting in high cost, and 1 in the case of software processing when the number of measurement channels increases.
The calculation speed is reduced because of displaying a plurality of data on the raster of the book.

Further, according to the latter method, it is difficult to obtain high accuracy because the digital sampling data is converted into analog again, and it is also difficult to change the interpolation function because the filter is composed of analog.

The present invention focuses on such a point, and an object of the present invention is to provide a waveform display device capable of performing high-speed and high-precision interpolation processing with a relatively simple configuration.

<Means for Solving the Problems> A waveform display device of the present invention is a waveform display device which inserts interpolation data between discretely sampled waveform data and reproduces and displays the data. By inputting and counting a data latch circuit that holds a sampling data of each piece and a horizontal synchronizing signal, a signal for shifting and latching the sample data in the data latch circuit is output to the data latch circuit, A signal that indicates the time difference from the interpolated data is output to the read-only memory described later, sample data is selected at each cycle of an integer multiple of the horizontal sync signal, and the selected signal for selecting and outputting the interpolated data during other periods. Is output to the selector, and a data signal is input by inputting a clock signal and counting with a J-adic counter. A control signal generating circuit having a function of outputting the J number of sampling data held in the circuit to a read-only memory described later and outputting the count output of the J-adic counter to the read-only memory described later; interpolation data and sample data; A read-only memory that stores weighted data based on a time difference between the control signal generating circuit and the sample data from the data latch circuit, and a weighted data from the read-only memory. Based on a select signal from the control signal generating circuit, an adder for adding J data in one cycle of the horizontal synchronizing signal, the interpolation data input from the adder, and the sample data input from the data latch circuit. A selector for selecting and outputting is provided.

<Operation> In the waveform display device according to the present invention, the ROM data is read out as interpolation data based on the control signal obtained by processing the horizontal synchronization signal (the signal synchronized with the time required to display one raster). Therefore, it is possible to obtain interpolation data at high speed with a simple configuration.

<Example> Hereinafter, an example of the present invention is described in detail using a drawing.
FIG. 1 is a configuration explanatory view showing an embodiment of the present invention.
In the figure, reference numeral 1 denotes a memory for storing sample data D _in , and a data latch circuit 2 for latching a required number of sample data for interpolation data is connected to the memory 1. Reference numeral 3 is a control signal generation circuit, which controls the horizontal synchronizing signal and the clock signal necessary for operation to the data latch circuit based on the enlargement ratio (K times) and the number of sample data (J) necessary for generating the interpolation data. The signal (S1), the control signal (S2) to the read-only memory 4, and the selection signal (S3) to the data output control circuit 5 are output. The control signal (S1) is a signal synchronized with the horizontal synchronization signal, which holds the sample data Din input from the memory 1, and is interpolated using a plurality of sample data Din within a period of displaying on one raster. There is a signal with a faster cycle than the horizontal synchronizing signal for performing the calculation. The control signal (S2) is a signal indicating the time relationship between the sample data Din for performing the interpolation calculation and the output interpolation data. The selection signal (S3) has a cycle K times that of the horizontal synchronizing signal, and has sample data Din and interpolation data (○ in FIG. 2).
And x) are signals for selecting.

The data latch circuit 2 outputs the data D ₁ selected from the J sampled data latched to the read-only memory 4 as an address according to the control signal S ₁ applied from the control signal generation circuit 3 and also outputs a certain data. D ₂
Is output to the data output control circuit 5.

Reference numeral 4 denotes a read-only memory, which stores weighted values for data used in interpolation calculation. The value of this weight is determined by the time difference between the interpolation data and the sample data, and is stored in the order in which the values required for the calculation can be extracted by inputting the control signal (S2) and the sample data Din. A data output control circuit 5 inputs a value weighted based on the interpolation calculation output from the read-only memory 4 and adds the necessary number (J) for performing the interpolation calculation. Also, the sample data Din and the interpolation data are selected and output based on the selection signal (S3) output from the control signal generation circuit 3. A CRT 6 displays the data Dout for each raster based on the horizontal synchronizing signal and updates the screen for each frame period.

The operation of the apparatus configured as described above will be described. Indicator 6
For example, the CRT used as is scanned in the vertical direction, the display waveform is updated in synchronization with the frame cycle, and the data interpolation calculation is executed in synchronization with the raster cycle.

Here, assuming that the time axis of the measured waveform is enlarged by K times based on the sample data D _in and displayed, the display data D _out input to the display 6 is, as shown in FIG.
The data is interpolated so that (K-1) rasters indicated by X are inserted between the rasters of the sample data D _in indicated by the mark. That is, the sample data D _in is latched by the shift register 17 every K times the cycle of the horizontal synchronization signal (hereinafter referred to as the raster cycle), but the display data Dout changes every raster cycle. For example, if K = 5, the number of rasters can be represented by s × 5 + i. s represents the number of sample data input from the memory 1 before displaying this raster, and i represents the number of raster from the last raster displaying the sample data.

First, the control signal generation circuit 3 should determine which i is 0, 1, 2, 3, 4 based on the horizontal synchronizing signal and the clock signal, and should use which sample data to perform data interpolation. determine, outputs control signals S ₁ to the data latch circuit 2 in accordance with these determination results, and outputs a control signal S ₂ to the read only memory 4, and outputs a control signal S ₃ to the data output control circuit 5.

The data latch circuit 2 latches the sample data Din at every K times raster period and holds J pieces of data necessary for the data interpolation processing. Then, the data D ₁ is output to the read-only memory 4 according to the control signal S ₁ , and the data output control circuit 5
The data D ₂ is output to.

The read-only memory 4 outputs the corresponding data D ₃ to the data output control circuit 5 using the control signal S ₂ input from the control signal generation circuit 3 and the data D ₁ input from the data latch circuit 2 as an address.

The data output control circuit 5 outputs data every raster cycle, but the sample data D3 is output every K times the raster cycle.
Is displayed and the rest displays interpolation data D2.

FIG. 3 is a circuit diagram showing a specific example of FIG. 1, and the same parts as those in FIG. 1 are designated by the same reference numerals. In the figure, 7 is a raster counter that counts horizontal synchronizing signals, and its count output S ₄ is input to a comparator 8 and a signal generation gate 9. When the comparator 8 detects that the count output S ₄ of the raster counter 7 has reached “J”, it inputs the detection signal S ₅ to the K-adic counter 10. The K-adic counter 10 starts counting the horizontal synchronizing signal when the detection signal S ₅ is input from the comparator 8, and inputs the count output S ₆ to the comparator 11 and the read-only memory 4. The comparator 11 is a raster counter 7 for horizontal sync signals from the start of the frame period.
The output signal S ₇ is output to the signal generation gate 9 every time the count value of is equal to J + nK (n = 1,2,3 ...). 12 is a J-ary counter, a decoder and the count output S ₈ counts the clock signal having a cycle shorter than 1 / J raster cycle
Input to 13 and read-only memory 4. 17 is a shift register cascade-connected to the J stage,
In synchronization with the clock S ₉ input from the signal generation gate 9, the J sample data D _in are sequentially fetched and updated and stored. Reference _numeral 14 denotes J tri-state buffers provided for each shift register, which are selectively driven according to the control signals S _{101 to} S _10J input from the decoder 13 and stored in the corresponding shift register 13. First data D ₁ output from the data latch circuit 2 as sample data
Is input to the read-only memory 4. The read-only memory 4 inputs the data D ₃ corresponding to the input address as described above to the adder 15 constituting the data output control circuit 5. The adder 15 is the count value of the J-adic counter 12.
The data D ₃ output from the read-only memory 4 is added while S ₈ changes from 1 to J, and the result is input to one of the selectors 16 forming the data output control circuit 5 as interpolation data. The data stored in the shift register 17 _{J / 2} is input to the other side of the selector 16 as the second data D ₂ output from the data latch circuit 2. The selector 16 selects the interpolation data input from the adder 15 or the actual sample data input from the shift register 17 _{J / 2} according to the control signal S ₃ output from the signal generation gate 9 of the control signal generation circuit 3. The display data D _out is output to the display 6.

FIG. 4 is a timing chart showing the time relationship of such a series of operations, (a) shows the frame period,
(B) shows a horizontal cycle, (c) shows the control signal S ₉ input from the signal generation gate 9 to each shift register 17,
(D) shows the control signal S ₃ input from the signal generation gate 9 to the selector 16. The control signal S ₉ outputs one pulse for each horizontal period immediately after the start of each frame period until the horizontal period reaches the J period, and thereafter it outputs 1 pulse every horizontal period for the K period. Output pulses. Further, the selector 16 outputs the actual sample data when the control signal S ₃ is at the H level after the sample data D _in is stored in each of the shift registers 17 _{1 to} 17 _j after the start of the frame period, and the selector 16 outputs the L level signal. In the state, the interpolation data input from the adder 15 is output. That is, from the start of each frame period until the count output of the raster counter 7 reaches J, actual sample data is stored in the shift register 17 for each raster period, and thereafter, the output of the K-adic counter 10 is K-.
Until reaching 1, the interpolation data is sequentially output for each raster cycle, and the actual sample data stored in the shift register 17 _{J / 2} is output each time the output of the K-adic counter 10 reaches K.

These relationships will be described in detail with reference to FIG. 5 and mathematical expressions. The number of actual sample data required for interpolation calculation is J (J
Is an even number), the magnification factor of the display is K, and the read-only memory 4 inputs the time data up to the position of the actual sample data D _j and other sample data to be referred to and the position of the interpolation data H _k as an address. Therefore, the specified data is uniquely output.
_k is Shall be calculated according to.

Here, h _kj (D _j ) is an expression based on the idea of the digital filter, and it means that the k-th interpolation is performed for a certain current actual sample data D _{J / 2} and the actual sample data to be referred to. It can be uniquely obtained by determining the time data from the position of D _{j to} the position of the interpolation data H _k .

Accordingly, interpolation calculation processing in the circuit configuration of Figure 3 reads a h _kj stored in the read only memory 4 (D _j), is added to h _kj (D _j) of j = 1 through j = J .

It turns out that.

FIG. 6 is a flowchart showing a flow of operations in one frame period. In the figure, the constants and changes are as follows.

Constant K: Enlargement factor of screen J: Number of reference data required for interpolation calculation RA: Number of rasters in one frame period Variable k: Which raster between sample data Dj and Dj + 1 is the data to be interpolated and displayed Is an integer from 0 to K that represents j: is an integer from 0 to J that represents the time difference between the interpolated data and the sample data DISP: An integer from 1 to RA that represents the number of rasters from the end of the frame D (j): j However, when j ≦ 0, D (j) = 0 DRC (j): the data stored in the jth shift register h (x, y): x, y (where Y = Output data INT: h (x, y) value of read-only memory whose address is D (j)) Value obtained by adding INT from H (k) to J DISP becomes 0 at the start of the frame cycle. However, after the start, 1 is incremented until the condition DISP ≧ J (hereinafter referred to as condition A) is satisfied. When the condition A is satisfied, k = 0, and the actual sample data stored in the J / 2-th shift register is output to the display. Then, calculation processing of the interpolation data is performed. In the interpolation data calculation process, k is incremented by 1 until the condition of k = K-1 (hereinafter referred to as condition D) is satisfied, and j is incremented by 1 until the condition of j = J (hereinafter referred to as condition B) is satisfied. Is added. Then, when the condition B is satisfied, H (k) is output to the display. The processing of the frame cycle ends when the condition of J + (DISP-J) * K + k = RA (hereinafter referred to as condition C) is satisfied, but until the condition C is satisfied, the condition D described above is satisfied. The presence / absence is judged, and if the condition D is not satisfied, the process from the start step of the interpolation data calculation process is repeatedly executed, and if the condition D is satisfied, the process from the frame cycle start step is repeatedly executed. .

With this configuration, the interpolation processing operation can be realized with a relatively inexpensive read-only memory without using an expensive circuit element or a microprocessor. In such an interpolation calculation process, only the time for reading the data from the read-only memory and the time for performing the addition calculation are required, and the processing time of the entire interpolation calculation can be significantly shortened and a high-speed interpolation calculation process can be realized.

Since the part that determines the function for the interpolation calculation is the read-only memory, the function can be easily changed.

<Effects of the Invention> As described above, according to the present invention, it is possible to realize a waveform display device capable of high-speed and high-precision interpolation processing with a relatively simple configuration, and the practical effects are great.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation explanatory diagram of FIG. 1, FIG. 3 is a block diagram showing a concrete example of FIG. 1, and FIG. 4 is a diagram of FIG. A timing chart for explaining the operation, FIG. 5 is an operation explanatory view of FIG. 3, and FIG.
It is a flowchart which shows the flow of operation of the figure. 1 ... Memory, 2 ... Data latch circuit, 3 ... Control signal generating circuit, 4 ... Read-only memory, 5 ... Data output control circuit, 6 ... Display unit.

Claims (1)

[Claims] 1. A data latch circuit for holding J sampling data and a signal for shifting and latching sample data in the data latch circuit by inputting and counting a horizontal synchronizing signal to the data latch circuit. Output the signal indicating the time difference between the sample data and the interpolated data to the read-only memory, which will be described later, and select the sample data every cycle of an integer multiple of the horizontal sync signal, and select the interpolated data during other periods. A function of outputting a selection signal to be output to a selector, and a J-ary counter is used to selectively output J sampling data held in the data latch circuit to a read-only memory described later. And the function of outputting the count output of the J-adic counter to the read-only memory described later. A control signal generating circuit for storing the weighted data based on the time difference between the interpolation data and the sample data, and a read for address-inputting the signal from the control signal generating circuit and the sample data from the data latch circuit. An only memory, an adder for adding J pieces of weighted data from the read only memory within one cycle of a horizontal synchronizing signal, interpolation data input from the adder, and sample data input from the data latch circuit And a selector for selecting and outputting the signal based on a selection signal from the control signal generating circuit.